Journal ArticleDOI
The impact of data-line interference noise on DRAM scaling
Y. Nakagome,Mayu Aoki,Shinichi Ikenaga,Masashi Horiguchi,Shinichiro Kimura,Yoshifumi Kawamoto,K. Itoh +6 more
TLDR
It is found that the interference noise plays a dominant role in determining the operating margin of the DRAM and that a novel process or a cell array architecture for minimizing the interferencenovelity is indispensable in 16-MbDRAM and beyond.Abstract:
A kind of data-line (DL) interference noise in a scaled DRAM cell array is found and studied through analysis. The dynamic behavior of cell arrays due to sense-amplifier operation is derived analytically. Analysis shows that the amount of interference noise is more than three times larger than expected from simple data-line coupling. A novel experimental technique for precise noise determination is developed to verify the analysis. Analytical results are in good agreement with the experimental data. It is found that the interference noise plays a dominant role in determining the operating margin of the DRAM and that a novel process or a cell array architecture for minimizing the interference noise is indispensable in 16-Mb DRAM and beyond. >read more
Citations
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Journal ArticleDOI
RAIDR: Retention-Aware Intelligent DRAM Refresh
TL;DR: This paper proposes RAIDR (Retention-Aware Intelligent DRAM Refresh), a low-cost mechanism that can identify and skip unnecessary refreshes using knowledge of cell retention times and group DRAM rows into retention time bins and apply a different refresh rate to each bin.
Proceedings ArticleDOI
An experimental study of data retention behavior in modern DRAM devices: implications for retention time profiling mechanisms
TL;DR: A comprehensive quantitative study of retention behavior in modern DRAMs is presented, using a temperature-controlled FPGA-based testing platform, and two significant phenomena are observed: data pattern dependence, where the retention time of each DRAM cell is significantly affected by the data stored in other DRAM cells, and variable retention time, where some DRAM Cells' retention time changes unpredictably over time.
Journal ArticleDOI
Trends in low-power RAM circuit technologies
K. Itoh,K. Sasaki,Y. Nakagome +2 more
TL;DR: In this article, a general description of power sources in a RAM chip, and covers both DRAMs and SRAMs, is discussed, and the authors also show that the application of subthreshold current reduction circuits (such as source-gate back biasing) to cell and iterative circuit blocks is indispensable in the future.
Journal ArticleDOI
An experimental 1.5-V 64-Mb DRAM
Y. Nakagome,Tanaka Haruhiko,Kan Takeuchi,E. Kume,Y. Watanabe,Toru Kaga,Yoshifumi Kawamoto,Fumio Murai,R. Izawa,Digh Hisamoto,T. Kisu,Takashi Nishida,Eiji Takeda,K. Itoh +13 more
TL;DR: In this paper, an accurate and speed-enhanced half-V/sub CC/ voltage generator with a current-mirror amplifier and tri-state buffer is proposed to reduce data transmission delay.
Journal ArticleDOI
A high-speed clamped bit-line current-mode sense amplifier
T.N. Blalock,Richard C. Jaeger +1 more
TL;DR: In this article, a clamped bit-line current-mode sense amplifier that maintains a low-impedance fixed potential on the bit lines is introduced, which is achieved by relocating the large bitline capacitance to a node within the sense amplifier, with only a minimal effect on the speed of the circuit.
References
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Journal ArticleDOI
A 5 V-only 64K dynamic RAM based on high S/N design
TL;DR: A 5 V-only 64K dynamic RAM is designed and fabricated using double poly-Si technology based on the 3 /spl mu/m design rule, with a typical access time of 120 ns and a 170 mW operating power, with minimized sense noise of less than 50 mV.
Proceedings ArticleDOI
An Experimental 16mb Dram with Transposed Data-Line Structure
TL;DR: Experimental data indicate that these problems represent major limiting factors for 16Mb DRAMs and a transposed data-line structure for array noise suppression and a negative feedback preamplifier for the I/O lines for highspeed data transmission is proposed.