Journal ArticleDOI
Theory of transparent BIST for RAMs
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TLDR
The theoretical analysis shows that this transparent BIST technique does not decrease the fault coverage for modeled faults, it behaves better for unmodeled ones and does not increase the aliasing with respect to the initial test algorithm.Abstract:
I present the theoretical aspects of a technique called transparent BIST for RAMs. This technique applies to any RAM test algorithm and transforms it into a transparent one. The interest of the transparent test algorithms is that testing preserves the contents of the RAM. The transparent test algorithm is then used to implement a transparent BIST. This kind of BIST is very suitable for periodic testing of RAMs. The theoretical analysis shows that this transparent BIST technique does not decrease the fault coverage for modeled faults, it behaves better for unmodeled ones and does not increase the aliasing with respect to the initial test algorithm. Furthermore, transparent BIST involves only slightly higher area overhead with respect to standard BIST. Thus, transparent BIST becomes more attractive than standard BIST since it can be used for both fabrication testing and periodic testing.read more
Citations
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References
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Journal ArticleDOI
Efficient Algorithms for Testing Semiconductor Random-Access Memories
TL;DR: A fault model which views faults in semiconductor random-access memories at a functional level instead of at a basic gate level is presented and an efficient 0(n) algorithm to detect all faults in the fault model is described.
Journal ArticleDOI
Measures of the Effectiveness of Fault Signature Analysis
TL;DR: A linear feedback shift register can be used to compress a serial stream of test result data and it is possible for an erroneous bit stream and the correct one to result in the same signature.
Journal ArticleDOI
A March Test for Functional Faults in Semiconductor Random Access Memories
TL;DR: It is shown that the proposed test procedure detects modeled types of functional faults if only one type of fault is present in the RAM under test.
Journal ArticleDOI
Testing Memories for Single-Cell Pattern-Sensitive Faults
TL;DR: It is demonstrated that minimum-length SPSF tests can be inherently asymmetric and interpreted as polyominoes.