Journal ArticleDOI
Two-Stage Newton–Raphson Method for Transistor-Level Simulation
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TLDR
An efficient transistor-level simulation tool with SPICE-accuracy for deep-submicrometer very large-scale integration circuits with strong-coupling effects with orders-of-magnitude speedup over Berkeley SPICE3 is observed.Abstract:
In this paper, we introduce an efficient transistor-level simulation tool with SPICE-accuracy for deep-submicrometer very large-scale integration circuits with strong-coupling effects. The new approach uses multigrid for huge networks of power/ground, clock, and interconnect with strong coupling. Mutual inductance can be incorporated without error-prone matrix sparsification approximations or expensive matrix inversion. Transistor devices are integrated using a novel two-stage Newton-Raphson method to dynamically model the linear network and nonlinear devices boundary. Orders-of-magnitude speedup over Berkeley SPICE3 is observed for sets of real deep-submicrometer design circuitsread more
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Book
Electronic Design Automation: Synthesis, Verification, and Test
TL;DR: EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits.
Journal ArticleDOI
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Patent
Hierarchical Order Ranked Simulation Of Electronic Circuits
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References
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Proceedings ArticleDOI
An efficient inductance modeling for on-chip interconnects
TL;DR: The table-based inductance model has been integrated with a statistically-based RC model generation to generate RLC models for on-chip interconnects and is efficient enough to be used during iterative procedures of interconnect simulation and layout optimization.
Journal ArticleDOI
Piecewise approximate circuit simulation
Chandu Visweswariah,R.A. Rohrer +1 more
TL;DR: The SPECS simulator as discussed by the authors is a piecewise approximate, tree/link based, event driven, variable accuracy circuit simulation algorithm that uses table models for device evaluation and can be built at various levels of accuracy.
Proceedings ArticleDOI
On-chip inductance modeling and analysis
TL;DR: A detailed circuit model composed of interconnect resistance, inductance and distributed capacitance, device decoupling capacitances, quiescent activity in the grid, pad locations, and pad/package inductance is proposed which accurately determines current distribution and, hence, on-chip inductive effects, and proves superior to the traditional simplified loop inductance approach.
Journal ArticleDOI
Adaptively controlled explicit simulation
Anirudh Devgan,R.A. Rohrer +1 more
TL;DR: A new adaptively controlled explicit integration approximation is used that overcomes stability problems encountered in earlier explicit techniques, and circuit partitioning is employed, which allows event driven simulation and exploitation of circuit latency.
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