scispace - formally typeset
Journal ArticleDOI

Voltage difference engineering in SOI MOSFETs: A novel side gate device with improved electrical performance

Reads0
Chats0
TLDR
In this article, the authors studied the impact of voltage difference engineering in a silicon-on-insulator metal oxide semiconductor field effect transistor (SOI-MOSFET) and compared the performance to that of a conventional C-SOI.
About
This article is published in Materials Science in Semiconductor Processing.The article was published on 2013-12-01. It has received 7 citations till now. The article focuses on the topics: Drain-induced barrier lowering & Reverse short-channel effect.

read more

Citations
More filters
Journal ArticleDOI

Analysis of a high-performance ultra-thin body ultra-thin box silicon-on-insulator MOSFET with the lateral dual-gates: featuring the suppression of the DIBL

TL;DR: In this article, an inspiring ultra-thin box silicon-on-insulator (UTBB SOI) MOSFET with enhanced immunity to drain-induced barrier lowering (DIBL) is analyzed.
Journal ArticleDOI

High performance multi-channel MOSFET on InGaAs for RF amplifiers

TL;DR: In this article, a multi-channel MOSFET (MC-MOS-FET) was proposed for RF amplifier applications, which has two vertical gates placed in trenches creating multiple channels in p-body for parallel conduction of drain current.
Journal ArticleDOI

Simulation analysis of a novel fully depleted SOI MOSFET: Electrical and thermal performance improvement through trapezoidally doped channel and silicon–nitride buried insulator

TL;DR: In this article, a dual material buried insulator vertical trapezoidal doping SOI MOSFET (DV-SOI) was proposed to reduce the self-heating effect.
Journal ArticleDOI

Comparison of the performance improvement for the two novel SOI-tunnel FETs with the lateral dual-gate and triple-gate

TL;DR: In this article, the authors presented two silicon-on-insulator tunnel field effect transistors (SOI-TFETs), referred as a lateral dual-gate and a lateral triple-gate TFET, which consist of one or two vertical thin vertical dielectric layers within the original front-gate region.
Proceedings ArticleDOI

Investigation of a nanoscale grooved stepped gate MOSFET to explore the self-heating effect

TL;DR: In this article, a new grooved gate silicon-on-insulator (GG-SOI) MOSFET with multi-layered (SiO 2 /Si 3 N 4 /Si O 2 ) buried insulator structure was proposed to reduce self-heating effect (SHE).
References
More filters
Proceedings Article

Physics of semiconductor devices

S. M. Sze
Journal ArticleDOI

Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs

TL;DR: In this article, a 2D analytical model for the surface potential variation along the channel in fully depleted dual-material gate silicon-on-insulator MOSFETs is developed to investigate the short-channel effects (SCEs).
Journal ArticleDOI

Double-gate CMOS: symmetrical- versus asymmetrical-gate devices

TL;DR: In this article, numerical device-simulation results, supplemented by analytical characterizations, are presented to argue that asymmetrical double-gate (DG) CMOS, utilizing n/sup +/ and p/sup+/ polysilicon gates, can be superior to symmetrical-gate counterparts for several reasons, only one of which is its previously noted thresholdvoltage control.
Book

Physics of semiconductor devices

TL;DR: In this article, the PN junction diode and MOS transistor are discussed. And the Bipolar Transistor and Bipolar transistor have been shown to have similar properties.
Journal ArticleDOI

A Tunnel Diode Body Contact Structure to Suppress the Floating-Body Effect in Partially Depleted SOI MOSFETs

TL;DR: In this paper, a novel SOI MOSFET structure to suppress the floating-body effect (FBE) and the short-channel effects is proposed and successfully demonstrated, which does not enlarge the device size and is fully compatible with SOI CMOS technology.
Related Papers (5)