Showing papers on "Biasing published in 1988"

Microstrip phase scan antenna array

Abstract: A microstrip phase scan antenna array is provided having a columnar array microstrip radiating patches mounted on a dielectric substrate. Each column of the array is fed by a separate variable, reciprocal ferrite rod phase shifter which is mounted on the substrate and is coupled to the column which it controls and to a source of millimeter wave energy by microstrip to dielectric waveguide transitions. Each of the phase shifters is controlled by a helical biasing coil surrounding the ferrite rod. All of the biasing coils are serially interconnected by a single scanning control drive wire and the numbers of turns of the coils are related to each other by an arithmetic progression in which the number of turns of a particular biasing coil differs from the number of turns of the adjacent biasing coil in the sequence of biasing coils controlling the array by a constant amount.

Resonant tunneling and intrinsic bistability in asymmetric double‐barrier heterostructures

Abstract: We report measurements of the current‐voltage characteristics of an asymmetric GaAs/AlGaAs double‐barrier resonant tunneling device. The structure was designed to increase the space charge in the well under forward bias and consequently enhance the electrostatic feedback that leads to intrinsic bistability. The magnetotunneling data demonstrate unambiguously that the observed bistability is the property of the device, rather than the biasing circuit.

Depth dependence for extended x-ray-absorption fine-structure spectroscopy detected via electron yield in He and in vacuum

Abstract: X-ray absorption spectra have been measured using electron detection with both vacuum and helium gas surrounding the samples. The samples consisted of thin iron films covered with various thicknesses of aluminum to determine the contribution versus depth. The height of the iron K--absorption-edge jump decreases exponentially with aluminum covering thickness, with a 1/e depth of 1600 A. The addition of helium gas forms an ionization detector for the electrons, which have an average energy of about 2500 eV. The effects of electrode geometry and bias voltage are evaluated. When operated in a linear-response region, the signal-to-noise ratio for this method is excellent and the extended x-ray-absorption fine-structure (EXAFS) amplitudes agree with transmission measurements to better than 3%.

Voltage-dependent scanning tunneling microscopy imaging of semiconductor surfaces

Abstract: We present voltage-dependent scanning tunneling microscopy (STM) data from various semiconductor surfaces. Different techniques for acquiring the data are demonstrated, and the interpretation of spectroscopic data is discussed. For the Si(111)2 × 1, GaAs (110), and O/ GaAs(110) surfaces, we find that the voltage dependence of constant-current contours provides the most direct method for understanding the electronic and geometric structure of the surface. For the case of oxygen on n-type GaAs, we observe a reversal in the constant-current contours when the polarity of the bias voltage is reversed, which is interpreted in terms of band bending due to a negatively charged adsorbate. Theoretical calculations for a screened Coulomb potential are shown to agree with the observed reversal in the STM contours of the adsorbed oxygen.

Image forming device

Abstract: PURPOSE:To automatically adjust a control basic voltage value to a set voltage value by comparing the control basic voltage value for determining a developing bias voltage with the set voltage value and changing the control basic voltage based on its deviation output to adjust the developing bias voltage. CONSTITUTION:A scanning exposure lamp 101 is turned on and the reference voltage value VO of the control basic voltage applied from an amplifier circuit 104 through an adjusting circuit 2 is inputted to a central processing unit (CPU) 305 through an A/D converter 304 and compared with the set voltage value VS. In case of VOnot equal to VS, the deviation (e) of both values is calculated, the variation DELTAT in the time width of a clock pulse TP outputted from a PWM timer 302 is calculated by multiplying the deviation (e) by a constant of proportion K and a new TP is written in the PWM timer 302. Thus, the voltage is controlled by executing the loop operation so that VO=VS is formed. Consequently, the control basic voltage VO outputted from the amplifier circuit 104 is controlled in accordance with an original ground density (OD) and the developing bias voltage value VB is adjusted.

Identification and implication of a perimeter tunneling current component in advanced self-aligned bipolar transistors

Abstract: The identification of a perimeter tunneling current in the base-emitter junction of advanced double-poly self-aligned bipolar transistors has been verified by measuring based current as a function of temperature, bias voltage, and device perimeter-to-area ratio The perimeter tunneling current at forward bias is found to be predominantly an excess tunneling that depends on the sidewall oxide interface properties, while that at reverse bias is due to band-to-band tunneling resulting from the emitter and extrinsic base profile overlap Based on experimental results and an analysis of base-leakage-current trade-offs at forward and reverse bias, a device design concept was developed to enhance device performance and processing yield in scaled bipolar transistors >

Dual channel high electron mobility field effect transistor

Abstract: A multi-terminal Group III-V semiconductor high electron mobility field effect transistor comprised of a sandwich of molecular beam epitaxially grown layers and including two high mobility charge flow channels in respective two dimensional electron gas regions implemented, for example, by at least one doped layer of aluminum gallium arsenide adjacent an undoped gallium arsenide layer separated by a heterojunction. A pair of opposing two dimensional electron gas (2DEG) regions are generated in the layer of undoped gallium arsenide by the bending of the energy levels of the semiconductor materials. Charge flow occurs in a unidirectional fashion from one channel to the other in the common undoped gallium arsenide layer under the control of an electric field applied transversely through the structure by means of a top gate electrode and a bottom field plate electrode. Alternatively, the source voltage can be increased until the requisite amount of energy has been provided for the electrons to become "hot" enough to transfer from one channel to the other, in which case a lower biasing contact is not required. Relatively high signal isolation is inherently provided thereby between a pair of output terminals or signal ports. The device, moreover, is operable as a high speed signal coupler, amplifier, mixer as well as a photoelectric detector/amplifier.

A low-distortion output stage with improved stability for monolithic power amplifiers

Abstract: A low-distortion class AB output stage with improved stability suitable for monolithic power amplifiers (P/sub 0/>or=40 W) is described. The concept has been verified on a 12-W breadboard version as well as on a partly integrated prototype, and is supported by computer simulations for P/sub 0/>or=40 W A biasing control law which guarantees predictable conduction of both output transistors at all times is implemented. This reduces crossover distortion and allows the customary quasi-p-n-p compound transistor to be eliminated, thus also improving stability. Linearity is improved by use of local negative feedback. Phase margin is improved by application of high-frequency feedforward. Measured phase margin is around 60 degrees and total harmonic distortion for a load of 7 Omega is about -80 dB at 20 kHz. >

Electro-optic waveguide device

Abstract: An electro-optic waveguide device (10) comprises an assembly of waveguides (30) connected to a common light input region (41) and forming a common far field diffraction pattern (44). The device (10) comprises an n+ GaAs substrate (14) bearing a waveguide lower cladding layer (16) of n+ Ga0.9Al0.1As, which is in turn surmounted by a waveguide core layer (18) of n- GaAs. The layer (18) has grooves (20) defining the waveguides (30), each of which has a respective Schottky contact (32). Each contact (32) is biased negative with respect to the substrate (14), which reverse biases the respective Schottky diode waveguide structure. The waveguide core layer (18) has electro-optic properties, and its refractive index varies with electric field. The phase of light emerging from each waveguide is therefore independently variable by means of its applied bias voltage. The waveguides (30) are arranged to provide output confined very largely to lowest order spatial modes, so that they produce a single far field diffraction pattern (44). Varying the set of bias voltages applied to the waveguides (30) produces output phase variation which changes the position of the diffraction pattern principal maximum (46) to produce beam steering.

The abrasive wear resistance of sputter ion plated titanium nitride coatings

Abstract: Previous work has shown that under abrasive wear conditions it is not sufficient to consider coating hardness in isolation when seeking a guide to coating selection; it is more meaningful to talk in terms of the load-bearing capacity of the coating-substrate system. For titanium nitride coatings deposited onto austenitic stainless steel the variation in resistance to abrasive wear has been evaluated as a function of substrate bias voltage and the results have been compared with these earlier studies. Substrate bias has been identified as a particularly important system's parameter, since it allows some stress relaxation to occur within the coating because of its effect on porosity levels; this has important consequences with regard to adhesion, wear resistance and film hardness. With low substrate bias voltages, coatings degrade by a microchipping mechanism since fracture occurs relatively more easily in such open columnar microstructures, which are further characterized by low levels of internal stress accompanied by a poor load-bearing capacity. With increasing substrate bias much denser coatings are produced which result, initially, in better resistance to abrasive wear through increased load support. However, these improvements in coating microstructure result in higher levels of internal stress and these, when taken along with a reduction in the scratch adhesion critical load for failure Lc, eventually lead to a decrease in abrasive wear resistance with increasing bias voltage. The mechanism(s) by which the coatings degrade are described as a function of substrate bias, and the results are correlated with measurements of hardness, internal stress and critical load for coating detachment.

Power supply apparatus capable of multi-mode operation for an electrophoretic display panel

Abstract: There is disclosed a multi-mode power supply for biasing an electrophoretic display and particularly for biasing the anode electrode of such a display. The supply contains first and second supply means each of which can operate as a constant voltage or constant current supply. The first and second supplies are respectively coupled to the anode electrode of the electrophoretic display so that during the Write Mode the display is operated with a constant current at a first polarity and operates with a constant current at a second polarity during the Erase Mode. Additional modes are shown where AC voltages are applied to the anode electrode either directly as in the case of a Slow Erase Mode or via a capacitor in the case of a Time 60 Cycle Mode for a given time period. In these modes the supplies are operated as constant voltage sources to enable suitable magnitude voltages to be applied to the anode electrode in order to provide optimum operating conditions for the electrophoretic display.

Noninvasive method and apparatus for characterization of semiconductors

Abstract: A method and apparatus are described for characterizing a semiconductor using the surface photovoltage (SPV) effect. A region of the surface of the semiconductor is illuminated with an intensity modulated beam of light, the wavelength of the light being shorter than that corresponding to the energy gap of the semiconductor. The surface photovoltage (SPV) induced in the semiconductor is measured under bias voltage conditions. The intensity of the light beam and the frequency of modulation are selected such that the surface photovoltage (SPV) is directly proportional to the intensity and reciprocally proportional to the frequency of modulation. Using the surface photovoltage (SPV) and the bias voltage (V g ) measurements, the charge induced in the semiconductor space charge region (Q sc ) and the charge induced in the semiconductor (Q ind ) are determined. This information is used to determine various parameters of the semiconductor including surface state density and oxide/insulator charge. The technique is designed especially for use in characterizing semiconductor wafers, coated or uncoated, but may, if desired, also be used in characterizing MIS or MOS type semiconductor devices.

Simulation of hot-electron trapping and aging of nMOSFETs

Abstract: An analysis of the degradation of 1- mu m-gate-length nMOSFET operating under normal biasing conditions at room temperature is reported. A physical model of hot-electron trapping in SiO/sub 2/ is developed and is used with a two-dimensional device simulator (PISCES) to simulate the aging of the device under normal biasing conditions. The initial degradation takes place near the high-field drain region and spreads over a long time toward the source. The degraded I-V characteristics of the MOSFET exhibit a shift of the pinchoff voltage and a compression of the transconductance, for forward and reverse operation, respectively. The simulated degradation qualitatively agrees with reported experimental data. Large shifts of the MOSFET threshold voltage for small drain voltages result as the degradation is spreading toward the source. An inflection point arises for low gate and drain voltages in the drain I-V characteristics of the MOSFET. This inflection point originates when the pinchoff of the channel-induced trapped-electron charge is overcome by the drain voltage; the drain acts as a second gate (short-channel effect). The estimation of the device's lifetime by simulated aging is proposed. >

Protective circuit for a magnetoresistive element

Abstract: A protective circuit for a magnetoresistive (MR) element having a first and a second terminal in which a first current source is coupled to the first terminal of the MR element to produce a bias current through the MR element and a second current source is coupled to the second terminal of the MR element to produce a reference current. Circuit means coupled across the MR element senses the center potential of the MR element substantially midway between the first and second terminals, and a feedback circuit responsive to the sensed center potential is coupled to adjust the current output of the first current source to maintain the center potential to a selected reference voltage to protect the MR element from short circuits to a conductive area of the magnetic recording medium. A second feedback circuit is provided which comprises a pair of transistors coupled in a differential pair configuration and a transconductance stage which feeds back a signal as a current to the transistors which keeps the dc currents through each of the transistors equal, and the transistors provide an amplified output signal which is a function of the magnetic flux being sensed by the MR element.

Level shift circuit for converting a signal in an ecl level into a signal in a CMOS logic level

Abstract: A level shift circuit is made up of a capacitor, a MOS inverter, and a bias circuit for applying a bias voltage to an input node of the MOS inverter. A first electrode of the capacitor is connected to an output stage of an ECL circuit, while a second electrode to the input node of the MOS inverter. The output node of the MOS inverter is coupled with an input stage of a CMOS circuit. An output signal of the ECL circuit is capacitively coupled with the input node of the MOS inverter so that it is superposed onto a bias voltage being supplied from the bias circuit. A level of this signal is shifted to a CMOS logic level by the MOS inverter, and then applied to the input stage of the CMOS circuit.

Laser driver circuit

Abstract: A laser driver circuit is disclosed for operating an electrical current driven light emitting device or laser The laser driver circuit is driven from external equipment by a modulated electrical signal and includes a laser biasing network arranged to provide a threshold current to the laser The current is sufficient to bias the laser to an operating point just below the laser's turn on threshold First and second transistors connected to the laser form a differential switching amplifier The differential switching amplifier is disposed to switch drive current provided by a constant current source to the laser The drive current is sufficient to drive the laser over the threshold set by the laser biasing network On the application of the modulated electrical signal to the first transistor of the differential switching amplifier the drive current is switched from one side of the differential switching amplifier to the other effectively turning the laser on and off

Magnetoresistive sensor with improved antiferromagnetic film

Abstract: An improved thin film magnetoresistive (MR) sensor uses an alloy comprising Fe, Mn and Cr as an antiferromagnetic layer to provide a longitudinal exchange bias in the ferromagnetic MR layer. Sufficient exchange biasing is provided and the FeMnCr layer exhibits excellent corrosion resistance.

Transverse magnetic field dependence of the current‐voltage characteristics of double‐barrier quantum well tunneling structures

Abstract: We report the effects of a transverse magnetic field (J⊥B) on the conductivity of quantum well tunneling structures based on AlGaAs/GaAs/AlGaAs quantum wells. The current‐voltage characteristics in the positive differential resistance regime show negative magnetoconductance for all values of B. The peak bias voltage increases monotonically with increasing B. For B 6 T. The data also show dramatic magnetic field induced changes in the negative differential resistance (NDR) features. The behavior of the NDR changes from sharp hysteretic bistable‐like transitions to astable NDR transitions. Both the valley current and its bias voltage position increase with increasing magnetic field. This behavior is described by a simple model that includes magnetic field effects across the barriers.

Light-to-light transducers with amplification

Abstract: A device considered as a light-to-light transducer with amplification has been proposed and fabricated. The device structure is direct and has vertical (but offset) integration of a heterojunction phototransistor onto a cladding layer of a double-heterojunction light-emitting diode on one side of a substrate. Light amplification becomes possible by combining a transistor function and a light-emitting function. A gain of 15 times has been measured against an input-light-power of 10 mu W at 1.15- mu m wavelength, at a bias voltage of 4.25 V, and with a load resistance of 5 Omega . With the utilization of the Early effect in the weak-input-power range and the suppression of a regenerative effect in the intermediate-power range, an amplification characteristic close to the linear relation has been realized, for the first time, for an input light power from 0 to 20 mu W, at a bias voltage of 4.0 V and with a load resistance of 5 Omega . >

Tethered rocket experiment (Charge 2): Initial results on electrodynamics

Abstract: The tethered mother-daughter rocket experiment (Charge 2) was carried out by a NASA sounding rocket, Black Brant 9, at White Sands Missile Range in New Mexico in December 1985. It was intended to perform a new type of active experiment in space by applying a high voltage between the two payloads, as well as by injecting an electron beam from the tethered rocket system. An insulated conductive wire connecting the two payloads was deployed up to its maximum length of 426 m during the flight. An electron beam from 0.5 to 48 mA at 1 keV was injected from the mother payload. A voltage up to 500 V was applied between the two payloads with and without the beam injection. This paper describes the initial results on the electrodynamic effects induced by the potential difference between the two payloads. Measurements of the v×B electromotive force and the voltage/current characteristics up to 500 V have been explained by a model in which the ion current to the negatively biased payload effectively limited the tether current. Two kinds of VLF waves were observed when the bias voltage was applied between the two payloads; narrow-band emission at 2–4 kHz and broadband emission up to 15 kHz, depending on the applied voltage. The characteristic features of these emissions suggest that the lower hybrid instability (modified two-stream instability) driven by the potential difference between the rocket and the ambient plasma was responsible for the wave generation.

Temperature compensated monolithic delay circuit

Abstract: A temperature and processing compensated time delay circuit of the type which can be fabricated in a monolithic integrated circuit utilizes a field effect transistor (FET) (12) connected to the terminals of a charged capacitor (14). A bias voltage connected to the gate of the FET (12) varies with temperature in a manner to compensate for the changes in current which flows from the capacitor (14) through the FET (12) due to changes in temperature. The bias voltage also varies from one integrated circuit to another in a manner to compensate for variations in FET threshold voltage caused by variations in the processing of the integrated circuits.

Silicon double‐injection electro‐optic modulator with junction gate control

Abstract: Novel structures for carrier‐induced electro‐optical phase modulation in crystalline silicon are examined. A new dual‐injection field‐effect transistor structure for guided‐wave light modulation at 1.3 μm is proposed and analyzed. It consists of an elongated cathode‐anode‐gate structure integrated in a rib waveguide. Dual‐gate and single‐gate control are considered. The overlap between the plasma charge density and the optical guided mode is computed. For a cathode‐anode voltage of 0.32 V, the effective refractive index of the waveguide mode changes by ΔN=1×10−3 when the gate voltage is altered by 12 V. Numerical estimates of the bias current, pinchoff voltage, interaction length, and modulator speed are given.

Method for driving a photo-sensor by applying a pulse voltage to an auxiliary electrode during a non-read time

Abstract: A method for driving a photo-sensor to produce an improved, stable output which exactly represents the incident light is disclosed The photo-sensor has a pair of main electrodes found on a semiconductor layer with a photo-sensing area arranged therebetween A semiconductor layer and an auxiliary electrode are formed on at least the photo-sensing area with an insulating area being interleaved therein The auxiliary electrode is used for stabilizing the photosensing output and providing a signal proportional to the incident light The method of driving such a photo-sensor includes applying a bias voltage to the auxiliary electrode in accordance with the carriers carrying a current of the semiconductor layer A voltage of the same polarity as that of the bias voltage, but smaller in absolute value, is applied to the auxiliary electrode for a predetermine period of time in a non-read period of the photo-sensor to cause a next photo-sensor output to be read while a previous photo-sensor has been erased

Temperature control of light-emitting devices

Abstract: The temperature of the junction of a light-emitting semiconductor junction device 1 (e.g. an LED or laser diode) is measured by using the forward bias voltage/current characteristic of the device to provide an indication of the junction temperature and then controlling the temperature of the junction to a predetermined value in order to stabilise the output wavelength of the device. As shown the forward bias current of the device is measured by ammeter 3 and the forward voltage is measured by voltmeter 4. A signal processor 5 calculates the junction temperature and controls a temperature controller 6 to heat or cool the device. Alternatively the signal processor 5 may control the current source 2 and thereby vary the temperature of the junction by direct heating.

Novel CMOS current Schmitt trigger

Abstract: A novel CMOS current Schmitt trigger based on current mirrors is presented, using only seven MOS transistors. The significant feature of the circuit is that one threshold current is controlled by a bias current and the other by an MOS transistor dimension, depending on the circuit implementation. A design example and the simulation results are given.

Four-hundred-picosecond single-photon timing with commercially available avalanche photodiodes

Abstract: Avalanche photodiodes biased above the breakdown voltage are an interesting alternative to photomultiplier tubes in time‐correlated single‐photon counting. The characteristics and performance of a commercially available device (RCA C30921S) have been investigated. The time resolution is found to improve as the excess bias above the breakdown voltage is increased. Full width at half‐maximum values down to 400 ps have been measured with the detector cooled at −40 °C, and down to 460 ps at room temperature. The best results were obtained with an active quenching circuit, suitable for operation with excess bias voltage up to 40 V; at room temperature, fast gated operation was used for attaining optimum performance. Experimental data on the statistical behavior of the avalanche current pulses in these devices are reported and discussed.

High breakdown active device structure with low series resistance

Abstract: Series resistance in the low impurity portion of a high breakdown PN junction of a three or four layer device is reduced by providing an increased impurity region at the junction of the same conductivity type as the low impurity portion and having an impurity profile such that the increased impurity region is depleted under reverse biasing before critical field is reached therein. The three layer device include insulated gate field effect transistors and bipolar devices and the four layer device is an SCR.

Biasing circuit for generating precise currents in an integrated circuit

Abstract: An integrated circuit chip is fabricated with an operational active device and a nearly-identical, exemplary active device. The exemplary device is connected in series with a current reference element so that current flow through the reference element will be substantially duplicated in the exemplary device. A difference amplifier senses the output voltage of the exemplary device; compares it to a provided reference voltage; and generates a gate biasing level at the gate of the exemplary device to force the output voltage of the exemplary device substantially equal to the reference voltage. The biasing level at the gate of the exemplary device is duplicated at the gate of the operational device thereby creating a condition wherein the output current of the operational device will be a substantially precise replica of the current flow through the reference element when the reference voltage is duplicated across the output of the operational device.