Showing papers on "Bipolar junction transistor published in 1988"

Silicon-germanium base heterojunction bipolar transistors by molecular beam epitaxy

Abstract: The devices were fabricated using molecular-beam epitaxy (MBE), low-temperature processing, and germanium concentrations of 0, 6%, and 12%. The transistors demonstrate current gain, and show the expected increase in collector current as a result of reduced bandgap due to Ge incorporation in the base. For a 1000-AA base device containing 12% Ge, a six-times increase in collector current was measured at room temperature, while a 1000-times increase was observed to 90 K. The temperature dependence of the collector current of the Si/sub 0.88/Ge/sub 0.12/ base transistor is consistent with a bandgap shrinkage in the base of 50 meV. For the homojunction transistors, base widths as thin as 800 AA were grown, corresponding to a neutral base width of no more than 400 AA. >

An analytical model for the steady-state and transient characteristics of the power insulated-gate bipolar transistor

Abstract: An analytical model for the power Insulated-Gate Bipolar Transistor (IGBT) is developed. The model consistently describes the IGBT steady-state current-voltage characteristics and switching transient current and voltage waveforms for all loading conditions. The model is based on the equivalent circuit of a MOSFET which supplies the base current to a low-gain, high-level injection, bipolar transistor with its base virtual contact at the collector end of the base. The basic element of the model is a detailed analysis of the bipolar transistor which uses ambipolar transport theory and does not assume the quasi-static condition for the transient analysis. This analysis differs from the previous bipolar transistor theory in that (1) the relatively large base current which flows from the collector end of the base is properly accounted for, and (2) the component of current due to the changing carrier distribution under the condition of a moving collector-base depletion edge during anode voltage transitions is accounted for. Experimental verification of the model using devices with different base lifetimes is presented for the on-state current-voltage characteristics, the steady-state saturation current, and the current and voltage waveforms for the constant voltage transient, the inductive load transient, and the series resistor-inductor load transient.

Si/Ge0.3Si0.7/Si heterojunction bipolar transistor made with Si molecular beam epitaxy

Abstract: GexSi1−x heterobase n‐p‐n heterojunction bipolar transistor structure has been grown completely by Si molecular beam epitaxy for the first time. A collector‐top type design was adopted. The 3000 A p‐type Ge0.3Si0.7 heterobase layer with 5×1019 cm−3 doping level was grown on an emitter layer which was an arsenic highly doped substrate (7×1019 cm−3), followed by a 5000 A n‐type Si collector layer with 7×1017 cm−3 doping level. Low‐temperature device processes under 650 °C were used to avoid thermal diffusion of impurities. Common‐emitter current gain hFE with a 100‐μm‐diam emitter was 15 at 2×104 A/cm2 collector current density. Compared with a usual Si‐base bipolar transistor of the same size and doping level, an improvement in current gain was observed. Furthermore, GexSi1−x/Si (x=0.1–0.4) p‐n junction interfaces were investigated by current‐voltage and capacitance‐voltage measurements and transmission electron microscopy observation.

Carbon doping in molecular beam epitaxy of GaAs from a heated graphite filament

Abstract: Carbon doping of GaAs grown by molecular beam epitaxy has been obtained for the first time by use of a heated graphite filament. Controlled carbon acceptor concentrations over the range of 10 to the 17th-10 to the 20th/cu cm were achieved by resistively heating a graphite filament with a direct current power supply. Capacitance-voltage, p/n junction and secondary-ion mass spectrometry measurements indicate that there is negligible diffusion of carbon during growth and with postgrowth rapid thermal annealing. Carbon was used for p-type doping in the base of Npn AlGaAs/GaAs heterojunction bipolar transistors. Current gains greater than 100 and near-ideal emitter heterojunctions were obtained in transistors with a carbon base doping of 1 x 10 to the 19th/cu cm. These preliminary results indicate that carbon doping from a solid graphite source may be an attractive substitute for beryllium, which is known to have a relatively high diffusion coefficient in GaAs.

Analytical modeling of device-circuit interactions for the power insulated gate bipolar transistor (IGBT)

Abstract: The device-circuit interactions of the power insulated gate bipolar transistor (IGBT) for a series resistor-inductor load, both with and without a snubber, are simulated. An analytical model for the transient operation of the IGBT, previously developed, is used in conjunction with the load circuit state equations for the simulations. The simulated results are compared with experimental results for all conditions. Devices with a variety of base lifetimes are studied. For the fastest devices studied (base lifetime=0.3 mu s), the voltage overshoot of the series resistor-inductor load circuit approaches the device voltage (500 V) for load inductances greater than 1 mu H. For slower devices, though, the voltage overshoot is much less, and a larger inductance can therefore be switched without a snubber circuit (e.g. 80 mu H for a 7.1 mu s device). The simulations are used to determine the conditions for which the different devices can be switched safely without a snubber protection circuit. Simulations are also used to determine the required values and ratings for protection circuit components when protection circuits are necessary. >

GexSi1−x strained‐layer heterostructure bipolar transistors

Abstract: Double heterostructure bipolar transistors with the base region consisting of a p‐Ge0.5Si0.5 strained‐layer superlattice have been grown by molecular beam epitaxy. At a wavelength of 1.3 μm, optical gain as high as 52 has been achieved in two‐terminal phototransistors. The large photocurrent is inferred to be a product of the transistor gain, on the order of 20, and avalanche multiplication. A differential current gain of 10 has been obtained in the three‐terminal bipolar transistors. The incorporation of a narrow band‐gap GexSi1−x superlattice base is expected to result in higher emitter injection efficiency as compared to Si bipolar transistors.

A new effect at high currents in heterostructure bipolar transistors

Abstract: Large current densities in heterostructure bipolar transistors with heterostructure collectors are shown to cause an excess electron barrier leading to an increase in minority-carrier charge storage in the base and a decrease in current gain of the device. This effect occurs at current densities where the mobile charge in the collector depletion region significantly reduces the electrostatic field, thus exposing an electron chemical potential barrier due to bandgap grading at the junction. The effect appears at lower current densities than the Kirk effect and should occur in wide-gap heterostructure collector devices. The effect is demonstrated using experimental data and analyzed using device modeling; solutions are suggested for its elimination. >

Growth and diffusion of abrupt zinc profiles in gallium arsenide and heterojunction bipolar transistor structures grown by organometallic vapor phase epitaxy

Abstract: The growth and diffusion of abrupt Zn profiles in undoped gallium arsenide (GaAs), silicon‐doped GaAs, and heterojunction bipolar transistor structures grown by organometallic vapor phase epitaxy have been studied using secondary ion mass spectrometry depth profiling. The depth profiles indicate that abrupt (within 100 A) turn‐on of Zn doping to levels approaching 1020 cm−3 are obtainable, while abrupt turn‐off is limited to about two orders of magnitude due to dopant tailing toward the surface resulting from residual Zn in the reactor. The sharp diffusion fronts resulting from post‐growth anneals indicate that the Zn diffusion coefficient has a concentration dependence. However, the diffusion of Zn at high concentrations appears to be inhibited by crystal defect kinetics resulting in a relatively concentration‐independent Zn diffusion coefficient. The V/III growth ratio did not have an effect on Zn diffusion in undoped or silicon‐doped GaAs. The diffusion of Zn in heterojunction bipolar transistor struct...

Method of manufacturing integrated circuit containing bipolar and complementary MOS transistors on a common substrate

Abstract: An integrated circuit containing bipolar and complementary MOS transistors wherein the emitter terminals of the bipolar transistors as well as the gate electrodes of the MOS transistors are composed of the same material, consisting of a metal silicide or of a double layer containing a metal silicide and a polysilicon layer. The emitter base terminals are arranged in self-adjusting fashion relative to one another and the collector is formed as a buried zone. The collector terminal is annularly disposed about the transistor. As a result of the alignment in dependent spacing between the emitter and the base contact, the base series resistance is kept low and a reduction of the space requirement is achieved. The doping of the bipolar emitter and of the n-channel source/drain occurs independently. The method for the manufacture of the integrated circuit employs an n-doped gate material of the MOS transistors as a diffusion source and as a terminal for the emitters of the bipolar transistors and does not require an additional photolithography step. Because of the annular, deep collector region, a reduction of the collector series resistance and an increased latch-up hardness are achieved. The integrated semiconductor circuit is employed in VLSI circuits having high switching speeds.

Junction degradation in bipolar transistors and the reliability imposed constraints to scaling and design

Abstract: The stress-induced leakage current is predominantly a Shockley-Read-Hall-like generation-recombination current. As the stress progresses, the leakage current increases, eventually reaches a maximum and then decays. The leakage current lowers the current gain at low biases. It affects the narrow-emitter transistors more since it is proportional to the emitter edge length. But, its impact is less significant if the transistor is operated at a high V/sub be/, as required by constant-current scaling. The loss of the current gain does not affect the circuit speed directly. Instead, it reduces the logic swing and thus the noise margin of the circuit. The design to absorb the degradation with a larger initial logic swing results in a speed penalty. The reverse-stress-induced junction degradation can be eliminated by properly designing the circuit There is no concern for emitter-coupled logic (ECL) circuits when the logic swing is less than the V/sub be/ of the transistors. >

Design and realization of bipolar transistors

Abstract: Part 1 Overview: evolution of silicon bipolar technology evolution of heterojunction bipolar technology operating principles of the bipolar transistor. Part 2 Bipolar transistor theory: components of base current fundamental equations base current current gain shallow emitters heavy doping effects extension of the simple theory junction breakdown. Part 3 Bipolar transistor models: transistor modelling ebers-moll model small-signal hybrid-II model gummel-poon model modelling the low-current gain forward transit time TF base resistance collector/base capacitance the SPICE bipolar transistor model. Part 4 Polysilicon emitters: basic physics of the polysilicon emitter theory of polysilicon emitters emitter resistance design of practical polysilicon emitter transistors SIS emitters. Part 5 Heterojunction emitters: theory of heterojunction emitters GaAIAs/GaAs heterojunction emitters bandgap engineering. Part 6 Bipolar integrated circuit fabrication: buried layer and epitaxy isolation base emitter yield problems in bipolar processes analogue bipolar processes digital bipolar processes GaAs/GaAIAs heterojunction bipolar processes BICMOS processes. Part 7 Optimization of high-speed bipolar processes: ECL propagation delay expression calculation of the electrical parameters comparison of conventional and self-aligned processes process optimization. Appendices: bipolar transistor model parameters fundamental physical constants properties of silicon and gallium arsenide properties of silicon dioxide.

Self-aligned AlGaAs/GaAs HBT with low emitter resistance utilizing InGaAs cap layer

Abstract: A self-aligned AlGaAs/GaAs heterojunction bipolar transistor (HBT) with an InGaAs emitter cap layer that has very low emitter resistance is described. In this structure, a nonalloyed emitter contact allows the emitter and base electrodes to be formed simultaneously and in a self-aligned manner. The reduction of emitter resistance greatly improves the HBT's transconductance and cutoff frequency. In fabricated devices with emitter dimensions of 2 mu m*5 mu m, a transconductance-per-unit-area of 16 mS/ mu m/sup 2/ and a cutoff frequency of 80 GHz were achieved. To investigate high-speed performance, a 21-stage ECL ring oscillator was fabricated using these devices. Propagation delay times as low as 5.5 ps/gate were obtained, demonstrating the effectiveness of this structure. >

Current sensing for built-in testing of CMOS circuits

Abstract: Built-in current (BIC) testing involves the monitoring of power bus currents in a VLSI circuit, as a means of detecting processing defects in the circuit. The design and performance of a prototype BIC sensor for static CMOS are discussed. It has been demonstrated that a fully-operational BIC sensor can be designed using a standard CMOS process. The presented design met all basic requirements: it was small, it caused only a small degradation of the performance of the monitored module, and it provided sufficient current resolution. The main disadvantage of the described design, however, was a substrate current caused by the structure of the bipolar transistor. >

Monolithically integrated semiconductor device containing bipolar junction transistors, CMOS and DMOS transistors and low leakage diodes and a method for its fabrication

Abstract: Disclosed is a monolithic integrated semiconductor device which may contain specimens of seven different circuit components; namely: lateral N-MOS and lateral P-MOS transistors (CMOS), vertical N-DMOS and vertical P-DMOS transistors, vertical NPN bipolar transistors, vertical PNP bipolar transistors with isolated collector and low leakage junction diodes as well as a process for fabricating such a device.

High-frequency performance limitations of millimeter-wave heterojunction bipolar transistors

Abstract: Heterojunction bipolar transistor structure (HBTs) with 0.25-, 0.4-, and 0.6- mu m emitter stripe widths and ultrasubmicrometer base widths, which are designed to achieve minimum transit time and low parasitic effects, are examined for their millimeter-wave performance. In particular,the dependence of the unity current gain frequency (f/sub tau /), the maximum oscillation frequency (f/sub max/), and the stability of power gains on the device structure and material parameters are critically analyzed. It is shown that the classical f/sub max/ expression commonly used for bipolar transistors, involving the effective carrier transit time and the collector-based RC time constant does not adequately represent the performance of ultrasubmicrometer-based-width HBTs, where the transadmittance phase delay associated with the collector-base depletion layer transit time and the parasitic collector-based capacitance are significant. The expected ballistic and quasiballistic behaviour of electron in these ultrasubmicrometer structures, if properly designed, minimizes the effective carrier transit time effect, but its impact on the f/sub max/ by the excess transadmittance phase delay poses a more fundamental and serious high-frequency limiting factor for the realization of millimeter-wave HBTs than has been hitherto recognized. The accuracy and usefulness of the proposed analytical approach is demonstrated for a practical HBT structure with 1.2- mu m emitter stripe design, giving results that agree well with measurements. >

beta -SiC/Si heterojunction bipolar transistors with high current gain

Abstract: The combination of single-crystalline beta -SiC and Si permits the fabrication of a heterojunction bipolar transistor (HBT) in which the conventional poly-Si or single-crystalline Si emitter is replaced with a single-crystalline SiC emitter, a technique compatible with existing Si technology. A common-emitter current gain of 800 is attained with this device. The value of the ideality factor n of the base current is 1.1, which suggests that diffusion current is dominant. The large number of misfit dislocations at the SiC/Si heterojunction are ineffective as recombination centers and do not deteriorate the characteristics of the HBT. >

Analysis and characterization of BiCMOS for high-speed digital logic

Abstract: A combined bipolar and CMOS (BiCMOS) logic gate, capable of driving large capacitive loads at high speed, is analyzed and characterized. A simple analytical model which accurately predicts the transient response of the BiCMOS gate is described. At moderate and large loads, saturation of the bipolar transistors due to collector resistance can dominate the transient response. Device scaling issues are discussed for minimizing gate delay at various loading conditions. >

Process for manufacturing CMOS integrated devices with reduced gate lengths

Abstract: A process for manufacturing CMOS integrated devices with gate lengths of less than one micron and high supply voltage is described. In order to improve the resistance of CMOS devices to breakdown and punch-through phenomena without cost increases with respect to conventional CMOS processes and limiting as much as possible the introduction of resistances in series to the transistors, less doped source and drain regions being provided in only one of the two MOS transistors, e.g. in the N-channel transistor, to increase the breakdown voltage, an oppositely doped region, e.g. with P-type doping, being provided around the source and drain regions of this first transistor to protect this first transistor against punch-through, and doped wells being provided around the source and drain regions of the complementary transistor, which is e.g. a P-channel transistor; the doped wells being oppositely doped with respect to the source and drain regions but having a lower doping level than the region of the body of semiconductor material which accommodates the complementary transistor, in order to increase the breakdown voltage of the P-channel complementary transistor.

Degradation of bipolar transistors under high current stress at 300 K

Abstract: We have observed the onset of degradation of bipolar transistor characteristics under high current forward stress at room temperature. The observed degradation may be attributed to interface states generated next to the sidewall oxide at the emitter base junction in a self‐aligned bipolar transistor. Individual steps in the generation and annealing kinetics may be resolved. The sensitivity of the device to the extrinsic base doping profile is demonstrated and a model based on the generation of hot carriers by Auger recombination and bond breaking by these hot carriers is proposed.

Identification and implication of a perimeter tunneling current component in advanced self-aligned bipolar transistors

Abstract: The identification of a perimeter tunneling current in the base-emitter junction of advanced double-poly self-aligned bipolar transistors has been verified by measuring based current as a function of temperature, bias voltage, and device perimeter-to-area ratio The perimeter tunneling current at forward bias is found to be predominantly an excess tunneling that depends on the sidewall oxide interface properties, while that at reverse bias is due to band-to-band tunneling resulting from the emitter and extrinsic base profile overlap Based on experimental results and an analysis of base-leakage-current trade-offs at forward and reverse bias, a device design concept was developed to enhance device performance and processing yield in scaled bipolar transistors >

A review of thermal characterization of power transistors

Abstract: The thermal characteristics of power transistors and their measurement are discussed. The devices discussed include bipolar transistors and metal-oxide-semiconductor field-effect transistors (MOSFETs). Measurement problems common to these devices are addressed, such as general methods for measuring device temperature, control of thermal environment, selection of a temperature-sensitive electrical parameter, measurement of temperature-sensitive electrical parameters, reasons for measuring temperature, and temperature measurement of integrated power devices. Procedures for detecting nonthermal switching transients, extrapolation of the measured temperature to the instant of switching, and for measuring the temperature of Darlington transistors are included. The needs for thermal characterization of evolving devices such as high voltage and power integrated circuits and merged bipolar/MOSFET devices are mentioned. >

Selective epitaxial growth silicon bipolar transistors for material characterization

Abstract: In development of the epitaxial lateral overgrowth (ELO) bipolar transistor, devices were fabricated in silicon selective epitaxial growth (SEG). These devices were used to electrically characterize the quality of the SEG material. Three silicon bipolar transistors, with almost identical doping profiles and geometries were simultaneously fabricated on the same wafer and their electrical characteristics compared. The three transistors were located in the substrate, a single SEG layer, and a double (interrupted growth) SEG layer. The SEG silicon was grown in a reduced-pressure RF-heated pancake-type epitaxial reactor at 950 degrees C and 150 torr. The transistors were tested for junction ideality factors, junction reverse-bias leakage currents, and forward DC current gain. Test results indicated the excellent device quality of the SEG material relative to the substrate. >

Multiple-state resonant-tunneling bipolar transistor operating at room temperature and its application as a frequency multiplier

Abstract: A resonant-tunneling bipolar transistor with two peaks in the direct as well as in the transfer characteristics is presented. The multiple peaks are obtained by sequentially quenching resonant tunneling through the ground states of a series of double-barrier quantum wells, placed in the emitter of a Ga/sub 0.47/In/sub 0.53/As-Al/sub 0.48/In/sub 0.52/As bipolar transistor, thus obtaining nearly equal peak currents and peak-to-valley ratios. The transistor exhibits current gain of about 70 at room temperature and 200 at 77 K. Peak-to-valley current ratios at room temperature and at 77 K are as high as 4:1 and 20:1, respectively. Frequency multiplication by factors of three and five has been demonstrated using the multiple-peak transfer characteristics of the transistor. >

Inherent and stress-induced leakage in heavily doped silicon junctions

Abstract: Inherent leakage currents and leakage induced with reverse-bias stress are investigated in heavily doped emitter-base junctions of polysilicon self-aligned bipolar transistors and similar diodes. Inherent in the devices is a reverse leakage component found to have a perimeter trap-assisted tunneling component characteristic of the Si-SiO/sub 2/ surface and evident at doping insufficient for significant band-to-band tunneling. The band-to-band phonon-assisted tunneling and avalanche leakage components are also identified. Introducing surface states through reverse-bias stress induces a Pool-Frenkel electric field enhanced generation/recombination surface leakage component. The induced and trap-assisted tunneling components are distinct. The induced component is found to saturate as available states, dependent on the peak electric field, are exhausted. Trapped charge accumulation after extensive stressing affects the electric field along the surface reducing the induced and trap-assisted tunneling leakage components. >

High-current-gain submicrometer InGaAs/InP heterostructure bipolar transistors

Abstract: Common-emitter current gains of 115 and 170 are achieved in transistors with emitter dimensions as small as 0.3*3 and 0.8*3 mu m/sup 2/, respectively. These results are comparable with scaling experiments reported for Si bipolar devices and represent a significant improvement over AlGaAs/GaAs heterostructure bipolar transistors. Both the low surface recombination velocity and nonequilibrium carrier transport in the thin (800-AA) InGaAs base enhance the DC performance of these transistors. >

Monolithic optical position encoder with on-chip photodiodes

Abstract: A system that combines light sensors and analog and digital parts on the same CMOS chip has been fabricated. The optical and electrical properties of various photodiodes, which are fully compatible with a standard CMOS technology, are discussed. The current comparators use CMOS-compatible lateral bipolar transistors. The optical encoder also comprises a signal processor for code conversion, a serial or parallel output, and a self-test function. A 14-channel circuit which senses light signals at 880 nm with a power of 0.3-3 mW/cm/sup 2/ has been fabricated. Response time is shorter than 1 mu s at all illumination levels. This circuit operates in the temperature range -55 to +125 degrees C. Its current consumption is 8 mA at 5 V. >

Surface recombination in GaAlAs/GaAs heterostructure bipolar transistors

Abstract: Experimental evidence shows that surface recombination in npn GaAlAs/GaAs heterostructure bipolar transistors changes from an exp(qV/2kT) dependence at low currents to an exp(qV/kT) dependence at high currents. Using a one‐dimensional analysis, Henry, Logan, and Meritt [J. Appl. Phys. 49, 3530 (1978)] have derived a 2kT dependence for surface recombination in the presence of Fermi‐level pinning and flat quasi‐Fermi levels between the surface and the bulk. We find that the kT dependence, which dominates at high bias, arises when the recombination rate is limited by availability of minority carriers at high surface recombination velocities. The quasi‐Fermi levels do not remain flat at high surface recombination velocities. Two‐dimensional effects are also shown to be strong and influential in limiting the availability of carriers.

Near‐ideal transport in an AlGaAs/GaAs heterostructure bipolar transistor by Na2S⋅9H2O regrowth

Abstract: The deposition of sodium sulfide nonahydrate (Na2S⋅9H2O) onto mesa AlGaAs/GaAs heterostructure bipolar transistors confers near‐ideal transport characteristics to the device structure. By reducing the GaAs surface recombination velocity, sulfide regrowth leads to current gain ( β) almost independent of collector current, and β>1 at collector current density below 5×10−7 A/cm−2. Furthermore, we obtain by passivation an emitter junction ideality factor of n=1.03.

Bipolar transistor scaling for minimum switching delay and energy dissipation

Abstract: A novel figure-of-merit to guide in the scaling of high-speed bipolar transistors is proposed. A method is described to relate the gate delay of a ring-oscillator to measurable device parameters analytically. The closed-form solution for an unloaded ECL (emitter coupled logic) gate agrees very well with published data of the past several years and with the results of circuit simulation. The formula for the basic current switch relates in a simple way the different device parameters and has been used to optimize device design for maximum speed and minimum energy dissipation. >

Voltage clamped differential to single ended converter circuit

Abstract: A MOS differential to single ended converter circuit is provided for supplying a single ouput signal in response to first and second differentially related current being supplied to first and second junctions thereof. The converter circuit includes first and second MOS transistors each having gate, drain and source electrodes with the gate electrodes being coupled together while the drain and gate electrodes of the first transistor are interconnected. The drain and source electrodes of the pair of transistors are respectively coupled in series with the first and second junctions. First and second bipolar transistors each having first, second and control electrodes are provided for limiting the voltage swing at the drain of the second MOS transistor. The contol and first electrodes of the first bipolar transistor are coupled respectively to the first and second junctions whiled the control and first electrodes of the second bipolar transistor are respectively coupled to the second and first junctions with the second electrodes of the two bipolar transistors being coupled to an additional common terminal.