Showing papers on "Channel length modulation published in 1987"

The impact of gate-induced drain leakage current on MOSFET scaling

Abstract: Significant gate-induced drain leakage current can be detected in thin gate oxide MOSFETs at drain voltages much lower than the junction breakdown voltage. This current is found to be due to the band-to-band tunneling occurring in the deep-depletion layer in the gate-to-drain overlap region. In order to limit the leakage current to 0.1pA/µm, the oxide field in the gate-to-drain overlap region must be limited to 1.9MV/cm. This may set another constraint for the power supply voltage and/or oxide thickness in VLSI MOSFET scaling Device design considerations for minimizing the gate-induced drain leakage current are discussed.

Gate-voltage-dependent effective channel length and series resistance of LDD MOSFET's

Abstract: A measurement algorithm to extract the effective channel length and source-drain series resistance of MOSFET's is presented. This extraction algorithm is applicable to both conventional and LDD MOSFET's. It is shown that the effective channel length and the source-drain series resistance of an LDD device are gate-voltage dependent. The effective channel length of an LDD device is not necessarily the metallurgical junction separation between the source and drain as it is commonly seen in a conventional device. A more generalized interpretation of effective channel length is introduced to understand the physical meaning of this gate-voltage dependence. The result also indicates that the effective channel length and source-drain resistance are two inseparable device parameters regardless of LDD or conventional FET's.

The impact of intrinsic series resistance on MOSFET scaling

Abstract: The intrinsic parasitic series resistance associated with the practical structure of a MOSFET is examined. The components considered include contact resistance, diffusion sheet resistance, spreading (injection) resistance, and accumulation layer resistance. The impact of the total resistance on MOSFET scaling is assessed, down to a channel length of 0.15 µm. The results show that, contrary to what has been claimed before, the transconductance and current of a MOSFET continue to increase as the channel length is miniaturized, although the degradation percentage-wise compared to an ideal device without series resistance continues to increase. Based on the degraded I-V characteristics and their effects on an inverter, it is shown here that for NMOS or PMOS digital circuits, the maximum degradation in speed due to series resistance is 20-35 percent compared to ideal scaling for the shortest channel considered. For CMOS circuits, the maximum degradation is reduced to 7-15 percent. In absolute terms, a loss of speed in either case due to miniaturization of channel length is not expected even down to 0.15 µm.

Thermal effects in n-channel enhancement MOSFET's operated at cryogenic temperatures

Abstract: Thermal effects in n-channel enhancement-mode MOSFET's operated at cryogenic temperatures are discussed. Device heating is identified as the cause of drain current transients and the origin of this phenomenon is considered. Experimental results are presented in which thermal effects are studied as functions of temperature for various gate and drain biases. Drain current is found to be a monitor of device temperature, From an understanding of the thermal behavior of devices, the channel electron mobility can be examined as a function of temperature and gate bias. The observed thermal effects are explained in terms of material and device properties. The implications for future low-temperature CMOS VLSI development are discussed.

MOSFET substrate current model including energy transport

Abstract: A new MOSFET substrate current model, incorporating energy transport, is proposed. It was found that a non-steady-state electron transport effect and two effects attributed to electron pressure are essential to calculate the substrate current characteristics accurately. The predictions from the present model compare favorably with the experimental data for MOSFET's with effective channel length down to 0.45 µm.

Hot-carrier induced drain leakage current in n-channel MOSFET

Abstract: Hot-carrier induced drain leakage current in n-channel MOSFET's has been found. Two leakage mechanisms exist at least. The leakage current for one mechanism can be characterized by it, exponential dependence on the drain voltage, approximate proportionality to the stress time, and very small (0.10eV) activation energy. The other mechanism can be characterized by its somewhat ohmic-like dependence on the drain voltage, approximate quadratic dependence on the stress time, and relatively large (0.29eV) activation energy. When stress is imposed by triode-mode operation, the former mechanism is dominant. For pentode-mode operation, the former is followed by the latter. The drain leakage current is observed for conventional, LDD and ALDD (Advanced LDD) structures, although they differ in magnitude. This hot-carrier induced drain leakage current may cause functional failure in DRAM cell or in resistor-load type SRAM cell, while the corresponding degradation in channel conductance may not.

An analytic I—V model for lightly doped drain (LDD) MOSFET devices

Abstract: An analytic I-V model for lightly doped drain (LDD) MOSFET devices is presented. In this model, the n-region is considered to be a modified buried-channel MOSFET device, and the channel region is considered to be an intrinsic enhancement-mode MOSFET device. Combining the models of these two regions, the drain current in the linear/saturation regions and the saturation voltage can be calculated directly from the terminal voltages. In addition, the parameters used in the channel region can be extracted by a series of least square fittings. According to comparisons between the experimental data measured from the test transistors and the theoretical calculations, the developed I-V model is shown to be valid for wide ranges of channel lengths.

A unified analytical model for drain-induced barrier lowering and drain-induced high electric field in a short-channel MOSFET

Abstract: Using the well known El-Mansy-Ko method, a simple solution of the two dimensional Poisson equation is derived at the SiSiO 2 interface for the region bounded by the source and the drain. The solution is valid for long channel as well as short channel MOSFETs. The effect of variable values of the depletion depth is incorporated using the WKB approximation. The solution yields a new model of the subthreshold voltage of a short channel MOSFET. The solution also provides mathematical justification of the intuitive assumptions made by Hsu, Muller and Hu in their paper on punch through currents in short channel MOSFETs. Since the single solution gives both the drain induced high field, DIHF, and the drain induced barrier lowering, DIBL, it also yields an analytical relation between them. The DIBL increases approximately expnentially as E max decreases. The results obtained from this model are in agreement with the numerical simulations and are consistent with the known experimental results.

Matching current source

Abstract: In a matching current source for providing equivalent sink and source current, external voltage controls the amplitude of sink current and an operational amplifier is connected to mirror the sink current to the source current. The operational amplifier comprises a unity gain feedback loop for eliminating the effect of the channel length modulation effect in MOS transistors and the Early Effect in bipolar transistors, and serves the function of generating equivalent sink and source currents.

Junction field effect transistor

Abstract: A junction field effect semiconductor device is provided with p-type source and drain semiconductor regions separately formed in an n-type expitaxial layer grown on a substrate, a p-type channel layer, a highly doped n+ -type gate region surrounding the source and drain regions and the channel layer, and a highly doped n+ -type top gate layer formed on the channel layer. The channel layer is formed only in an area bounded between the source and drain regions, so that it is possible to make a drain current proportional to a channel width to length ratio.

High frequency, high power field effect transistor

Abstract: A high-frequency, low-gate leakage, low-noise, lateral junction field-effect transistor has a short, heavily doped channel of length determined by the dimensions of a backgate within a semiconductor substrate, and a more lightly doped drift region adjacent to the channel. A source region is formed on an end of the channel spaced from the drift region, and a drain region is formed on an end of the drift region spaced from the channel, such that the current flowing between the source and drain regions passes through channel and drift region. A gate electrode of material opposite to the channel forms a rectifying junction with the channel, and an electric field developed in the channel between the gate electrode and the backgate in response to gate and drain potential controls current flow between source and drain. The gate electrode overlays the drift region enough that the depletion region that forms with the application of drain potential moves away from the channel and semiconductor surface.

Anomalous Subthreshold Current-Voltage Characteristics of n-Channel

Abstract: The abnormally high slopes of the subthreshold current- voltage characteristics exhibited by n-channel silicon-on-insulator (SOI) MOSFET's are experimentally related to defect density (off-state leakage current) as well as drain voltage and channel length, and a theoretical physical description of the measured relations is presented and supported. The anomalous subthreshold behavior, is attributed analytically to the (floating) body effect due to charging (biasing) by impact ionization at the drain. ECAUSE of the inherent advantages of dielectric isolation in VLSI and in radiation-hardened IC's, silicon-on- insulator (SOI) CMOS technologies are of much interest today. In a recent paper ( 11, Davis et ai. showed that certain n- channel SO1 MOSFET's exhibit abnormally high slopes, or low gate-voltage swings {S = dVGs/d(log ID)), in their subthreshold current-voltage characteristics. After noting that S decreases with decreasing channel length and with increas- ing drain voltage, they associated this abnormality with the kink effect (2), which is normally observed in the suprathresh- old saturation-region characteristics. No physical description of the high subthreshold ID( VGs) slopes was given, however. In this paper we give such a description, supporting it with more comprehensive data that show the effect to be more profound in some cases and that reveal dependences on defect density (off-state leakage current) as well as channel length and drain voltage. While the anomalous subthreshold slopes could be due to significant conduction in the parasitic lateral bipolar transistor (3), we show that they can be described by the (floating) body effect due to charging (biasing) by impact ionization at the drain. Measurements of the body voltage? in addition to the drain current, in the subthreshold region give the physical insight needed to support the description, which in fact can aid the optimal design of SO1 IC's. The anomalous subthreshold behavior is not so severe in the SO1 p-channel transistors, which is commensurate with the lower hole-impact ionization coefficient in silicon. We examined n-channel MOSFET's fabricated in SO1 films produced by implantation of 0 - ions into n-type silicon substrates. The oxygen ions were implanted with an energy of

Enhancement-depletion CMOS circuit with fixed output

Abstract: In a CMOS FET IC element including at least one pair of transistors with connected drains, one an N-channel MOSFET and one a P-channel MOSFET, the N-channel MOSFET having a first threshold voltage controlled by the implantation of an ion, and the P-channel MOSFET having a second threshold voltage control are implanted with the same type of ion, so that one of the pair of transistors, either the N-channel MOSFET or the P-channel MOSFET is of a type that is normally ON, and the other MOSFET is of a type that is normally OFF with any gate voltage between the two voltages supplied to their sources.

Mosfet incorporating protection function

Abstract: PURPOSE:To reduce the cost by combining the drain current and the drain-source voltage to control turning-on/off of a main MOSFET. CONSTITUTION:The power consumption in the chip of a power MOSFET is detected by the combination between a drain-source voltage VDS and a drain current ID of the power MOSFET. When relations between the voltage VDS and the current ID satisfy condition ID>AXVDS+B, a gate-source voltage VGS is reduced to turn off a load driving MOSFET. A and B in this formula are a negative constant and a positive constant respectively, and they are so selected that a maximum value of VDSXID on the operation characteristic line, namely, -B /4A and a maximum allowable loss PD of the load driving MOSFET satisfy relations PD>=-B /4A. Thus, an MOSFET incorporating the overpower protection function of low cost is obtained.

Sub Micron P-MOSFETs under Static and SWAP Stress

Abstract: When the gate length is reduced to below 1/um, hot electron induced degradation of p-channel MOSFETs becomes a serious problem, Trapped electrons reduce the effective channel length causing reduction of absolute VT and current increase in the linear region1,2. Conventional and offset type P-MOSFETs have been analyzed under three stress conditions: (1) DC stress at maximum substrate current, (2) DC stress at high gate voltage, (3) and a novel Swap stress in which drain and source are interchanged several times during stressing. The last stress mode is relevant for P-channel pass transistors and transfer gates in P-MOS DRAMs.

New analytical expression for the drain current of short-channel MOS transistors in the triode region

Abstract: Neglecting the effects of the source and drain electric fields on the depletion-layer charge, and consequently on the drain current, cannot be justified in short-channel MOS transistors. The existing geometrical approach for analysing this problem, known as a charge-sharing model, gives good agreement with experimental data only if an extremely complex expression for the drain current is used. In the letter the use of Gauss's law as a more general approach to analysis of the fringing field effect has been proposed. Using this approach, a simple expression for the drain current of short-channel MOS transistors, which shows excellent agreement with experimental data, has been derived.