Showing papers on "Chip published in 1990"

The use and evaluation of yield models in integrated circuit manufacturing

Abstract: The development and refinement of net-die-per-wafer yield models during the past 25 years are reviewed, and the models are tested for accuracy by comparison with actual yield data from seven separate chip companies. Depending on chip size, the more accurate models are the Poisson and the negative binomial. Several models for line yields in wafer fabrication are also covered. For predicting yields of larger-die-area very large-scale integration, the negative binomial model is the more accurate, but its use many require experimental determination of alpha, sometimes called the cluster parameter, versus chip area for the particular process and factory environment of interest. How an Insystems holographic wafer inspection machine can aid this process is described. Financial payback calculations for cleaner processing machines and experience curve effects on yields are also discussed. >

Apparatus and method for recording jaw motion

Abstract: A method and apparatus for tracking, recording and analyzing a subject's jaw motion is provided. Cross-haired targets are non-intrusively fixed in relation to the subject's upper and lower jaws. Three video cameras are disposed about the subject's head, each camera lens being focused on the targets. Each video camera is equipped with a charge control device chip which includes an array of light sensitive pixels defining a two dimensional image coordinate system. The charge control device chip converts a light image indicative of a target's cross-hair position into a series of amplitude signals. A computer is used to receive, process and display said camera chip amplitude signals. The computer includes a pre-processor board for timing, synchronizing and transforming said camera chip amplitude signals into address record information representing the targets' relative positions as a function of time. The computer also has a mass storage unit for storing address record information, graphics software for creating a simulation of the subject's jaw movement in the subject coordinate system based on the address record information, and a display for visually presenting the simulation produced by the graphics software. The method and apparatus are useful for understanding orofacial pain, fabricating prosthesis, analyzing temporomandibular joint dysfunction pathology and orthodontic and occlusion problems.

Wireless alarm system

Abstract: A wireless alarm system using spread spectrum transmitters, fast frequency shift keying, spread spectrum receivers and computer with a display. The spread spectrum transmitter includes an oscillator coupled to a microprocessor with chip code generation means, preamble register, address register and data register. The spread spectrum receiver acquires synchronization of the spread spectrum signal using a microprocessor coupled to the quieting, signal strength or baseband output of the receiver, with a two step algorithm. The steps comprise achieving a coarse lock and a fine lock to the spread spectrum signal.

Self aligned, flip chip assembly of photonic devices with electrical and optical connections

Abstract: Self-aligned flip-chip assembly using solder bump bonding has been applied to photonic circuits, resulting in several important advantages, including high precision, excellent ruggedness, and uncritical final assembly. Experiments with lithium niobate integrated optical chips and single-mode optical fibers have demonstrated that the optical coupling loss due to misalignment can be held to less than 1 dB in a fully self-aligned, multifiber assembly. The technique achieves approximately 1 mu m accuracy in optical-fiber placement without requiring micromanipulation of piece parts during final assembly, and simultaneously forms an essentially unlimited number of high-performance electrical bonds in an interconnect pattern distributed as required over the chip surface. The assemblies are compatible with a rugged environment and with hermetic packaging. >

VLSI implementation of a neural network model

Abstract: The authors describe a complementary metal-oxide-semiconductor (CMOS) very-large-scale integrated (VLSI) circuit implementing a connectionist neural-network model. It consists of an array of 54 simple processors fully interconnected with a programmable connection matrix. This experimental design tests the behavior of a large network of processors integrated on a chip. The circuit can be operated in several different configurations by programming the interconnections between the processors. Tests made with the circuit working as an associative memory and as a pattern classifier were so encouraging that the chip has been interfaced to a minicomputer and is being used as a coprocessor in pattern-recognition experiments. This mode of operation is making it possible to test the chip's behavior in a real application and study how pattern-recognition algorithms can be mapped in such a network. >

Method and apparatus for the reception and demodulation of spread spectrum radio signals

Abstract: A spread spectrum receiver with filters matched to transmitter chip codes are implemented in digital circuits along with a digital circuit for acquisition and tracking of the arrival times of the chip codes. The digital circuit implementations are used for the noncoherent demodulation of pulse position spread spectrum modulation signals where the pulse is a carrier modulator by a chip code and for the noncoherent demodulation of multiple chip code modulation signals where each information symbol is represented by one of several chip codes modulating a carrier.

A monolithic 20 b delta-sigma A/D converter

Abstract: Oversampled delta-sigma converters have been used for high-resolution analog-to-digital conversion over a wide range of input frequencies. Oversampled converters reduce the need for complex antialias filters, eliminate sample-and-hold amplifiers, and are free of differential nonlinearity errors. A fourth-order converter with a dynamic range of 123 dB and a signal-to-total-harmonic-distortion ratio of 126 dB is described. The input voltage range is 20 V peak to peak, the input signal bandwidth is DC to 500 Hz, the clock frequency is 1024 MHz, and the output word rate is 32 K/s. The 4.48*6.53-mm chip is packaged in a 28-pin plastic leaded chip carrier/leadless chip carrier (PLCC/LCC) and dissipates 120 mW using +5 V, -5 V, and ground. >

Artificial neural networks using MOS analog multipliers

Abstract: A neural network implementation that uses MOSFET analog multipliers to construct weighted sums is described. The scheme permits asynchronous analog operation of Hopfield-style networks with fully programmable digital weights. This approach avoids the use of components that waste chip area of require special processing. Two small chips have been fabricated and tested-one implementing a fully connected (recursive) network and the other containing isolated portions of a neuron. The fully connected network chip successfully solves simple graph partitioning problems, in confirmation of network simulations performed using an analytic model of the analog neuron. This result verifies the operation of the complete network, including common-mode biasing circuits and connection weight data paths. A direct scaling of this chip would allow the complete integration of 81-neuron fully connected networks with 6-b plus sign connection weights using 1.25- mu m design rules on a 1-cm die. >

Multiple signal receiver for direct sequence, code division multiple access, spread spectrum signals

Abstract: Disclosed is a multiple-signal receiver system for direct sequence, code division multiple access (CDMA), spread spectrum (SS) signals. The receiver is structured to overcome inter-signal interference during signal acquisition and data reception even when the ratio of received signal powers exceeds the bandwidth spreading ratio of the signals. The receiver contains one processing channel for each signal in which correlation with the spread spectrum code of its particular signal is used to selectively isolate that signal so that its waveform parameters can be estimated, its data demodulated, and its waveform reconstructed. Each reconstructed CDMA waveform is individually adjusted in amplitude and phase to cancel its particular CDMA signal from the composite input of multiple CDMA signals. This receiver structure allows cancellation at the input of each receiver signal processing channel of all CDMA signals except the particular desired signal for that channel.

Method of forming an apparatus for burn in testing of integrated circuit chip

Abstract: An integrated circuit AC test and burn-in socket (10) for communicating test signals between test circuitry and an integrated circuit chip (11) comprises connection circuitry (32) associated to engage the chip (11) and communicate test signals between the chip (11) and the test circuitry. A compliant base (34) supports the circuitry (32) and assures positive engagement and electrical connection between the circuitry (32) and the chip (11). A socket assembly (20 and 21) holds the chip (11) in engagement with the connection circuitry (32).

Apparatus and method for reading data encoded on circular objects, such as gaming chips

Abstract: A gaming chip that has a circular bar code imprinted thereon so as to convey information about the issuer of the chip, the chip's denomination, and a serial number which can be utilized to verify the authenticity of the chip. A chip validating device rotates the chip while being maintained in a stationary linear position, such that the encoded information is repeatedly passed before a stationary bar code reader. The validator then uses this information to determine the authenticity of the chip, to indicate the denomination of the chip being wagered, and to accept or reject the chip.

Code division multiplex system using selectable length spreading code sequence

Abstract: A code division multiplex system for use in a spread spectrum communication system utilizes selectable length spread spectrum spreading code sequences. At the encoder, one of a pluraluty of a spread spectrum spreading code sequences having a given fixed length is selected for differential encoding in accordance with the input data to be transmitted. At the receiver correlator, a selectable length differential decoder is set to be responsive to a spread spectrum spreading code sequence having a length substantially equal to the length of the encoded spread spectrum spreading code sequence.

Design and implementation of a general-purpose median filter unit in CMOS VLSI

Abstract: A general-purpose median filter unit configuration in the form of two single-chip median filters, one extensible and one real time, is described. The networks of the chips are pipelined and systolic at bit level and based on odd/even transposition sorting. The chips are implemented in 3- mu m standard CMOS using full-custom VLSI design techniques. The exact median of elements, in a window size w=9 with arbitrary word length L, can be found using only one extensible median filter chip. The filter can be extended to arbitrary window size and word lengths by using many chips. Simulation results show that the extensible median filter chip can be clocked up to 40 MHz and can generate 30/L megamedians per second. The real-time median filter chip can find the exact running medians of elements in a window of a fixed size w=9 with L=8. Simulations show that it can generate up to 50 megamedians per second with a 50-MHz clock. The algorithms, VLSI implementations, and chip test results are presented, along with some possible applications. >

Subscriber unit for wireless digital subscriber communication system

Abstract: A subscriber unit for wireless communication with a base station in a wireless subscriber communication system includes a FIR chip, a DIF (digital intermediate frequency) chip, a single processor chip and a radio. The processor chip transcodes a digital voice input signal to provide digital input symbols; demodulates an output signal received from the base station to provide digital output symbols; and synthesizes a digital voice output signal from the digital output symbols. The FIR chip FIR filters the digital input symbols and generates timing signals for timing the transcoding and synthesizing operations in the processor chip. The DIF chip digitally synthesizes a digital intermediate frequency signal by direct digital synthesis (DDS) and modulates the digital intermediate frequency signal with the filtered input symbols to provide a modulated intermediate frequency input signal. The radio further processes the modulated input signal for transmission to the base station.

Real-time phased array imaging using digital beam forming and autonomous channel control

Abstract: The authors designed and constructed a real-time phased-array imaging system for medical applications based on the principles of digital beam formation and autonomous channel control. The system is capable of high-precision steering, dynamic apodization, dynamic focusing, and highly accurate beamforming using sampling rates close to the Nyquist rate over the medical diagnostic frequency range. All controls and signal processing needed for a single channel of the array imager have been integrated into a single custom VLSI circuit. The authors describe the basic principles embodied in this chip. >

A reconfigurable CMOS neural network

Abstract: An analog CMOS neural net with a programmable architecture containing 32 K connections is discussed. The objective of packing as large a network as possible on a chip leads to the choice of an analog approach. Analog signals are used only inside the network. All the input and output data are digital. The reconfigurable network consists of building blocks that can be joined to form various network architectures. The circuit can be programmed to implement single-layer networks or multilayer networks with binary or analog connections. >

Performance of a stochastic learning microchip

Abstract: We have fabricated a test chip in 2 micron CMOS that can perform supervised learning in a manner similar to the Boltzmann machine. Patterns can be presented to it at 100,000 per second. The chip learns to solve the XOR problem in a few milliseconds. We also have demonstrated the capability to do unsupervised competitive learning with it. The functions of the chip components are examined and the performance is assessed.

Arrangement for mounting and cooling high density tab IC chips

Abstract: A printed circuit board assembly includes a printed circuit board having a top side, a bottom side and a hole. A heat spreader which comprises a plate made of a material having high thermal conductivity is mounted on the bottom side of the printed circuit board. The plate includes a pedestal which extends up into the hole. A high density TAB IC chip is mounted on top of the pedestal and is electrically connected to pads on the top side of the printed circuit board. A heat pipe is mounted underneath the plate of the heat spreader through a mounting pad which is fixed to the heat pipe and which is made of a material having good thermal conductivity. In operation, heat generated by the chip during use is spread out by the heat spreader and then removed by the heat pipe.

A fully monolithic 4-18 GHz digital vector modulator

Abstract: A fully monolithic vector modulator covering the entire 4-18 GHz band and featuring independent direct digital control of amplitude and phase is presented. The modulator output amplitude can be varied over a 25-dB range with 32 steps of resolution and the phase can be independently varied over 360 degrees with 32 steps. The vector modulator chip set consists of a miniaturized 5-b MMIC (monolithic microwave integrated circuit) phase shifter and a 5-b MMIC segmented dual-gate distributed variable-gain amplifier-attenuator. The chips are assembled on a carrier measuring less than 0.4 in *0.5 in and require no supporting RF-hybrid hybrid or DAC (digital-to-analog converter) circuitry. The vector modulator demonstrates state-of-the-art performance with ultrawide (instantaneous) bandwidth, high uncorrected accuracy and resolution, and direct digital control with a potential transition time of a few nanoseconds. In addition, the individual MMIC chip performance is the best reported to date for ultrawide bandwidth phase and amplitude control functions. >

Scan mechanism for monitoring the state of internal signals of a VLSI microprocessor chip

Abstract: A VLSI chip debug and production test apparatus that allows an engineer to view the state of hundreds of signals internal to a chip in real-time without probing, which greatly simplifies the isolation of circuit, speed, logic, and microcode bugs. For production testing, it also provides the ability to check the state of these internal signals on a clock-by-clock basis. The mechanism uses a gated XOR-input serial shift-register cell (10), which is stepped out underneath major buses in otherwise unpopulated areas of the chip. Several of these cell groups are linked together to form a scanout path of the desired length, the operation of which is controlled with a single input pin (40). Output data is channeled through a shared output pin (19) to a VLSI tester (16). In the tester (16) the data (19) is checked and accumulated by back-end software over multiple test-loop iterations, and formatted into a readable form.

A VLSI architecture for a high-speed all-digital quadrature modulator and demodulator for digital radio applications

Abstract: An all-digital architecture is presented for implementing the front-end signal-processing functions in a quadrature modulator and demodulator for high bit-rate digital radio applications. A pair of CMOS chips has been designed and submitted for fabrication in a 1.25- mu m process and is expected to accommodate symbol rates up to 35 MBd. The modulator chip accepts a pair of 8-b in-phase and quadrature data streams and generates a bandlimited IF output with an excess bandwidth factor of 35%. The demodulator chip accepts a digitized IF input signal and generates a pair of filtered in-phase and quadrature baseband signals. The modulator and demodulator chips each incorporate 40-tap multiplierless FIR (finite-impulse response) square-root Nyquist matched filters, and the cascade of the two chips achieves a peak intersymbol interference distortion of -54 dB. The modulator chip can generate any arbitrary signal constellation within a rectangular grid of 256*256 points. Thus, the all-digital implementation results in a generic chip set suitable for a wide variety of high bit-rate digital modem designs using formats such as M-ary PSK and QAM. >

Noise Reduction Using Low Weight and Constant Weight Coding Techniques

Abstract: Signalling off-chip requires significant current. As a result, a chip''s power-supply current changes drastically during certain output-bus transitions. These current fluctuations cause a voltage drop between the chip and circuit board due to the parasitic inductance of the power-supply package leads. Digital designers often go to great lengths to reduce this ``transmitted'''' noise. Cray, for instance, carefully balances output signals using a technique called differential signalling to guarantee a chip has constant output current. Transmitted-noise reduction costs Cray a factor of two in output pins and wires. Coding achieves similar results at smaller costs.

Free-space optical interconnection scheme.

Abstract: As integrated circuit linewidths are reduced, single chip system functionality and speed increase. Conventional electronic chip input/output does not scale with this trend: bonding pad sizes and off-chip capacitive loads remain essentially constant. The shortage of chip interconnect capability has become critical. Integrated free-space optical interconnect has the potential to overcome this problem by providing a large number of high speed connections between chips. This paper describes methods for performing free-space intermodule optical interconnections within a digital electronic computer utilizing large arrays of light beams. A particular architecture and its ongoing implementation with integrated components are discussed.

A Delay-Line Based Motion Detection Chip

Abstract: Inspired by a visual motion detection model for the rabbit retina and by a computational architecture used for early audition in the barn owl, we have designed a chip that employs a correlation model to report the one-dimensional field motion of a scene in real time. Using subthreshold analog VLSI techniques, we have fabricated and successfully tested a 8000 transistor chip using a standard MOSIS process.

A 23-ns 1-Mb BiCMOS DRAM

Abstract: A 1-Mb BiCMOS DRAM having a 23-ns access time is described. The DRAM uses a direct sensing technique and a nonaddress-multiplexing configuration. This technique combines the NMOS differential circuit on each pair of data lines with a common highly sensitive bipolar circuit. The resulting chip has been verified to have high-speed characteristics while maintaining a wide operating margin and a relatively small chip size of 62.2 mm/sup 2/, in spite of a 1.3- mu m lithography level. >

Semiconductor integrated circuit chip having an identification circuit therein

Abstract: A semiconductor integrated circuit chip has an identification circuit connected between a power voltage supply terminal and one of the input terminals of the chip. The identification circuity includes a voltage limiter to limit the input potential difference between the power voltage supply terminal and the input terminal to a predetermined voltage level. The identification circuit further includes an option device connected to the voltage limiter to provide identification information of the chip. According to the identification circuit, chip identification testing may be achieved with existing input/output and power supply terminals, thereby eliminating the need for extra test and diagnosis pins or additional identification equipment employed during testing.

Combined flat capacitor and tab integrated circuit chip and method

Abstract: A capacitor, having an area smaller than the top area of a chip, is attached above the top of a tape-automated-bonded (TAB) chip and short bonded wires or TAB leads interconnect the capacitor electrodes with the power and ground pads on the chip The interconnections are made as short as possible, with a maximum distance therebetween and with the greatest number which will reduce the inductance of the leads The power and ground pads may contain inwardly extending bonding regions for wire bonds or flip chip capacitor attachment

Echo cancellation in multi-frequency differentially encoded digital communications

Abstract: A differentially encoded digital signal waveform is generated as a discrete time representation of a desired analog signal utilizing multi-frequency modulation techniques. The computational capability of present day, industry-standard microcomputers equipped with a floating point array processor or digital signal processor chip is utilized to perform digital frequency encoding and compute both discrete Fourier transforms and inverse discrete Fourier transforms to provide a transmitter and receiver system utilizing suitably programmed microcomputers coupled by a communications channel.

Multiple circuit chip mounting and cooling arrangement

Abstract: A circuit chip mounting arrangement for use in a multiple chip unit (MCU) of a computer is disclosed which provides high chip packing density to decrease signal path lengths and thereby increase operational frequency. Chip mounting assemblies are employed which include a centrally located metal heat sink block attached to a chip site on the MCU base. A plurality of circuit chips are attached by their top sides to the front and back sides of the heat sink block with a thermally conductive electrically insulating adhesive. The chips are electrically connected to vertically disposed interconnect boards on either side of the heat sink block, and corresponding flex circuits are employed to connect the interconnect boards to bonding pads on the chip site. A pair of the chip assemblies can be disposed on a single chip site of the MCU, and any desired number of circuit chips can be disposed in each chip assembly.