Showing papers on "Current divider published in 2015"

A Four-Way Microstrip Filtering Power Divider With Frequency-Dependent Couplings

Abstract: A four-way microstrip power divider is designed with bandpass filtering response The synthesized inline filter has a generalized Chebyshev response, where frequency-dependent couplings are utilized All of the critical parameters, including the characteristic impedances and electrical lengths, can be determined by our derived closed-form formulas By extending the inline filter, the configuration of four-way power divider is obtained Then, three isolation resistors are properly selected according to the even-/odd-mode analysis The proposed four-way filtering power divider has low in-band insertion loss and high frequency selectivity It can provide the in-band return loss and isolation between outputs better than 167 and 175 dB, respectively

Enhanced locking range technique for frequency divider using dual-resonance RLC resonator

Abstract: An enhanced locking range technique for a CMOS injection-locked frequency divider (ILFD) is presented, which uses a cross-coupled oscillator with a dual-resonance RLC resonator. This ILFD has dual locking ranges at a fixed bias, and the resistor in the resonator is used to have overlapping dual locking ranges so that a single-band wide-locking range is obtained. At the incident power of 0 dBm, the locking range of the divide-by-2 ILFD is 6.7 GHz, from 3 to 9.7 GHz, and the locking range percentage is 105.51%.

Dual-band in-phase filtering power dividers integrated with stub-loaded resonators

Abstract: A compact microstrip dual-band in-phase filtering power divider is presented in this study The integrated two stub-loaded resonators are applied to realise the dual-band filtering response and compact size Based on the even–odd-mode analysis, an analytical model of the proposed power divider structure is presented To improve the frequency selectivity, a source-load cross coupling is introduced by placing input and output coupling lines closely A prototype of the dual-band in-phase filtering power divider centred at 35 and 5 GHz with 3 dB fractional bandwidth of 74 and 42% is designed, fabricated and measured The size of the fabricated power divider is 027λ g × 035 λ g The simulated and measured results are presented and show good agreement

A Compact Four-way Dual-band Power Divider Using Lumped Elements

Abstract: A compact four-way dual-band microstrip power divider is investigated and demonstrated in this letter. The proposed divider reduces the number of transmission line sections by decomposing a single dual-band transformer into a four-way power divider. The theoretical equations for isolation structures and the design procedures of the power divider are presented. For demonstration, a prototype operating at 1 and 2 GHz is fabricated and measured. Good agreements can be observed between the simulated and measured results.

Reconfigurable Unequal Power Divider With a High Dividing Ratio

Abstract: This letter introduces a novel simple structure for the realization of a reconfigurable unequal power divider with a high dividing ratio. Two transmission modes, high power mode and low power mode, can be obtained by this reconfigurable unequal power divider. Only three p-i-n diodes are required without dc blocking capacitors. In addition, the parameters of p-i-n diodes under different bias conditions are involved in matching. For verification, measured results of a reconfigurable 1:5 power divider operated at 5 GHz are given in both transmission modes.

Digitally programmed fractional-order Chebyshev filters realizations using current-mirrors

Abstract: Fractional-order filter realizations with Chebyshev characteristics, approximated by appropriate integer-order topologies, are realized in this work. The employed active blocks were current-mirrors and the derived filters offer the following attractive characteristics: capability of operating in a low-voltage environment, circuit simplicity and resistor-less realization. In addition, a digitally controlled current division network is employed to perform electronic adjustment of the cut-off frequency as well as the order of the filters. The performance of the proposed fractional-order filters is evaluated through the Analog Design Environment of the Cadence software and the Design Kit provided by the AMS 0.35μm CMOS process. The obtained simulation results for orders 1.2, 1.5, and 1.8 confirm that both pass-band and stop-band characteristics of the filters are preserved, while the transition from pass-band to stop-band is performed in fractional-order steps.

A design of single-ended to differential-ended power divider for X band application

Abstract: A five-port power divider with single-ended input and two differential-ended outputs is proposed. The frequency ranges from 9 to 11 GHz with a central frequency of 10 GHz. A stepped impedance line with open stubs is used between differential pairs for broadening the bandwidth and miniaturization of the divider. The divider is fabricated and the measurement results comply with the simulation. A proper performance for differential mode signal is achieved. The insertion loss is within 1.8 dB, the isolation is more than 15 dB, and the return loss is more than 11 dB. In addition, the common mode suppression is reached as well. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:2669–2673, 2015

Generalized, miniaturized, dual-band Wilkinson power divider with a parallel RLC circuit

Abstract: In this paper, a generalized, dual-band Wilkinson power divider consisting of a parallel RLC circuit and two two-section transmission lines is presented, and its circuit parameters, bandwidth ratios for lower and upper bands and miniaturization are discussed. A coupled-line section of loose coupling is introduced to take place a straight transmission line for miniaturization under the assumptions of linear phase characteristics and equal phase velocities of the even- and odd-modes. The relationship between normalized frequency and phase shift as electrical length increased are newly presented, and their S-parameters have also been simulated and discussed in details. Experimental result for miniaturized power divider showed good agreement with theoretical result, and the proposed dividers reported can be applied for practical use.

A novel miniaturized Gysel power divider using lowpass filter with harmonic suppression

Abstract: This paper presents a new design of a compact Gysel power divider with harmonic suppression. It is comprised of the six similar lowpass filters instead of the six conventional transmission lines in the Gysel power divider. The proposed power divider not only effectively reduces the occupied area to 35%, but also features the higher order harmonic rejection. Simulation and measurement results show good insertion loss, return loss, isolation, and wide stopband bandwidth, while maintaining high-power handling capability over the Wilkinson power divider.

Extremely compact ultra-wideband power divider using hybrid slotline/microstrip-line transition

Abstract: A novel extremely compact ultra-wideband (UWB) power divider using hybrid slotline/microstrip-line transition is proposed, designed, and implemented. The even- and odd-mode equivalent-circuit method is applied to the proposed power divider. Measured results show that excellent impedance matching at the input/output ports, amplitude and phase balance, and the isolation between the two output ports are observed within the UWB band. The UWB power divider has a simple structure and good performance.

Simple miniaturized Wilkinson power divider using a compact stub structure

Abstract: The paper presents a study on the miniaturization of microwave power dividers/ combiners. The authors propose a modified two-way Wilkinson power divider with dimensions of 33×24mm, twice reduced compared to the standard structure (65×24mm). This new structure has been designed based on an "artificial transmission line" consisting of a microstrip line and two shunt capacitors at its edges where the capacitors are replaced by two open-ended stubs located inside the circuit loop and do not take any additional space. The power divider has good performance at the designed frequency 900 MHz and its bandwidth of over 1 GHz is sufficient for various applications. The simulation has been performed in both Agilent ADS/ Momentum and CST Microwave Studio and good agreement of the results obtained in these design tools was obtained. Two prototypes have been fabricated and tested, and the measurement results fit well with the simulation. This approach can be applied to design other microwave circuits where quarter-wavelength transmission lines are required, and the modified Wilkinson power divider can be used for various applications such as measurement systems or in antenna array feeding circuits.

A 60 GHz frequency divider with quadrature outputs in 130nm SiGe BiCMOS technology for optical OFDM systems

Abstract: A frequency divider providing quadrature outputs up to 30GHz is presented. Rms phase error and rms clock jitter are discussed in the context of OFDM systems, where the usual phase error correction in the digital baseband processor is included. A measurement technique for the static phase error between the in-phase and quadrature signal is proposed using an integrated single-sideband mixer in conjunction with an integrated 1:256 frequency divider. For a 20GHz I/Q output signal a static phase error of 0.16° is obtained from these measurements. The quadrature divider core draws 35mA from a 3.3 V supply and occupies 0.2 mm2 chip area, including output buffers and two differential delay lines for I/Q adjustment.

Extremely wideband in-phase power divider using modified Wilkinson design

Abstract: A planar in-phase power divider with extreme wideband behavior using modified Wilkinson design is presented. Instead of using T-junction at the input port of the traditional design, the proposed divider uses broadside coupled microstrip to slotline configuration. Moreover, the impedance matching of the output ports is significantly improved across several octaves bandwidth using three binomial sections, whereas the isolation between those ports is enhanced across that band using three isolation resistors. The utilized structure is suitable for single layer integration as both the input and output ports are located at the same layer. A prototype of the presented device is designed using a proper theoretical approach, built, and tested. The developed device has a compact size with an overall dimension of 40 × 55 mm2 using the substrate Rogers RO4003 (dielectric constant=3.38, thickness=0.406 mm). While the device can be used for any wideband application, the developed prototype is designed to operate within the band 1-7 GHz, which is used in most microwave-based medical imaging applications. The achieved simulated and measured results show that the proposed device has equal power division between the two output ports with less than 0.2-dB amplitude imbalance, more than 10-dB return loss and 15-dB isolation, and less than 2° phase difference between the two output signals across the extremely wide frequency band 1.2-7 GHz.

Unequal Wilkinson power divider with wide range of arbitrary power division based on recombinant technology

Abstract: An arbitrary ratio Wilkinson power divider with large power dividing ratio is analysed and demonstrated in this study. This kind of Wilkinson power divider is constructed by incorporating equal (or unequal) power divider cells, recombinant structures, extra low power branches and transformers for matching the circuits. The proposed structure is compatible with single-layer printed circuit board fabrication process. The structure is analysed in detail, while the formulas are given as design guidelines. Moreover, this method is extended to unequal power dividers based on three-way Wilkinson power divider with larger dividing ratio. To verify the proposed design approach, the prototypes of 5:1, 7:1 and 11:1 unequal power divider are optimised, fabricated and measured. The measured bandwidth of 20 dB return loss are about 10, 10 and 6%, respectively, while the isolations of the output ports are better than 20 dB. Good agreements can be observed between the simulated and measured results. The phase differences of output ports are within ±3° over 10% fractional bandwidth.

A class of planar multi-band Wilkinson-type power divider with intrinsic filtering functionality

Abstract: This paper focuses on the application of signal-interference techniques to develop planar multi-band Wilkinson-type power dividers. By inserting transversal signal-interference multi-band filtering cells into the branches of the classic Wilkinson-type power-divider scheme, multi-band power-splitting/combining actions with added filtering operation can be attained. Design formulas for this dual-behavior filtering/power-dividing device for a particular class of embedded multi-band filtering cell are provided. Moreover, a 1.6/3/4.4-GHz triple-band microstrip prototype is built and tested for practical validation.

Design of substrate integrated waveguide based power divider for S-band applications

Abstract: In this paper, a SI W based power divider for S-band applications is proposed The proposed power divider is designed using Y-junction configuration on Rogers R04360 substrate with dielectric constant of 615 and substrate thickness of 152 mm The high dielectric constant substrate is selected for the sake of minimizing the dimension of power divider The proposed power divider is numerically analyzed in terms of return loss and output power equality Besides that, various characteristic of power divider is also investigated as an effect of different vias diameter of SIW and different types of transition structure Based on the numerical analysis, the proposed SIW based power divider demonstrates a good performance over the frequency range of 2–36 GHz with return loss less than −15 dB in the 2–24 and 27–36 GHz band The output power equality achieves 34 ± 02 dB approximately

Design of a Traveling-Wave Slot Array Power Divider Using the Method of Moments and a Genetic Algorithm

Abstract: A 1-to-25-way uniform amplitude and linear phase power divider, using slotted rectangular waveguides in the traveling-wave mode, is designed to cover the 71–77-GHz band. The design employs the scattering parameters of three-port couplers computed from the method of moments (MoM) solution to the integral equation of the slot aperture field. Subsequent genetic algorithm (GA) optimization is aimed at maximizing the return loss and combining efficiency and flatness of coupling amplitudes in the whole frequency band. GA utilizes the MoM solution to the coupled integral equations of slot apertures in the entire power divider structure. Simulations indicate the optimized power divider yielding better than 26-dB return loss and greater than 86% efficiency in the 71–77-GHz band for the power divider combiner connected back to back. Computed MoM results have been validated by the commercial code HFSS and also by experimentally measured results. The measured insertion loss of two back-to-back divider–combiners is about 2 dB.

Efficient design technique for pulse swallow based fractional-N frequency divider

Abstract: A new high speed pulse swallow based fractional-N frequency divider circuit has been proposed for the frequency range of 2.2 GHz to 4.6 GHz. Moreover, unlike the previously published pulse swallow based frequency divider, the proposed architecture does not include any reset or reload signal for the swallow counter which is basically triggered by the SR latch circuit. Absence of any frequency dependent delay block or any frequency dependant RC delay network to eliminate the conventional frequency divider problems. The proposed architecture has been implemented in 0.18 μm CMOS and the divider phase-noise at 1 MHz offset frequency is −169.2 dBc/Hz for a carrier signal of 4.6 GHz and the power dissipation from a 1.8 V supply is 13 mW. The proposed frequency divider's swallow counter has no zero division for any counting state which also leads to a higher speed of operation, that has been checked in transistors level simulation. The appropriate figure of merit (FoM) of this divider is 168.40 dB.

Design of wideband single-layer in-phase power divider using microstrip to slotline coupled structure

Abstract: The design of a planar in-phase power divider for wideband applications is presented. The proposed divider uses a broadside coupled microstrip/slotline configuration with an improved isolation between the output ports using suitable isolation resistor. The proposed design is suitable for single layer integration as both the input and output ports are located at the same layer. Although the device can be used for any wideband application, the developed prototype is designed to operate within the band 2-5 GHz, which is used in microwave-based head imaging systems. The simulated and experimental results of the developed divider show equal power division with less than 0.5 dB of additional insertion loss, less than 2 degrees of phase imbalance, more than 13 dB of isolation and more than 10 dB of return loss over the band 2.3-4.7 GHz. It has a compact size with an overall dimension of 30 x 30 mm(2). (c) 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:789-791, 2015

100–166 GHz wide band high speed digital dynamic frequency divider design in 0.13 μm SiGe BiCMOS technology

Abstract: Design of a digital dynamic divider in SiGe bipolar technology is presented in this paper. The proposed digital dynamic frequency divider is based on two latches connected with negative feedback. However, in contrast to the conventional static frequency divider the latching differential pair has been completely omitted to reduce the load for the sensing differential pair to extend the maximum operating frequency. Two versions of dynamic dividers (A and B) are fabricated to validate the concept. The divide ratio for version A is two while that for version B is four. In version B, the divide ratio of four is achieved by cascading a conventional static frequency divider by two in front of version A. The circuits are fabricated in IHP 0.13 μm SiGe BiCMOS technology with ft and fmax of 300 GHz and 500 GHz, respectively. The input referred self-oscillation frequency (SOF) of 149 GHz was measured. With single-ended sine wave clock input, both dividers are operational from 100 to 166 GHz. At dual power supply with Vcc = 3 V and Vee = −1.9 V, the version A and B consume 80 mA and 160 mA (without output buffers), respectively.

A novel compact tunable coupled-line power divider using varactors

Abstract: In this paper, a novel compact tunable coupled-line power divider using varactors is presented. It has a compact circuit due to the coupled line with short electrical length. The operating frequency can be flexibly controlled by the bias voltage because the capacitance of the varactors is regulated by the applied bias voltage. The theory of this power divider is analyzed and a microstrip example of this tunable power divider is designed, fabricated, and measured. The measured results indicate that the operating frequency of the proposed tunable power divider ranges from 0.8 to 1.15 GHz, agreeing well with the simulated result.

Gate Leakage Based Low Power Circuits

Abstract: A low power voltage divider facility using gate leakage characteristics to divide voltage levels of sub-threshold and near-threshold circuits. The divider comprises a gate leakage based divider facility, and, optionally, a capacitive divider facility.

A Gysel power divider with enhanced isolation bandwidth

Abstract: In this paper, a microstrip Gysel power divider with improved isolation bandwidth is presented. The design procedure of the proposed power divider has been described in detail. For verification, two experimental circuits operating at 2GHz with power splitting ratio of 1:1 and 2:1, respectively, have been designed, simulated and measured. The measured results exhibit a bandwidth of 60% based on isolation better than 15dB, which is obviously enhanced compared with that of traditional Gysel power divider.

A 70 GHz static dual-modulus frequency divider in SiGe BiCMOS technology

Abstract: A 2/3 divider in a 130 nm SiGe BiCMOS technology is presented. Inductive shunt peaking was used to optimize the divider for high input frequencies. Two test circuits with and without input balun were manufactured for characterization at high and low input frequencies, respectively. The divider is functional for input frequencies up to 70 GHz and draws 20 mA from a 3.3 V supply. The circuit will enable high-performance frequency synthesizers at 120 GHz and above.

Design of an ultra-wideband power divider with harmonics suppression

Abstract: The design of an ultrawideband (UWB) power divider with harmonics suppression is presented. With the proposed approach, the size of the quarter-wavelength transmission line can be reduced and the high order harmonics can be suppressed. The design equations are deduced by transmission line theory. A prototype power divider operated at UWB band is designed and fabricated. Experimental results show good performance of the proposed design. In addition, a stop-band with rejection level more than 20 dB is from 17.3 to 24.5 GHz. © 2014 Wiley Periodicals, Inc. Int J RF and Microwave CAE 25:299–304, 2015.

VLSI implementation of current mode analog multiplier

Abstract: This paper presents low-voltage, low power current-mode analog multiplier/divider circuit, which is based on current-mode squaring circuit. The trans linear loop is the basic circuit in the realization of MDC (multiplier/divider circuit). Current mode operation has advantage of simple circuitry. The circuit complexity is reduced by reusing MOS transistor for both the squaring circuits. The proposed MDC is designed for implementing in 0.18um CMOS technology, with low voltage(supply voltage of 1.2 V) and low power operation. The circuit power consumption is 317uW.

A design of unequal power divider with positive and negative group delays

Abstract: This paper presents group delay investigation and implementation of unequal power divider with very high power division ratio. The proposed structure consists of Wilkinson power divider and branch-line where direct and coupled ports are terminated with resistors. By analytically study, the group delay associated with transmission paths between 3 and 1 is negative whereas the group delay associated between transmission path 2 and 1 is positive. Moreover, the negative group delay (NGD) characteristics are purely controlled by resistor connected in branch-line. For experimental validation, the power divider with power division ratio of 21.39 dB and NGD of −0.529 ns was designed, fabricated and measured at center frequency of 2.14 GHz.

Dynamic power divider circuits and methods

Abstract: The present disclosure includes dynamic power divider circuits and methods. In one embodiment, a dynamic power divider includes first and second quarter wave lines that receive an input signal and produce first and second signal on second terminals of the lines. Dynamic power division of the input signal uses a variable impedance circuit between the second terminal of the first quarter wave line and the second terminal of the second quarter wave line. The variable impedance may reduce impedance between two output paths as the input signal power increases or increase impedance between the output paths as the input signal power decreases.

A 17 GHz programmable frequency divider for space applications in a 130 nm SiGe BiCMOS technology

Abstract: A programmable frequency divider for fractional-N frequency synthesizers is presented. The input frequency range is from DC to 17GHz for divider ratios from 16 to 255. We show by analysis and time-domain simulations that the quantization noise folding in a fractional-N PLL can be reduced tremendously, if a prescaler between VCO and programmable divider can be avoided by using this high-speed divider. The programmable divider was manufactured in a 130nm SiGe BiCMOS technology. Robust operation is obtained from a supply voltage VCC=3D2.3-3.9 V. The measured divider phase noise floor for a 100 MHz output signal is as low as −156dBc/Hz. The chip occupies 1.7 mm2 including bondpads and draws 154mA from a 2.3V supply.