Showing papers on "Depletion region published in 1979"

Photovoltaic properties of metal‐free phthalocyanines. I. Al/H2Pc Schottky barrier solar cells

Abstract: The photovoltaic properties of Schottky barier solar cells, made by dispersing particles of the x form of mental‐free phthalocyanine in a binder polymer and sandwiching between NESA (SnO2/Sb) and aluminum electrodes, have been studied. A power conversion efficiency of over 6% for transmitted light at low power densities (0.06 W/m2) has been obtained for monochromatic irradiation at 670 nm. At peak solar power density (1400 W/m2) the extrapolated power conversion efficiency (η) for transmitted 670 nm irradiation decreases to 0.01%. The decrease in η with intensity was attributed to a space charge limitation due to nonlinear resistance. The devices exhibit Voc’s as high as 1.1 V, but are still limited by a field dependent quantum efficiency. Analysis of the action spectra of these devices revealed the formation of a thin photoactive depletion region (∼400 A) at the semiconductor/metal interface. These devices are capable of capturing 30% of the solar spectrum within the photoactive region. The effect of pig...

Depletion layer studies in organic films: Low frequency capacitance measurements in polycrystalline tetracene

Abstract: The study of the electrical properties of (metal 1‖ organic ‖metal 2) cells has not led to a consistent model of their origin. On the one hand, conductivity measurements suggest that many organic materials behave as insulators (low carrier concentrations) while photovoltaic properties of some of these same materials may be rationalized using the concepts of semiconductor physics, suggesting that the organic film has a high carrier concentration. In this paper the voltage dependence of the capacitance of a (Al‖tetracene‖Au or Nesatron) cell is investigated in an attempt to better understand this contradiction. The electrical properties of this cell are explained in terms of a model in which depletion layers are made from a high density of immobile trapped charge. The trapped charge can be mobilized by light and then evidence is found for a Schottky depletion region (∼2000 A thick) in the tetracene film.

Low-frequency noise in Schottky barrier diodes

Abstract: The low-frequency excess noise in Schottky barrier diodes has been investigated. In the ideal case where the saturation current is completely determined by thermionic emission of electrons, no 1/ƒ noise will be produced in the barrier. The presence of trap states in the depletion region can lead to generation-recombination noise. At sufficient high forward currents 1/ƒ noise can be generated in the series resistance of the Schottky diode. Deviations from the ideal diode, for example as a result of edge effects, produce 1/ƒ noise and increase at the same time the ideality factor. It is empirically found that the 1/ƒ noise level decreases very rapidly if the ideality factor tends to unity.

Detection of minority-carrier traps using transient spectroscopy

Abstract: A technique for measuring the properties of deep states which trap minority carriers in the depletion region of a Schottky barrier is described. By combining minority-carrier capture and d.l.t.s. the method enables states to be separated according to their capture cross-sections as well as their emission properties. Results on GaP are described.

Deep-depletion breakdown voltage of silicon-dioxide/silicon MOS capacitors

Abstract: The deep-depletion breakdown voltage of silicon-dioxide/ silicon MOS capacitors is determined by the ionization-integral method, with potential distributions computed by two-dimensional relaxation techniques. Calculations cover the range of substrate doping between 1014and 1018cm-3and oxide thickness between 0.01 and 5.00 µm, providing plots of breakdown voltage versus substrate impurity concentration with oxide thickness as parameter. A universal and normalized criterion is derived for field uniformity in terms of the ratio of oxide thickness to the maximum (breakdown) width of the silicon depletion region: this ratio should be larger than 0.3 in order not to have field concentration around the edges of the metal plate.

Deep‐state‐controlled minority‐carrier lifetime in n‐type gallium phosphide

Abstract: Details of a method for the characterization of deep levels with large capture cross sections for minority carriers are presented. This technique has been used to investigate centers in gallium phosphide. Two defects at EV+0.75 eV and EV+0.95 eV are described in detail. Evidence is presented that shows that the shallower of these defects can control the minority‐carrier lifetime in n‐type gallium phosphide and in fact is the dominant recombination center in most epitaxial layers of this material. The technique uses capacitance as a measure of the charge state of the deep levels in the depletion region of a Schottky barrier. This charge state is perturbed by the capture and subsequent thermal emission of minority carriers. The carriers are generated by irradiation of the semiconductor with low‐intensity light at a wavelength near the absorption edge. Minority carriers generated in the neutral material within about a diffusion length of the barrier region are extracted by the depletion field. Majority carri...

Semiconductor device for generating an electron beam and method of manufacturing same

Abstract: The invention relates to a semiconductor, cathode and a camera tube and a display tube, respectively, having such a cathode, based on avalanche breakdown in a p-n junction extending parallel to the surface of the semiconductor body. The released electrons obtain extra energy by means of an accelerating electrode provided on the device. The resulting efficiency increase makes the manufacture of such cathodes in planar silicon technology practical. Since the depletion zone of the p-n junction upon avalanche breakdown does not extend to the surface, the released electrons show a sharp, narrow energy distribution. This makes such cathodes particularly suitable for camera tubes. In addition they find application, for example, in display tubes and flat displays.

Time dependence of depletion region formation in phosphorus‐doped silicon MOS devices at cryogenic temperatures

Abstract: The time dependence of depletion region formation in 1015/cm3 phosphorus‐doped silicon MOS devices in the temperature range 14–25 °K has been observed using three different experiments: fast ramp C‐V measurements, pulsed capacitor measurements, and pulsed transistor measurements. It is observed that the time required to form a depletion region in thermal equilibrium is strongly dependent on the applied gate bias. Following the application of a gate bias from accumulation to deep depletion, a peak is observed in the substrate current versus time. These results are explained by the dependence of the electron‐emission rate from the phosphorus donors on the electric field in the semiconductor (Poole‐Frenkel effect). Calculations from a one‐dimensional model including the field emission effect are shown to predict the major features of the data.

Radiation Damage Coefficients for Silicon Depletion Regions

Abstract: An experimental and analytical study of radiation effects on silicon depletion regions has been performed. Data are presented which yield damage coefficients appropriate for describing the effects of fission neutrons and Co60 gamma rays on depleted regions and on the SiO2-Si interface. A model incorporating these coefficients is described and used to perform calculations of radiation-induced increases in dark (or leakage) current in CCDs, diodes, and JFETs. The model calculations performed involve no adjustable parameters. Agreement between calculations and experimental results is within a factor of < 2 in most cases. Model calculations for these devices are based on the assumption that dark current is primarily attributable to carriers thermally generated at centers in the depletion region bulk. Results of short-term annnealing measurements on CCDs are presented which provide information regarding damage in depletion regions at early times following pulsed neutron bombardment. Evidence of the production of interface states in an MOS device by neutron bombardment is also presented.

Hetero junction semiconductor device

Abstract: A hetero junction semiconductor device having at least one inter-semiconductor hetero junction, which has at least a first non-single-crystal semiconductor region having a first energy gap, a second non-single-crystal semiconductor region having a second energy gap different from the first energy gap and a third non-single-crystal semiconductor region serving as the hetero junction formed to extend between the first and second semiconductor regions and having an energy gap continuously changing from the first energy gap on the side of the first semiconductor region to the second energy gap on the side of the second semiconductor region, and in which the first, second and third semiconductor regions are doped with recombination center neutralizers.

Electronic defect levels in self‐implanted cw laser‐annealed silicon

Abstract: Electronic defect levels in self‐implanted cw Ar‐laser‐annealed silicon have been measured by deep‐level transient spectroscopy. The electron emission spectrum is dominated by two levels near the middle of the silicon forbidden energy band with activation energies of ∼0.49 and 0.56 eV. These levels can be spatially resolved in the depletion layer of Schottky diodes due to a more rapid decrease with distance in the density of the shallower level. In samples receiving a 450 °C furnace anneal (after laser irradiation) an additional level appears at 0.28 eV; the defect density is shown to decrease monotonically with depth into the silicon substrate.

Threshold shifts due to nonuniform doping profiles in surface channel MOSFET's

Abstract: The threshold shift due to ion implantation may be defined as the shift in curves of N_{\inv} versus V G , where N_{\inv} is the inversion layer carrier density per unit area and V G is the gate bias. This definition corresponds to the experimental shift of current versus gate bias curves, because current is proportional to N_{\inv} in the linear regime of operation of the MOSFET (metal-oxide-semiconductor field-effect transistor). In addition, the shift in N_{\inv} versus V G curves is not sensitive to the value chosen for N_{\inv} , provided this value is not so low as to fall within the weak-inversion, subthreshold regime. Therefore, this definition of threshold shift avoids the use of arbitrary criteria for threshold, such as 2φ B (φ B = bulk Fermi level measured from midgap), which have uncertain meaning in implanted structures. Here, the use of N_{\inv} versus V G curves is made practical by introduction of a simplified method of calculation. It is shown how to evaluate N_{\inv} and V G without using a numerical solution of Poisson's equation, by invoking a charge-sheet approximation for the inversion layer and a modified depletion approximation for majority carriers. The resulting formulation applies provided the profile does not vary rapidly within a Debye length of the depletion edge, and provided most of the implant extends beyond the inversion layer. Threshold shift is shown to depend primarily upon the zero-order and first-order moments of the excess surface charge the implant has introduced into the depletion region of the device (the dose and centroid of this portion of the implanted charge). For fully depleted implants, a simple equivalent delta-function implant with the same dose and centroid as the real implant can be used to find threshold, and calculations can be made on a programmable pocket calculator. For a partially depleted implant, the moments of the depleted portion of the implant are needed. In addition, built-in junction effects can become significant. Comparison of the delta-function approach with a slightly more complex calculation for Gaussian implants is made. For fully depleted implants, agreement is complete. For partially depleted implants, a good estimate is obtained by introducing the ideas of "effective dose" and of "clamping of the depletion edge."

An investigation of dark current and photocurrent superposition in photovoltaic devices

Abstract: In the design and analysis of photovoltai cells, a principle of superposition of light and dark currents is usually assumed to apply. This principle states that the current flowing in an illuminated device subject to a bias V is given by the superposition of the short circuit photocurrent and the current that would flow at bias V in the dark. Using a straightforward modification of Shockley's theory of the pn junction diode, the validity of the superposition principle is established here for Si and GaAs homojunction cells exposed to one sun illumination. The argument commences by demonstrating that the quasi-fermi potentials are essentially constant across the depletion region for a device exposed to one sun illumination and biased at a reasonable operating point. Proceeding in this way, it is found that superposition applies even when recombination and photogeneration in the depletion region contribute substantially to both the dark current and the photocurrent. The theoretical argument is confirmed by direct numerical solution of the basic semiconductor equations.

Electric and optical properties of the ''Cu-red'' center in ZnSe

Abstract: Emission and capture rates describing the optical and thermal transitions at the ’’Cu‐red’’ center in ZnSe have been investigated using a modified photocapacitance technique. By keeping the depletion region of a Schottky diode constant during the measurements of transients highly compensated samples could be used, resulting in larger signals than previously possible. This permitted optical‐emission rates for both electrons and holes to be measured with higher accuracy and in a broader temperature region than in previous investigations. The capture cross section of electrons σn was determined in the temperature range 77–200 K. σn increases with decreasing temperature and has a value of 1.4×10−19 cm2 at 77 K.

Rectification at N-N GaAS: (Ga, Al)As heterojunctions

Abstract: n-n Ga07Al03As: GaAs heterojunction structures have been grown by lpe, with 1 × 1015 cm-3 net carriers in the ternary N/W profiling across the heterojunction shows an accumulation region on the GaAs side and a depletion region on the (Ga, Al)As side I/V characteristics at room temperature show significant rectification

Capacitor memory and methods for reading, writing, and fabricating capacitor memories

Abstract: An improved metal dual insulator semiconductor capacitor memory is disclosed The memory contains a plurality of capacitor cells, each cell comprising a semiconductor substrate layer and a high conductivity layer sandwiching two insulator layers The substrate is doped to provide avalanche breakdown in a surface depletion layer at a voltage comparable to the write voltage in the accumulation direction The invention also provides a method of reading stored information without disturbing adjacent cells A small variable voltage is applied across a "flat-band" portion of the hysteresis loop describing the voltage-capacitance relationship for the capacitor memory A change or the absence of a change in the current through the capacitor indicates the state of the capacitor cell Methods to fabricate the memory are also disclosed

Rectification at n-n GaAs:(Ga,Al)As heterojunctions

Abstract: n-n Ga0.7Al0.3As: GaAs heterojunction structures have been grown by l.p.e., with 1 × 1015 cm-3 net carriers in the ternary. N/W profiling across the heterojunction shows an accumulation region on the GaAs side and a depletion region on the (Ga, Al)As side. I/V characteristics at room temperature show significant rectification.

Geometry effects of small MOSFET devices

Abstract: The effects of diminishing MOS inversion channel length or width on device characteristics are discussed. As opposed to the geometric device size, an "electric device size" is established by normalizing all dimensions on an appropriately chosen depletion layer width. It is shown how this "electric size" governs the intensity of geometry effects. DC device modeling methods are reviewed with respect to their ease of application to electrically small devices. Finally, means for reduction of geometry effects are considered.

Photosensitive device arrangement using a drift field charge transfer mechanism

Abstract: A photosensitive element and a photosensitive device arrangement using the element include a charge transfer structure having an electrode layer extending over a photosensitive area of a semiconductor body. In operation, a bias potential is applied to the electrode layer to form a depletion layer in the underlying body portion, and a drift field is produced in the depletion layer which extends in the direction of an edge portion of the electrode layer to permit photogenerated charge carriers to be transmitted towards the edge portion. A preferred structure for producing the desired drift field includes a resistive electrode having first and second connections for applying a potential difference along the resistive electrode. The photosensitive device arrangement further includes a localized charge-storage zone adjacent the edge portion of the electrode layer for collecting the photogenerated charge carriers and a detector circuit for measuring the charge state of the charge-storage zone.

Depletion approximation analysis of the differential capacitance&#8212;Voltage characteristics of an MOS structure with nonuniformly doped semiconductors

Abstract: The semiconductor equations relating the differential capacitance-voltage characteristics of an MOS structure with nonuniformly doped semiconductors have been derived by using the depletion approximation based on the rigorous definition of the depletion layer width. The relationship between the depletion layer width and the differential capacitance is shown to be the same as the one derived using classical model that is sometimes taken for granted. At the same time, it is shown that the differential capacitance arises from the introduction (or removal) of majority carriers from the abrupt space-charge edge. Expressions derived using this model that are necessary to obtain the impurity distributions are the same as those developed by Kennedy et al. The present model will permit the explicit analysis of subthreshold characteristics in ion-implanted MOSFET's even for non-space-charge neutral profiles.

Schottky barrier diode

Abstract: PURPOSE:To obtain a diode functioning at high speed by a method wherein a P layer is formed on a surface of a ringed I layer on an N layer, a common electrode is attached, the contacts of both the N layer and a Schottky barrier property and both the I layer and an ohmic property are made up, and an ohmic electrode is fitted on the back. CONSTITUTION:An I (intrinsic semiconductor) layer 45 is circularly formed on a main surface of an N layer 42 on an N type substrate 41, and a P layer 46 is made up in the region. A metal layer 50 is attached in common on the surfaces of a region 47 surrounded by the I layer and the P layer 46, and both the region 47 and a Schottky barrier contact 51, both the layer 46 and an ohmic contact 52 and both the substrate 41 and an ohmic contact 55 are built up. A layer 56 is an insulating layer. According to this constitution, a composite element in which a Schottky barrier diode and a PIN diode are connected in parallel in the same polarity is formed, a depletion layer finally expands to the whole region 47 and currents in the reverse direction do not flow when the electrode 50 is made negative and voltage is applied, and a diode is obtained which has characteristics more superior than a normal Schottky barrier diode.

Self-aligned semiconductor circuits and process therefor

Abstract: A semiconductor circuit in which a plurality of transistors is provided, the collector regions/contacts and the base regions/contacts of the transistors being mutually self-aligned. In one embodiment, the collectors have conductive layer contacts (such as metal) and are self-aligned to polysilicon base contacts while in another embodiment the base contacts are comprised of a conductive (metal) layer while polysilicon is used for the collector contacts. The collectors of these transistors can be butted to a field oxide to reduce the extrinsic base area and to minimize excess charge storage in the base region. The base contacts, whether polysilicon or metal, etc. provide alternate base current paths so that the removal of the extrinsic base area does not adversely affect the total amount of base current which can flow. The use of a polysilicon layer for the base contacts, where "fingers" are provided by the polysilicon layer, enhances wirability and the mode of fabrication of the structure, since the polysilicon fingers can have an insulating layer (grown oxide) thereover to provide electrical isolation from over-lying conductors. These self-alignment techniques provide enhanced electrical properties since the distance between the base and collector contacts is minimized and since the base-emitter depletion layer capacitance, the stored charge and the base series resistance are reduced. From a processing standpoint, an additional masking step is not required to form the collector regions.

Integrated circuit with I2 L and power transistors and method for making

Abstract: An integrated circuit has a P-type substrate and two N-type epitaxial layers. P-type isolation walls define pockets in the dual-layer epitaxial material, a power transistor being formed in one and an inverted I2 L transistor being formed in another of the pockets. An upper buried layer doped with antimony (N-type) at the interface between the two epitaxial layers extends into the outer epitaxial layer forming a N+ N holes-barrier junction. This junction is spaced from the depletion region of the normally forward biased base emitter junction by from 0.1 to 0.45 holes-diffusion lengths to provide high emitter efficiency in 0.5 to 5 ohm-cm epitaxial material. The P-type bases of the two kinds of transistors have the same depth but the N-type emitter of the power transistor is shallower than the N-type collector of the inverted transistor although formed earlier. Breakdown voltage of the power transistor is thus enhanced while the base width of the I2 L transistor is predictable and uniform being substantially determined by late and independent process steps.

Semiconductor switching device

Abstract: Provided is a semiconductor switching device having a four-layer structure. A second semiconductor layer of the switching device has a depth of 8μ. The thickness of the second semiconductor layer is set at a value less than a value four times the thickness of a depletion layer which is formed in the second semiconductor layer when breakover voltage has been applied to the switching device.

Method of making integrated semiconductor structure having an MOS and a capacitor device

Abstract: This disclosure is directed to an improved semiconductor capacitor structure especially useful in an integrated semiconductor structure with an MOS device and fabrication methods therefor. This semiconductor capacitor is particularly useful for forming the capacitor portion of a single MOS memory cell structure in a dynamic MOS random access memory which utilizes one MOS device in combination with a capacitor. In one specific disclosure embodiment, the semiconductor capacitor comprises a boron (P) implanted region in a substrate of P- type conductivity followed by a shallow arsenic (N) implant into the boron implanted region. The boron implanted region provides a P type conductivity which has a higher concentration of P type impurities than the concentration of impurities contained in the substrate which is of P- type conductivity. Thus, the boron implanted region performs the important function of preventing a surface N type inversion layer from being formed across the semiconductor surface beneath the silicon dioxide insulating layer which could occur across the substrate P- surface if the arsenic implant region was made into the P- substrate without the P type boron implant. The arsenic implant is of N type conductivity and has a higher concentration of impurities than the boron implant region. The dielectric portion of the semiconductor capacitor is the portion of the silicon dioxide layer located on the surface of the arsenic implanted region. A doped polysilicon electrode is formed over this portion of the silicon dioxide insulating layer and provides the other plate of the capacitor structure. In another embodiment that is disclosed, this above described semiconductor capacitor structure or device is combined with an MOS device in a single integrated semiconductor structure in order to provide a single MOS memory cell for dynamic random access memory chip utilizing the MOS device and the capacitor. Preferably, the semiconductor capacitor is shown as a connected extension of either the source or drain region of the MOS device.