Showing papers on "Drain-induced barrier lowering published in 1995"

Experimental investigation of a PtSi source and drain field emission transistor

Abstract: A p‐type PtSi source and drain, no ‘‘gap,’’ metal oxide semiconductor field effect transistor (MOSFET) has been successfully fabricated and experimentally investigated in detail down to 4.2 K. Gate curves (source current versus gate voltage) clearly show that, in the ‘‘on’’ state, the current flow mechanism from the source metal into the channel gradually changes from primarily thermal emission over the small ∼0.2 eV Schottky barrier to holes to completely field emission through the triangular Schottky barrier as the temperature is lowered below ∼100 K. Gate curves for different channel lengths also show minimal short channel effects down to 1.0 μm, in agreement with previous simulations. Drain curves (source current versus drain voltage) demonstrate that the drive current is comparable to that of a conventional MOSFET, and that the Schottky barrier is rendered transparent to the flow of holes when the device is strongly ‘‘on.’’

Method of making asymmetric low power MOS devices

Abstract: Low threshold voltage MOS devices having asymmetric halo implants are disclosed herein. An asymmetric halo implant provides a pocket region located under a device's source or drain near where the source (or drain) edge abuts the device's channel region. The pocket region has the same conductivity type as the device's bulk (albeit at a higher dopant concentration) and, of course, the opposite conductivity type as the device's source and drain. Only the source or drain, not both, have the primary pocket region. An asymmetric halo device behaves like two pseudo-MOS devices in series: a "source FET" and a "drain FET." If the pocket implant is located under the source, the source FET will have a higher threshold voltage and a much shorter effective channel length than the drain FET.

Low voltage one transistor flash EEPROM cell using Fowler-Nordheim programming and erase

Abstract: A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.

Delta doped and counter doped dynamic threshold voltage MOSFET for ultra-low voltage operation

Abstract: A dynamic threshold voltage IGFET such as a MOSFET is operable at voltages of 0.6 volt or less. The threshold voltage of the transistor is reduced to zero volt or less by interconnecting the gate contact and the device body in which the voltage controlled channel is located. The channel region is delta-doped or counter-doped which permits superior performance for high-end VSLI applications. A selective epitaxy on a counter-doped substrate can be used in a counter-doped device. Doped wells can be used in a bulk silicon substrate in forming the devices. Trenching can be used to isolate devices in the doped wells.

Extended drain resurf lateral DMOS devices

Abstract: A high voltage PMOS or NMOS transistor 7 has improved on-resistance by truncating gate field oxide 43 so that drain region 42 may be implanted closer to channel region 49 than possible otherwise. By shortening the physical distance d2 between drain 42 and channel region 49, the drain to source on-resistance of the high voltage device is reduced and the performance of high voltage device 7 is thereby improved.

Single split-gate MOS transistor active pixel sensor cell with automatic anti-blooming and wide dynamic range

Abstract: The size of an active pixel sensor cell is reduced by utilizing a single split-gate MOS transistor and a reset gate. The split-gate transistor includes an image collection region which is formed in the drain region and electrically connected to the floating gate of the transistor. Light energy striking the image collection region varies the potential of the floating gate which, in turn, varies the threshold voltage of the transistor. As a result, the current sourced by the transistor is proportional to the received light energy.

A liquid crystal display driver with threshold voltage drift compensation

Abstract: A shift register for scanning a liquid crystal display includes cascaded stages. A given stage is formed with an input transistor switch that is responsive to an output pulse of a stage upstream in the chain of the cascaded stages. An output pulse of the given stage is produced in a pull-up transistor of a push-pull amplifier. A pull-down transistor is responsive to a control signal that tracks a variation of a threshold voltage of the pull-down transistor. A difference between the control signal and the threshold voltage is maintained small in a manner to reduce a change in a conductivity of the pull-down transistor when a drift in the threshold voltage of the pull-down transistor occurs.

PMOS flash EEPROM cell with single poly

Abstract: A P-channel single-poly EPROM cell has P+ source and P+ drain regions, and a channel extending therebetween, formed in an N-type well. A thin layer of tunnel oxide is provided over the channel and, in some embodiments, over significant portions of P+ source and P+ drain regions. A poly-silicon floating gate overlies the tunnel oxide. A P diffusion region is formed in a portion of the N-well underlying the floating gate and is thereby capacitively coupled to the floating gate. In this manner, the P diffusion region serves as a control gate for the memory cell. Programming is accomplished by coupling a sufficient voltage to the floating gate via the control gate while biasing the source and drain regions to cause the hot injection of electrons from the N-well/drain junction to the floating gate, while erasing is realized by biasing the floating gate, N-well, source and drain regions appropriately so as cause the tunneling of electrons from the floating gate to the N-well, the source, and the drain. In another embodiment, an N-type diffusion region is formed within the P diffusion region and serves as the control gate.

High voltage cmos logic using low voltage cmos process

Abstract: CMOS transistor logic circuitry is permitted to operate at higher power supply voltages while retaining lower voltage processing geometries by inserting input shielding transistors (P1, N1) before the gate terminals of each input switching transistor (P2, N2). Each shielding transistor has a gate terminal coupled to a shield voltage (Vshld) of a magnitude substantially midway between ground potential and the positive power supply voltage. The input signal is conveyed by the source-drain channel of the input shielding transistor to the gate of the switching transistor.

Fabrication of complementary field-effect transistors each having multi-part channel

Abstract: Each of a pair of complementary insulated-gate field-effect transistors is manufactured in an asymmetric lightly doped drain structure that enables the source characteristics to be decoupled from the drain characteristics. Each transistor has a multi-part channel formed with an output portion, which adjoins the drain zone, and a more heavily doped input portion, which adjoins the source zone. The drain zone of each transistor contains a main portion and a more lightly doped extension that meets the output channel portion. The drain extension of each transistor typically extends at least as far below the upper semiconductor surface as the main drain portion so as to help reduce hot-carrier effects. The input channel portion of each transistor is situated in a threshold body zone whose doping determines the threshold voltage. Importantly, the provision of lightly doped source extensions is avoided so that improving the drain characteristics does not harm the source characteristics, and vice versa. In fabricating the complementary transistor structure, the threshold body zone of each transistor is formed at the same time as the drain extension of the other transistor.

Structure for cross coupled thin film transistors and static random access memory cell

Abstract: A pair of thin film transistors formed in adjacent layers of polysilicon. The gate of the first TFT and the source, drain and channel regions of the second TFT are formed in the first polysilicon layer. The source, drain and channel regions of the first TFT and the gate of the second TFT are formed in the second polysilicon layer. A dielectric layer is interposed between the first and second polysilicon layers. The first TFT gate overlaps the second TFT drain region in the first polysilicon layer and the second TFT gate overlaps the first TFT drain region in the second polysilicon layer. In another aspect of the invention, two TFTs are incorporated into a SRAM memory cell. The memory cell includes: (i) a bit line; (ii) an access transistor having a first source/drain and a second source/drain, the first source/drain being electrically connected to the bit line; (iii) a parasitic diode formed between the second source/drain of the access transistor and the substrate; (iv) a pull down transistor having a source, drain, channel and gate; (v) a first TFT having a source, drain, channel and gate, the first TFT gate being coupled to a power supply voltage V cc through an active load device comprising a second TFT having a source, drain, channel and gate, and to a voltage not greater than ground through the pull down transistor; and (vi) a storage node for storing a high voltage representative of a first digital data state or a low voltage representative of a second digital state, the storage node being coupled to the bit line through the access transistor, to the substrate through the parasitic diode, to the pull down transistor gate and to the power supply voltage V cc through the first TFT.

Local thinning of channel region for ultra-thin film SOI MOSFET with elevated source/drain

Abstract: An elevated source/drain structure is described in which the channel region is thinned by local oxidation and wet etch while the source/drain region remained thick. This structure achieves source/drain resistances as small as 300 ohm-μm for NMOS, which makes possible high drive currents in deep submicron thin-film SOI/MOSFET.

Semiconductor device having interlayer insulating film and method for forming the same

Abstract: An insulated-gate field-effect transistor adapted to be used in an active-matrix liquid-crystal display. The channel length, or the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudinal direction of the channel. Offset regions are formed in the channel region on the sides of the source and drain regions. No or very weak electric field is applied to these offset regions from the gate electrode.

Method of fabricating a thin film transistor having vertical channel

Abstract: A thin film transistor having a vertical channel provided according to the invention comprises a vertical channel 4B having a sideways angular U-shaped or "" -shaped cross-section; source and drain areas 5 formed respectively in two ends of the channel 4B, and a gate electrode 7 surrounding a gate insulating layer 6 formed on upper and outer sides of the channel except for the source and drain areas. Accordingly, the satisfactory channel length in less area can be obtained and the leakage current can be reduced when the transistor is in Off state.

Method of fabricating an asymmetric lightly doped drain transistor device

Abstract: A method of fabricating an asymmetric lightly doped drain transistor device. The device's drain region is shielded with a barrier layer when ion implantation is applied to a implant a highly doped source region. A large angle implantation then follows to form a lightly doped pocket region adjacent to the highly doped source region. The implantation forming the pocket region increases the doping concentration along the device's source side which increases the device's threshold voltage diminishing short channel effects.

Field-effect transistor having local threshold-adjust doping

Abstract: An insulated-gate field-effect transistor utilizes local threshold-adjust doping to control the voltage at which the transistor turns on. The local threshold-adjust doping is present along part, but not all, of the lateral extent of the channel. In the transistor structure, a channel zone laterally separates a pair of source/drain zones. The channel zone is formed with a main channel portion and a more heavily doped threshold channel portion that contains the local threshold-adjust doping. Gate dielectric material vertically separates the channel zone from an overlying gate electrode. The transistor is a long device in that the gate electrode is longer, preferably at least 50% longer, than the gate electrode of a minimum-sized transistor whose gate length is approximately the minimum feature size. The long-gate transistor is suitable for use in analog and high-voltage digital portions of a VLSI circuit.

Method of fabricating a sub-quarter micrometer channel field effect transistor having elevated source/drain areas and lightly doped drains

Abstract: A reverse self-aligned field effect transistor having sub-quarter micrometer (<0.25 um) channel lengths, lightly doped source/drain, and shallow junction depths was achieved. The method for fabricating the FET includes a doped pad oxide layer that functions as both an etch stop layer and a diffusion source for the lightly doped drain. The doped pad oxide prevents the substrate from being etched when a channel opening for the gate electrode is etched in a source/drain polysilicon layer. The sub-quarter micrometer channel length was achieved by reducing the channel opening by sidewall spacer techniques. The shallow source/drain junctions out diffused from the polysilicon are about 0.10 to 0.15 um depth, and the lightly doped source/drain junctions are about 0.05 to 0.08 um depth.

Field effect transistor with short channel and manufacturing method therefor

Abstract: On a p-type semiconductor substrate (well region) there are arranged apart from each other an n-type source region and an n-type drain region, a channel region therebetween, and a gate electrode. A pair of p-type channel diffusion regions doped more heavily than the substrate are formed along the channel boundary between the source region and the drain region and the substrate. The channel diffusion region below the drain region is doped with an n-type impurity to achieve a lower active impurity concentration relative to that in the channel diffusion region below the gate electrode.

Method of forming CMOS devices using independent thickness spacers in a split-polysilicon DRAM process

Abstract: NMOS and PMOS devices are formed in a split-polysilicon CMOS process using independent thickness transistor gate spacers, and using a silicon nitride layer as a mask for the p-channel region during an n+ source/drain implant step of the n-channel region. The p-channel spacer is formed significantly thicker than the n-channel spacer, thereby reducing lateral diffusion of p-type dopant species under the p-channel gate and avoiding short channel effects to improve device reliability and performance. P-channel transistor junction depth and lateral diffusion is further reduced by performing an n-channel arsenic source/drain implant before the p-channel source/drain boron difluoride implant, although the p-channel transistor gate is etched before the n-channel gate. Moreover, since the p-channel transistor gate is etched before the n-channel gate, the p-channel gate sidewalls are reoxidized as well as the n-channel gate sidewalls for improved gate oxide integrity.

Method of driving ferroelectric gate transistor memory cell

Abstract: A ferroelectric gate transistor has a structure in which n-type source and drain regions are formed on a p-type semiconductor, a ferroelectric thin film is formed on a channel region between the source and drain regions, and a gate electrode is formed thereon. Memory information is erased by applying a voltage Vg to the ferroelectric to cause poling in the first direction. The memory information is written by applying a voltage VW lower than a coercive voltage of the ferroelectric and having a polarity opposite to that of the voltage Vg to the ferroelectric. The memory information is read out by applying a voltage VDR lower than the voltage VW and having a polarity opposite to that of the voltage Vg to the drain to read a drain current IDS.

Single-transistor electrically-alterable switch employing fowler nordheim tunneling for program and erase

Abstract: A one-transistor, electrically-alterable switch in combination with a pass transistor includes a first MOS transistor having a drain, a gate, and a source, and a pass transistor having a drain, a source and a floating gate. The floating gate is capacitively coupled to the source of the first MOS transistor through a tunneling dielectric. An erase electrode is capacitively coupled to the floating gate through a coupling dielectric.

Double poly split gate PMOS flash memory cell

Abstract: A P-channel MOS memory cell has P+ source and drain regions formed in an N-well. A thin tunnel oxide is provided between the well surface and an overlying floating gate. In one embodiment, the thin tunnel oxide extends over a substantial portion of the active region and the device. An overlying select and control gate is insulated from the floating gate by an insulating layer. The select and control gate including an elongated extension portion for preventing overprogramming of the circuit. The device is programmed via hot electron injection from the drain end of the channel region to the floating gate, without avalanche breakdown, which allows the cell to be bit-selectable during programming. Erasing is accomplished by electron tunneling from the floating gate to the N-well with the source, drain, and N-well regions equally biased. Since there is no high drain/well junction bias voltage, the channel length of the cell may be reduced without incurring and destructive junction stress.

Semiconductor device for improved power conversion having a hexagonal-system single-crystal silicon carbide

Abstract: To provide a field-effect transistor having a large power conversion capacity and its fabrication method by decreasing the leakage current between the source and the drain of a semiconductor device made of hexagonal-system silicon carbide when the gate voltage of the semiconductor device is turned off and also decreasing the electrical resistance of the semiconductor device when the gate voltage of the semiconductor device is turned on. The main current path of the field-effect transistor is formed so that the current flowing between the source and the drain of, for example, a field-effect transistor flows in the direction parallel with the {0001} plane and a channel forming plane is parallel with the {1120} plane. Selected Drawing!FIG. 1

Triple poly PMOS flash memory cell

Abstract: A P-channel MOS memory cell has P+ source and drain regions formed in an N-well. A thin runnel oxide is provided between the well surface and an overlying floating gate. In one embodiment, the thin tunnel oxide extends over a substantial portion of the active region and the device. An overlying control gate is insulated from the floating gate by a first insulating layer. An overlying select gate is insulated from the control gate by an insulating layer. The select gate includes an elongated extension portion for preventing overprogramming of the circuit. The device is programmed via hot electron injection from the drain end of the channel region to the floating gate, without avalanche breakdown, which allows the cell to be bit-selectable during programming. Erasing is accomplished by electron tunneling from the floating gate to the N-well with the source, drain, and N-well regions equally biased. Since there is no high drain/well junction bias voltage, the channel length of the cell may be reduced without incurring any destructive junction stress.

Enhanced GaAs MESFET CAD model for a wide range of temperatures

Abstract: We describe a new and enhanced GaAs MESFET model suitable for implementation in computer aided design (CAD) software packages such as, for example, SPICE. The model accurately reproduces both above-threshold and subthreshold characteristics of GaAs MESFET's in a wide temperature range, from 77 K to 350/spl deg/C. The current-voltage characteristics are described by a single continuous, analytical expression for all regimes of operation. The physics-based model includes effects such as velocity saturation in the channel, drain induced barrier lowering, finite output conductance in saturation, bias dependent series source and drain resistances, effects of bulk charge, bias dependent average low-field mobility, frequency dependent output conductance, backgating and sidegating, and temperature dependent model parameters. The output resistance and the transconductance are also accurately reproduced, making the model suitable for analog CAD. >

Method for programming a nonvolatile memory

Abstract: A method for programming a nonvolatile memory cell having a control gate, a floating gate, a drain, a source, and a channel region disposed between the drain and source, the method includes the steps of applying a first voltage to the control gate to form an inversion layer in the channel region, the first voltage being varied to program at least two threshold levels of the memory cell, applying a second voltage to the drain and a third voltage to the source, the second voltage being greater than the third voltage, monitoring a current flowing between the drain and the source during the programming of the at least two threshold levels, and terminating any one of the first voltage, the second voltage, and the third voltage when the monitored current reaches a preset reference current to thereby stop the programming of the at least two threshold levels.

Electrostatic breakdown protection circuit for a semiconductor integrated circuit device

Abstract: A protection circuit for protecting against electrostatic discharges (ESD) applied to a bonding pad is connected to ground. The ESD is discharged to ground through the protection circuit, which includes a primary transistor for conducting the discharge current to ground and a gate voltage controlling circuit for controlling the gate voltage of the primary transistor. Operation of the protection circuits begins from a low electrostatic voltage, thereby positively enhancing the electrostatic voltage resistance. In particular, when the gate voltage controlling circuit is a secondary transistor, the source terminal of the primary transistor is connected to ground, and the drain terminal is connected to the bonding pad. The source terminal of the secondary transistor is also connected to ground. Its gate terminal and drain terminal are connected to the gate terminal of the primary transistor.

Bias circuit for depletion mode field effect transistors

Abstract: An amplifier (10) receives a bias voltage to the gate of a depletion mode field effect transistor (12). In one embodiment, a bias circuit (20) offsets (22) the bias voltage from a power supply potential (26) to maintain substantially constant drain current over a range of threshold voltages (34,36,38) caused by process and temperature variation. In an alternate embodiment, a transistor (58) in the bias circuit (50) provides an incremental current flow to compensate the bias voltage of the MESFET for variation in threshold voltages. The bias circuit is applicable to other depletion mode field effect transistor circuits having a negative threshold voltage.

Manufacture of electronic devices having thin-film transistors

Abstract: In the manufacture of a large-area electronic device (e.g. an active-matrix liquid-crystal display or other flat panel display), a TFT of improved lifetime stability results from the inclusion of a field-relief region (22) which is of lower doping concentration than the drain region (12) and which is formed in an area (2) of lateral separation between the channel region (21) and the drain region (22). An energy beam (40), e.g. from an excimer laser, is used to provide the field-relief region (22), by laterally diffusing the doping concentration of the drain region (12) along an area (2) of the semiconductor film (20) significantly larger than the thickness of the semiconductor film (20). The method is simple and easily controllable, an advantageous doping profile (FIG. 3b) is obtained along the field-relief region (22) by this lateral diffusion. The laterally-diffused low-doping profile near the channel region (21)increases progressively along the current path to the drain region (12) so avoiding the creation of areas of high field in the separation area (2). Near the drain region the laterally-diffused doping concentration approaches in magnitude the high doping concentration of the drain region (12), so reducing the increase in drain series resistance resulting from the inclusion of the field-relief region (22). The lateral diffusion length is generally an order of magnitude larger than the depths of the drain and field-relief regions (12,22), because the thickness of the thin film(s) limits the vertical diffusion.

Contoured-tub fermi-threshold field effect transistor and method of forming same

Abstract: A Fermi-threshold field effect transistor includes a contoured-tub region of the same conductivity type as the source, drain and channel regions and having nonuniform tub depth. The contoured-tub is preferably deeper under the source and/or drain regions than under the channel region. Thus, the tub-substrate junction is deeper under the source and/or drain regions than under the channel region. The diffusion capacitance is thereby reduced compared to a tub having a uniform tub depth, so that a high saturation current is produced at low voltages. The contoured-tub may be formed by an additional implant into the substrate using the gate as a mask.