Showing papers on "Etching (microfabrication) published in 1980"

Fabrication process for Josephson integrated circuits

Abstract: A process for fabricating experimental Josephson integrated circuits is described that is based primarily on the use of vacuum-deposited Pb-alloy and SiO films patterned by photoresist stencil lift-off. The process has evolved from one previously reported, with changes having occurred in junction electrodes, tunnel barrier formation, layer patterning, device geometry, and minimum linewidths. Films of Pb-In(12 wt%)-Au(4 wt%) alloy (200-800 nm thick) are used for forming junction base electrodes, interferometer controls, and interconnection lines. Tunnel barriers are formed on the base electrode films by thermal oxidation and subsequent sputter-etching in an rf-oxygen plasma. Junction counter electrodes are formed from 400-nm-thick Pb-Bi(29 wt%) alloy films. Ground planes are formed from 300-nm-thick Nb films patterned by subtractive etching and insulated in part by a Nb2O5 layer formed by liquid anodization. Films of the intermetallic compound AuIn2(30-43 nm thick) are used for forming terminating, load, and damping resistors. The Si0 films are used for interlayer insulation, for defining junction areas in interferometers, and as protective coatings. Layer patterning is achieved mainly by means of photoresist lift-off stencils. By utilizing this process, experimental logic and memory circuits containing ≅100 interferometers with lines as small as 2.5 µm in width have been successfully fabricated.

Electron spectroscopy study of silicon surfaces exposed to XeF2 and the chemisorption of SiF4 on silicon

Abstract: The surface chemistry of silicon exposed to reactive XeF2 gas and the chemisorption of SiF4 on Si at −150 and 25 °C have been studied using XPS and AES. While SiF4 can be condensed at −150 °C, XeF2 is dissociatively chemisorbed and Xe does not stick on the surface. For both Si/SiF4 and Si/XeF2 at 25 °C, a layer of SiF2‐like surface species is identified from the characteristic core level chemical shifts. The formation of this fluorinated surface layer hinders the adsorption of SiF4, but XeF2 reacts with this layer to form volatile SiF4. The behavior of fluorine chemisorption on silicon is illustrated for the first time and the role of surface fluorine in the silicon etching process is discussed in light of the new results.

Anisotropic plasma etching of polysilicon

Abstract: Plasma etching of polycrystalline silicon films for fabrication of silicon gate MOS integrated circuits has been studied with emphasis on fine‐line devices. CF4–O2 plasmas, commonly used for etching silicon, are unacceptable for very fine features because the etching is isotropic and load dependent. This results in substantial undercutting and insufficient dimensional control. Several alternative gases were investigated in a parallel–plate reactor. CF3Cl and a 70% CF3Br–30% He mixture were found to provide selectivities of 30:1 and 16:1, respectively, over thermal SiO2, freedom from loading effects and a large vertical to lateral etch rate anisotropy which minimizes undercutting. Extensive measurements of etch rate and edge profile as a function of gas composition were made for C2F6–Cl2 plasmas. Fully anisotropic etching (zero lateral etch rate) was observed at low Cl2 concentrations with a selectivity ≳6:1 over thermal SiO2 when using conventional photoresist masks. The vertical and lateral etch rates an...

A general simulator for VLSI lithography and etching processes: Part II—Application to deposition and etching

Abstract: The extension of the general process simulator SAMPLE to plasma etching and metallization is described The etching algorithm is divided into isotropic, anisotropic, and direct milling components and is suitable for modeling wet etching, plasma etching, reactive ion etching, and ion milling Separate deposition algorithms are used for CVD, sputtering, and planetary deposition With the extension, it is possible to use a simple keyword repertoire to simulate a sequence of photolithography, etching, and deposition steps to obtain device cross sections at each stage of fabrication

Laser‐induced microscopic etching of GaAs and InP

Abstract: Ultraviolet laser photolysis of methyl‐halides has been used to produce localized photoetching of GaAs and InP. A spatial resolution of ≃1μm has been achieved and an etch rate ≳104 times that of the dark reaction demonstrated. A chemical mechanism is proposed and the observed resolution is explained by a simple physical model.

An improved technique for selective etching of GaAs and Ga1−xAlxAs

Abstract: An improved technique is described for selectively etching ’’windows’’ in GaAs crystals with Ga1−xAlxAs (0.30⩽x⩽ 0.80) epitaxial layers. A reduction factor of 10–50 in the sample preparation time is achieved with a good reproducibility.

Computer controlled system for processing semiconductor wafers

Abstract: Automated reactor system and process for etching or otherwise processing semiconductor wafers in a plasma environment. The wafers are carried into and out of a reaction chamber by a conveyor and processed on an individual basis. Within the chamber, an electrode mounted on a swinging arm carries each wafer from the conveyor to a processing position adjacent to a stationary electrode. Gas is admitted to the chamber, and the electrodes are energized to ionize the gas and form a plasma for processing the wafer between the electrodes.

Method of making a high density V-MOS memory array

Abstract: A method for providing high density dynamic memory cells which provides self-alignment of both V-MOSFET device elements and their interconnections through the use of a device-defining masking layer having a plurality of parallel thick and thin regions. Holes are etched in portions of the thin regions with the use of an etch mask defining a plurality of parallel regions aligned perpendicular to the regions in the masking layer. V-MOSFET devices having self-aligned gate electrodes are formed in the holes and device interconnecting lines are formed under the remaining portions of the thin regions. A combination of anisotropic etching and directionally dependent etching, such as reaction ion etching, may be used to extend the depth of V-grooves. A method of eliminating the overhang of a masking layer after anisotropic etching includes the oxidation of the V-groove followed by etching to remove both the grown oxide and the overhang is also disclosed.

GaInAsP/InP stripe‐geometry laser with a reactive‐ion‐etched facet

Abstract: We report the first use of reactive‐ion etching (RIE) to form mirror facets on GaInAsP/Inp double‐heterostructure (DH) lasers (λ∼1.3 μm). The RIE, performed with a Cl2:O2 gas mixture, provides vertical etched walls with no undercutting. Initial laser results demonstrate that quasi‐single‐mode operation and reasonable threshold currents are possible.

Reactive‐ion etching of GaAs and InP using CCl2F2/Ar/O2

Abstract: We describe the reactive ion etching of GaAs, InP, and their derivative compounds using an etch gas composed of CCl2F2, O2, and argon. Etching was generally carried out at pressures between 1 and 10 μ, and power densities below 0.8 W/cm2. Clean etch profiles were obtained with etch rates as high as 0.25 μm/min. A strong dependence of etch rate on pressure was observed with a maximum at 5 μ total pressure. The etch profiles exhibited a ’’negative undercut’’ character which was also dependent upon the total pressure.

Twin-tub CMOS - A technology for VLSI circuits

Abstract: CMOS technology has been developed through several generations of design rules with an n-type substrate (where p-channel transistors were formed) and with a p-tub implanted and diffused region (where n-channel transistors were formed). In order to enable a separate optimization of both transistors and to utilize the dopant control available with implanted layers, a two-tub approach was adopted. Utilizing lightly doped epi on an n+substrate (for latch-up protection), nitride-masked self-aligned tubs, 1016cm-3surface doping and 600A gate oxides, an 8-mask CMOS process (named 'Twin-Tub") was formulated. The combination of n on n+epi and careful I/O layout renders the circuits latch-up free. Novel aspects of the process, the devices it produces and finally the resultant circuit performance are herein described.

Improved efficiency of CdSe photoanodes by photoelectrochemical etching

Abstract: By illuminating a CdSe photoanode in an electrolyte in which it is photoelectrochemically unstable, a selective etching of the CdSe to a matte black surface occurs with formation of small pits (≈1000 A diameter). This photoelectrochemical etch was found to improve the output characteristics of the CdSe‐polysulfide photoelectrochemical cell through an increase in short‐circuit current (SCC) for single‐crystal CdSe, and an increase in fill factor and SCC for polycrystalline CdSe, where the improvement is more marked. This increase could be explained only partly through decreased reflectivity of the surface, and is probably connected with removal of (near) surface recombination centers.

Directional reactive ion etching at oblique angles

Abstract: Directional reactive ion etching (RIE) at oblique angles is possible using a simple grid‐covered structure (Faraday cage) in conventional parallel‐plate sputter etching equipment. Oblique‐angle etching, as is possible in any ion‐beam system, has been demonstrated using the etchant ions from CHF3 gas on a fused‐silica substrate. The first detailed measurements of the angular etch dependence of RIE show a strong similarity to those of an ion‐beam system (no chemical etching).

Plasma etching of silicon

Abstract: By utilizing a fluorine-containing gaseous compound in a plasma etching process, isotropic etching of monocrystalline silicon (48) and doped or undoped polycrystalline silicon (54) is achieved. The etching processes, which are applicable, for example, to pattern delineation in the processing of semiconductor wafers, are substantially free of any proximity effects and are characterized by a high etching rate at relatively low power levels, high selectivity (with respect to, for example, silicon dioxide) and excellent uniformity. By mixing other gases (for example, chlorine) with the fluorine-containing gas, the amount of undercutting achieved during the etching process can be selectively controlled.

Planar multi-level metal process with built-in etch stop

Abstract: Use of a dual composite mask for a lift-off multi-layered structure process in which a base component layer acts as an etch stop for reactive ion etching of overlying layers.

Refined techniques for staining plagioclase and alkali feldspars in thin section

Abstract: Staining of thin sections for plagioclase and alkali feldspar has not become a universally applied petrographic tool, probably due to difficulties encountered in effectively staining plagioclase. Modifications of standard techniques are described for rapidly producing stained thin sections of high quality. Critical steps in the procedure include pre-polishing with wet 600-grit abrasive paper, using adequate etching times, and applying a K-rhodizonate solution of 0.02 g per 30 ml water, or weaker.

Dry development of Se‐Ge inorganic photoresist

Abstract: Striking rate differences in gaseous plasma etching is found between undoped and Ag‐photodoped Se‐Ge inorganic photoresist. After the Ag photodoping, the plasma etch rate almost disappears and the etch rate ratio reaches 370:1. This leads to the ’’dry development’’ of the Se‐Ge inorganic resists. It is shown that by using the plasma etching technique, fine pattern delineation of less than 1‐μm linewidth is easily possible. Several advantages over wet chemical processing are expected in process simplification and reproducibility.

Linewidth measurement on IC masks and wafers by grating test patterns.

Abstract: Test patterns in the form of diffraction gratings are used for testing and monitoring linewidths on integrated circuit structures. The first and second diffraction orders produed by a laser beam are evaluated to give the width of the grating lines. Measurements on chrome masks show that this technique is accurate to 5% down to linewidths of 0.5 μm. The design of a test set for factory type mask testing is presented. Also, experiments are reported on the testing of patterns on Si wafers directly after. photoresist development and after various etching steps, and an automatic setup for rapid testing of wafers is described.

Bonding of Polymers to Enamel: Influence of Deposits Formed During Etching, Etching Time and Period of Water Immersion

Abstract: A technique for measuring the shear bond strength of composites to etched enamel was developed. The importance of thorough washing of the enamel surface to remove deposits formed during etching was demonstrated by measurements of bond strength and by scanning electron microscopy. One of three orthodontic adhesive systems showed a highly significant increase in bond strength afterimmersion in water for three months. Etching times as short as five seconds gave a bond strength not significantly different from that obtained after a one-minute etch.

Electrical Defects in Silicon Introduced by Sputtering and Sputter‐Etching

Abstract: Sputtering a gold contact on n‐silicon or sputter‐etching the silicon surface prior to deposition of gold results in a Schottky barrier which shows a barrier height which depends on the sputtering voltage and time, and is lower than a corresponding barrier obtained by evaporation of a gold contact. On p‐silicon a sputtered gold contact also shows a barrier height influenced by the sputtering conditions. The modifications of the barrier height are caused by a thin positively charged layer formed in the semiconductor near the metal‐semiconductor junction. During sputter etching the silicon surface is subject to bombardment by Ar ions with energies of about the sputtering voltage. If this voltage is high enough charged centers will be introduced. These centers are also observed after sputter deposition at high voltage. We found that damage is caused by etching at 500V but not at 100V. This indicates that the damage found after sputter deposition was caused by rebounded Ar atoms.

Method of making solar cell

Abstract: A silicon solar energy cell having improved anti-reflective properties and resistance to radiation is composed of a light receiving surface having spaced indentations in the form of inverted pyramids therein. The pyramids, which have their bases in the plane of the light-receiving surface, are produced by masking the surface with a layer resistant to attack by a silicon etchant, forming open regions in the mask, then etching the major surface through the exposed regions.

Process for production of integrated mos circuits with and without mnos memory transistors in silicon-gate technology

Abstract: OF THE DISCLOSURE Integrate MOS circuits with and without MNOS transistors in silicon-gate technology are produced with overlapped contacts using a silicon nitride mask. After production of structured SiO2 layer on a p- or n- doped semiconductor substrate to separate active transistor zones in accordance with the so-called LOCOS process, a silicon nitride layer is deposited onto the surface and is then structured so that the zones in which a gate oxide is to be produced, are uncovered and during gate oxidation, the surface of this structured silicon nitride layer is converted into an oxynitride layer. In contrast to previously known processes, the invention provides self-aligned overlapped contacts with oversized contact holes. The silicon-nitride layer functions as an etch-stop during etching of an intermediate oxide. This avoids under-etching of the polysilicon during contact hole etching. The overlapped contacts allow a substantial increase in the packing and integra-tion density of the so-produced circuits.

Method of making near infrared polarizers

Abstract: A method of producing near infrared polarizers is disclosed using holograc techniques. The interference pattern from two intersecting laser beams is used to produce a plane grating in a layer of photoresist which has been deposited on a layer of conductive material which in turn has been used to coat a substrate. Ion milling reproduces the plane grating in the conductive material layer by selectively etching away a uniform level of material.

Fabrication of 300‐Å metal lines with substrate‐step techniques

Abstract: Metal lines as narrow as 30 nm and as long as 0.5 mm have been fabricated by new techniques based on substrates with surface‐relief steps. Substrate steps with a square profile are formed by ion‐beam etching. Metal wires of triangular cross section are produced by ion‐etching a metal‐coated substrate at an angle, so that the wire is formed in the shadow of the step. An alternative process, direct evaporation onto the step edge, is used to produce lines of very high aspect ratio of height to width.

Textured thin-film Si solar selective absorbers using reactive ion etching

Abstract: Solar selective surface photothermal absorbers consisting of thin‐film Si with a submicron surface texture have been produced by reactive ion etching an evaporated Si film on a Mo layer Such surfaces formed on 316 stainless steel and other substrates have solar absorptivities of 09 and calculated thermal emissivities of ∼02 at 200 °C These selective surfaces are stable in air to 500 °C

Process and gas mixture for etching silicon dioxide and silicon nitride

Abstract: Process and gas mixture for etching silicon dioxide and/or silicon nitride in a plasma environment in a planar reactor. The gas mixture comprises a primary etching gas and a secondary gas which controls the selectivity of the etch. The process is carried out at relatively high pressure and power levels and provides substantially faster removal of silicon dioxide and/or silicon nitride than has heretofore been possible in planar reactors.