Showing papers on "Fault model published in 1992"

Method and system for diagnosis and analysis of products troubles

Abstract: A computer-implemented method and system for diagnosing and system for diagnosing and analyzing fault information of a product is carried out by (a) creating a fault tree representing causal relations between faults and causes thereof base on information of past faults and information concerning the structure and characteristics of the product, and storing the fault tree in a storage unit, the fault tree having branches allocated with weighting coefficients; (b) inputting new fault information of the product into the computer; (c) searching the fault tree in accordance with the weighting coefficients based on the fault information stored in the storage unit to thereby determine the cause of the fault; (d) generating and outputting information concerning an adjustment or repair of the product suffering from the fault based on the determined cause of the fault as well as the information concerning the structure and the characteristics of the product; (e) supplying information concerning the timing of the occurrence of the fault, symptoms appearing in the fault, the cause of the fault and the adjustment and repair data to a host computer through a data collecting station to thereby construct a database for the fault information; and (f) the quality of the product based on all or a part of information of the database

HOPE: an efficient parallel fault simulator

Abstract: The authors present an efficient sequential circuit parallel fault simulator, HOPE, which simulates 32 faults at a time. HOPE is a parallel fault simulator based on single fault propagation. It adopts the zero gate delay model. The key idea incorporated in HOPE is to screen out faults with short propagation paths, and prevent them from being simulated in parallel. The screening process drastically reduces the number of faults simulated in parallel to achieve substantial speedup. The experimental results presented show that HOPE is about two times faster than PROOFS for most ISCAS89 sequential benchmark circuits. >

Fault Model Evolution For Diagnosis: Accuracy vs Precision

Abstract: This paper describes the evolution of accurate fault models, especially with respect to integrated circuit diagnosis. The difference between accuracy and precision is described. The solution to the Byzantine General's problem is described using the voting model for CMOS bridging faults.

On the generation of small dictionaries for fault location

Abstract: Fault location based on a fault dictionary is considered. To justify the use of a precomputed dictionary in terms of computation time, the computational effort invested in computing a dictionary is first analyzed. The number of circuit diagnoses that need to be performed dynamically, without the use of precomputed knowledge, before the overall effort exceeds the effort of computing a dictionary, is studied. Experimental results on ISCAS85 circuits show that for relatively small numbers of diagnoses, a precomputed dictionary is more efficient. A method to derive small dictionaries without losing resolution of modeled faults is then proposed. Methods to compact the resulting dictionary further, using compaction techniques generally applied to fault detection, are then described. Experimental results are presented to demonstrate the effectiveness of the methods presented. Internal observation points to increase the resolution of the test set are also considered.

Possible source models for the 1855 Wairarapa Earthquake, New Zealand

Abstract: The magnitude 8 Wairarapa, New Zealand, earthquake of 1855 was associated with surface rupture along the Wairarapa fault and regional uplift of the southwest of the North Island. Forward elastic dislocation modelling shows that movement on a steeply dipping Wairarapa fault alone cannot account for the recorded deformation data. Modelling of movement on the subduction interface that underlies the Wellington region as well as the Wairarapa fault also fails to produce a satisfactory ill to the data. Although a complex Wairarapa fault model may be able to explain the deformation pattern if its location, subsurface geometry, and slip distribution could be independently constrained, the best effort supported by available data, a flexed model incorporating a left side step of 8 km at the surface, incorrectly locates the deformation. The best fit to the data is obtained from a listric Wairarapa fault model involving rupture on 0 to 50 km width of the deeper part of the subduction interface. The shallower pan of the subduction interface, east of the Wairarapa fault, apparently did not rupture in 1855, and the uplift mechanism for the overlying Aorangi Range remains unexplained. Partitioning of strike-slip and dip-slip components of the relative plate motions may involve separate earthquakes. Seismological verification of listric fault rupture mechanisms is required to determine the plausibility of the listric model presented here, because its implications arc that the 1855 earthquake did not completely account for the relative plate motion in the region.

An efficient non-enumerative method to estimate path delay fault coverage

Abstract: A method for estimating the coverage of path delay faults of a given test set, without enumerating paths, is proposed The method is polynomial in the number of lines in the circuit, and thus allows circuits with large numbers of paths to be considered under the path delay fault model Several levels of approximation, with increasing accuracy and increasing polynomial complexity, are proposed Experimental results to show the effectiveness and accuracy of the estimate in evaluating the path delay fault coverage are presented Combining this nonenumerative estimation method with a test generation method for path delay faults would yield a cost effective method to consider path delay faults in large circuits, which are beyond the capabilities of existing test generation and fault simulation procedures that are based on enumeration of paths >

A functional fault model for sequential machines

Abstract: A fault model at the state transition level is proposed for finite state machines. In this model, a fault causes the destination state of a state transition to be faulty. Analysis shows that a test set that detects all single-state-transition (SST) faults will also detect most multiple-state-transition (MST) faults in practical finite state machines. The quality of the test set generated for SST faults is close to that of the sequences derived from the checking experiment. It is also shown that the upper bound of the length of the SST fault test is 2MN/sup 2/ for an N-state M-transition machine, while that of the checking sequence is exponential. An automatic test generation algorithm and a test generation system, FTG, based on the model show that the test set generated for SST faults achieves high single stuck-at-fault coverage as well as high transistor fault coverage for multilevel implementations of the machine. >

A novel approach to delay-fault diagnosis

Abstract: The authors discuss possibilities of delay fault diagnosis based on fault simulation. They detail the proposed approach based on critical path tracing. A path tracing process is presented with information provided by a logic simulation. Due to the limitations induced by such a simulation, a reliable approach is described based on a six-valued logic simulation. It requires no delay size based fault models and considers only the fault-free circuit. This method is an alternative to fault simulation based approaches and provides perfectly reliable results. It does not require timing evaluations and can be very accurate. >

At-speed delay testing of synchronous sequential circuits

Abstract: Methods to test sequential circuits for delay faults are discussed. A method called at-speed testing is proposed for simplifying test application and reducing test length. A value system to allow at-speed testing is developed, and a test generation procedure is presented. The effect of at-speed test application on the path delay fault model is described. Experimental results are presented, demonstrating the applicability of at-speed testing and its effect on test length. >

Dynamic fault tree models: techniques for analysis of advanced fault tolerant computer systems

Abstract: There is a need for the development of methods for evaluating the vulnerability to failure of goods or systems produced using advanced technology. In particular, the systems for which this evaluation is most critical tend to be complex fault tolerant systems intended for applications where a catastrophic failure can mean loss of life. We contribute to this development of evaluation methods by extending the traditionally combinatorial fault tree evaluation method in such a way that it becomes capable of modeling the full range of system behavior that can be expressed with Markov chains for non-repairable systems. The resulting new modeling technique is called dynamic fault trees and combines the best characteristics of both the fault tree and Markov chain modeling methods. This modeling method requires a two-step procedure that is usually needed for analytical modeling methods: model generation followed by model solution. To further extend the dynamic fault tree method, we develop a one-step algorithm in which the model can be solved as it is generated. This helps ease the use of certain approximation methods for reducing model size and helps optimize the use of computation resources.

An efficient non-enumerative method to estimate path delay fault coverage

Abstract: A method to estimate the coverage of path delay faults of a given test set, without enumerating paths, is proposed. The method is polynomial in the number of lines in the circuit, and thus allows circuits with large numbers of paths to be considered under the path delay fault model. Several levels of approximation, with increasing accuracy and increasing polynomial complexity, are proposed. Experimental results are presented to show the effectiveness and accuracy of the estimate in evaluating the path delay fault coverage. Combining this nonenumerative estimation method with a test generation method for path delay faults would yield a cost effective method to consider path delay faults in large circuits, which are beyond the capabilities of existing test generation and fault simulation procedures, that are based on enumeration of paths.

Advanced fault collapsing (logic circuits testing)

Abstract: The partitioning of faults into equivalence classes so that only one representative fault per class must be explicitly considered in fault simulation and test generation, called fault collapsing, is addressed. Two types of equivalence, which are relevant to the work reported, are summarized. New theorems on fault equivalence and dominance, forming the basis of an algorithm that collapses all the structurally equivalent faults in a circuit, plus many of the functionally equivalent faults, are presented. Application of the algorithm to a set of benchmark circuits establishes that identification of functionally equivalent faults is feasible, and that, in some cases, they are a large fraction of the faults in a circuit. The collapsing algorithm applies not only to combinational designs but to synchronous sequential circuits as well. >

Efficient diagnosis of multiprocessor systems under probabilistic models

Abstract: The problem of fault diagnosis in multiprocessor systems is considered under a probabilistic fault model. The focus is on minimizing the number of tests that must be conducted to correctly diagnose the state of every processor in the system with high probability. A diagnosis algorithm that can correctly diagnose these states with probability approaching one in a class of systems performing slightly greater than a linear number of tests is presented. A nearly matching lower bound on the number of tests required to achieve correct diagnosis in arbitrary systems is proved. Lower and upper bounds on the number of tests required for regular systems are presented. A class of regular systems which includes hypercubes is shown to be correctly diagnosable with high probability. In all cases, the number of tests required under this probabilistic model is shown to be significantly less than under a bounded-size fault set model. These results represent a very great improvement in the performance of system-level diagnosis techniques. >

Delay-fault diagnosis by critical-path tracing

Abstract: A delay fault diagnosis process consisting of simulation of the fault-free circuit with a four-valued logic algebra and critical-path tracing from primary outputs to primary inputs is presented. An alternative to fault simulation, the method requires no delay-size-based fault models and considers only the fault-free circuit. A sensitivity analysis process for improving diagnosis accuracy is also presented. >

The total delay fault model and statistical delay fault coverage

Abstract: Delay testing at the operational system clock rate can detect system timing failures caused by delay faults. However, delay fault coverage in terms of the percentage of the number of tested faults may not be an effective measure of delay testing. A quantitative delay fault coverage model to provide a figure of merit for delay testing is presented. System sensitivity of a path to a delay fault along that path and the effectiveness of a delay test are described in terms of the propagation delay of the path under test and the delay defect size. A new statistical delay fault coverage model is established. A defect level model is also proposed as a function of the yield of a manufacturing process and the new statistical delay fault coverage. A new delay testing strategy driven by the defect level for delay faults is proposed. >

Footwall uplift during normal faulting — implications for structural geometries in the North Sea

Abstract: In recent years, studies of major normal faults in actively extending regions (Aegean, Basin and Range) have documented the vertical motions associated with normal faulting. In addition to the expected subsidence of the hanging wall, it has been found that uplift of the footwall occurs during earthquakes on normal faults. This uplift has been modelled as an elastic effect, treating the fault as a dislocation in an elastic medium. Over geological time scales, however, creep processes below the upper crust act to restore isostatic equilibrium, and so a purely elastic model is not appropriate. Instead, a flexural model is used, in which the upper crust is treated as an elastic layer, overlying a “fluid” substratum. A single fault cutting such a layer gives rise to buoyancy forces that produce reverse drag in both footwall and hanging wall. The wavelength of the reverse drag depends principally on the effective elastic thickness of the lithosphere. The relative amplitude of the footwall and hanging wall vertical movements is dominated by the nature of the fill in the half-graben: loading by sediment pushes the whole structure down, whereas loading by water (sediment-starved) allows more footwall uplift. When a number of faults occur adjacent to one another, their reverse-drag fields overlap to produce the familiar tilted-block profile of normal-faulted terrains. If the major faults are evenly spaced, dips within the fault blocks will be relatively uniform and can be approximated by a “domino” model. Such a fault model can be readily incorporated into a lithospheric stretching model (which causes subsidence of the whole basin), to predict vertical motions relative to a fixed datum such as sea level. We apply these concepts to a variety of fault systems in the North Sea and the mid-Norway shelf. Normal faulting in the Late Jurassic created sediment-starved half-graben with significant bathymetric relief. The footwalls of major platform boundary faults are typically eroded, often showing post-rift sediments resting on basement (e.g., East Shetland Boundary Fault, Brae Fault). In these cases, no direct evidence remains of the amount of footwall rotation, so that the eroded crest might be assumed rigid and erroneously projected into the basin as a regional datum for “section balancing”. However, some boundary faults preserve a condensed footwall sequence, or contain intra-basement reflections, which demonstrate that flexural uplift of the footwall accompanied normal faulting. The Froya Fault (Haltenbanken) is an example of these. Erosion of marginal footwalls was an important source of clastic material, and is, therefore, a major factor in the distribution of Upper Jurassic reservoir formations (e.g., Froya Formation, Brae Formation, Claymore Sst. Member, Fulmar Sand Formation). Within the graben, arrays of fault terraces can be described by the domino model, leading to the conclusion that the extent of erosion on intra-basinal footwalls is largely a function of fault spacing. Thus, in the Brent Province, the Snorre fault block suffered severe erosion during the Late Jurassic extension, whereas on the Brent fault-block erosion was less marked, approximate fault spacings being 30 km and 15 km, respectively. Erosion of intra-basinal footwalls has also been a significant source of Late Jurassic sediment for reservoirs, e.g., the Magnus member and Munin member.

Transition fault simulation for sequential circuits

Abstract: ~ NJ 07974 Abstract - This paper addresses the problem of simukating transition faults in synchronous sequential circuits. After presenting the concept of the transition fault modell for sequential circuits, we present a fault simulation algorithm for transition faults. The algorithm is a modification of PROOFS, a parallel, differential fault simulation algorithm for stuck faults. A novel fault injection technique is pro- posed. Experimental results show that neither a comprehen- sive functional verification sequence nor a test sequence gen- erated by a sequential circuit test generator for stucck-at faults produces a high fault coverage for transition faults. and finite state machine (FSM) synthesis for delay testabil- ity was adtlressedl. A known reset state is required. The method has limited capability of handling large circuits, because it Icquires the extraction of the complete or partial state transition graph. The approach suggested in 1131 assumes that the circuit is fault-free in the initialization and fault propagation phases. This suggestion is valid if the clock is applied alt a lower speed during the initialization and the fault propagation phases and is applied at a rated speed during the fault activation phase. Slow clock for ini- tialization ,and fault propagation is also assumed in (12). To the author's Icnowledge, no delay-fault simulator €or sequential circuits has been reported before. In this paper, we address the problem of simulating transition faults in sequential circuits. We first enhance the transition fault model for the gate-delay faults and the stuck-open faults in synchronous sequential circuits. We assume the input vectors and clock are applied at speed and at a fixed interval during test application. The primary outputs are: also observed at a fixed interval. We use a transition fault of size n clock cycles to model the defects that cause im extra delay of n clock cycles to a transition. We present a fault simulation algorithm for the proposed fault model. Fault simulation results on the ISCAS-89 sequential benchmark circuits are presented in Section 5.

Optimal diagnostic methods for wiring interconnects

Abstract: The problem of generating minimum test sets for diagnosing faults in wiring interconnects on printed circuit boards is addressed. It is assumed that all the nets can be accessed in parallel or through a boundary-scan chain on the board. The fault model includes multiple stuck-at-hand faults. Three methods for three different diagnosis mechanisms are presented. All the diagnostic methods can be further improved by taking advantage of the structural information of wiring interconnects. >

Evaluation and improvement of fault coverage of conformance testing by UIO sequences

Abstract: The fault coverage of testing protocols using unique input/output (UIO) sequences is analyzed. UIO sequences can be efficiently employed in checking the conformance specifications of protocols by using transition testing. The test sequence is found using the rural Chinese postman tour algorithm. A comprehensive fault model is developed, and analytical expressions are given for the fault coverage. The conditions for undetectability are analyzed, and a new algorithm is proposed. Simulation results and illustrative examples are presented. Overhead issues are discussed, and significant improvements are shown for achieving 100% fault coverage. The major advantage of the proposed approach is that it provides the theoretical basis for fault coverage evaluation of protocol testing using UIO sequences. >

A model for sequential machine testing and diagnosis

Abstract: A mathematical framework for the testing and diagnosis of sequential machines is developed. A very general fault model is used in which a faulty machine is represented as a sequential machine, possibly with state and output sets different from those of the good machine. A deterministic finite automaton, called observer, describes the process by which one gains information from the observation of the responses to test sequences. It generalizes the work of Hennie on distinguishing and homing sequences, by modelling all the possible conclusions that could be drawn from observing the circuit under test. A nondeterministic acceptor is derived from the observer; it accepts diagnosing sequences and can also be used to generate test sequences. We then associate probabilities with this nondeterministic acceptor which, together with a stochastic source of input symbols, provides a probabilistic diagnoser. As a particular application we consider the testing and diagnosis of random-access memories by random test sequences. Our model generalizes the work by David et al. on the calculation of the length of a random test sequence required to guarantee that the probability of detection of a fault exceeds a prescribed threshold.

Synthesis for Testability: Binary Decision Diagrams

Abstract: We investigate the testability properties of Boolean circuits derived from (Reduced Ordered) Binary Decision Diagrams. It is shown that BDD-cirucits (or at least) BDD-like circuits are easily testable with respect to different fault models (cellular, stuck-at and path delay fault model). Furthermore the circuits and the test sets can be constructed efficiently.

Go/no-go testing of analogue macros

Abstract: A time-domain go/no-go testing strategy for analogue integrated circuit macros is presented. The strategy is based on exciting an analogue macro with a pseudo-random binary sequence and measuring the transient response generated at the external nodes, thereby eliminating the need for intermediate probing. Four methods of analysing the transient response data are discussed. Of these methods, the response digitisation is the most efficient.

QUIETEST: a methodology for selecting I DDQ test vectors

Abstract: Even high stuck-at fault coverage manufacturing test programs cannot assure high quality for CMOS VLSI circuits. Measurement of quiescent power supply current Iddq) is a means of improving quality and reliability by detecting many defects that do not have appropriate representation in the stuck-at fault model. Since each Iddq measurement takes significant time, a hierarchical fault analysis methodology is proposed for selecting a small subset of production test vectors for I DDQ measurements. A software system QUIETEST has been developed on the basis of this methodology. For two VLSI circuits QUIETEST selected less than 1% of production test vectors for covering all modeled faults that would have been covered by I DDQ measurement for ail of the vectors. The fault models include leakage faults and weak faults for representing defects such as gate oxide shorts and certain opens.

All Tests for a Fault are Not Eyually Valuable for Defect Detection

Abstract: The standard approach to generating a test set for a logic circuit is to select a set of target fault,s and generate one test for each fault (or at least most of the faults). By far, the most common target fault set is composed of single stuck-at faults. However, many potential manufacturing (non-target) defects are not included in the target fault set, so that their detection is just a fortuitous coincidence. In most cases, many different tests may exist which detect a given single stuck-at fault. However, each of these tests (for the same stuck-at fault) may perform very differently in terms of their non-target defect detection. We investigate this phenomenon empirically using a subset of the ISCXS 85 benchmark circuits, and our results show that extremely wide variations in defective part level are possible over sets of tests which all guarantee 100% single non-redundant stuck-at fault coverage. Our objective in this work is the investigation of non-target defects and their impact on defective part level. Here, our thrust is not to develop new test gene rut i o n methods .

Models for fault tolerance in manufacturing systems

Abstract: The field of fault tolerance in computer science and engineering has been thoroughly investigated over a long period of time. A great number of different approaches have been presented on means for improving fault tolerance under certain error conditions in computerized systems. One important area that has introduced computers in order to enhance productivity, flexibility and economy, is manufacturing systems in order to acquire computer-integrated manufacturing (CIM). Using computers in a manufacturing system introduces new sources of difficulties, as well as providing new possibilities for overcoming erroneous situations that might disturb production. The aim of this paper, is to describe how the use of different configurations for a manufacturing system can improve fault tolerance. One specific erroneous situation which may occur in CIM is the partitioning of a network. This situation can be handled satisfactorily by using the suggested manufacturing system configurations. Additional improvements to fault tolerance can be achieved through the introduction of data buffers and material buffers, This approach is described in this paper.

Time and magnitude predictions in shocks due to chaotic fault interactions

Abstract: The equations of motion for a two block, driven, spring loaded fault model with assymetric frictional forces are iterated in the chaotic regime [4,5]. The seismic moment, M0, of each failure episode whose moment exceeds a threshold, M0t, is recorded together with the time, T, since the last significant event (M0>M0t). Preliminary results from prediction-regression analysis indicate that the distribution of points in M0-T space takes the form of a map, Mo(t), T(t) determining the values of M0(t+l), T(t+l). It is suggested that such analysis on real data would be helpful in assessing the applicability of such low-dimensional systems to earthquake modelling and may prove useful in the prediction of real events.

Synthesis for Testability: Binary Decision Diagrams.

Abstract: We investigate the testability properties of Boolean circuits derived from (Reduced Ordered) Binary Decision Diagrams. It is shown that BDD-cirucits (or at least) BDD-like circuits are easily testable with respect to different fault models (cellular, stuck-at and path delay fault model). Furthermore the circuits and the test sets can be constructed efficiently.

Automated Fault Analysis for Hydraulic Systems: Part 1: Fundamentals:

Abstract: Early expert systems for fault analysis tended to be based on shallow, heuristic knowledge. For success in engineering applications, it is argued that the complementary knowledge of the underlying principles (deep knowledge) should also be modelled. An object-oriented software library representing models of components of hydraulic circuits is being built using deep knowledge alone. The software modules within this library are reusable for the construction of model-based expert systems for the performance of failure mode and effects analysis and fault tree analysis on any arbitrary hydraulic circuit.

Switch-level fault detection and diagnosis environment for MOS digital circuits using spectral techniques

Abstract: A switch-level fault detection and diagnosis environment for MOS digital circuits using a compression data method based on a spectral signature is described. The selected fault model includes an MOS transistor permanently On and Off, breaks in internal gate lines, and shorts between two internal nodes of different logic gates, or between the internal nodes within the same complex gate. Circuit editing is performed in modules containing simple switch-level descriptions of the transistors. From the module structure a fault list is created, which will later be processed to eliminate all equivalent faults (fault collapsing). Simulation of the faults contained in this lift, and Walsh or Haar spectral analysis of the outputs, allow a data file to be created, containing a list of faults detected, a list of diagnosed fault groups and the spectral signature for each of these groups. The circuits are tested by comparing the information contained in this file and the data provided by a logic analysis system (LAS).< >