Showing papers on "Gate driver published in 2002"

Multiple-gate SOI MOSFETs: device design guidelines

Abstract: This paper describes computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "/spl Pi/-gate" or "Pi-gate" MOSFET) is introduced. The Pi-gate device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. The simulation results indicate that the the Pi-gate device is a very promising candidate for future nanometer MOSFET applications.

A novel resonant gate driver for high frequency synchronous buck converters

Abstract: This paper introduces a new resonant gate driver for both the top and bottom switches of a synchronous buck converter. A coupled inductor is used to reduce the size as well as to transfer energy between the top and bottom gate driving. A possible semiconductor integration approach is proposed for this resonant gate driver based on a self-adaptive control method. Theoretical analysis, simulation and experimental results prove that the proposed driver can greatly reduce the gate driving loss and that it is well suited to high-frequency applications.

A resonant power MOSFET/IGBT gate driver

Abstract: This paper discusses a resonant gate driver that employs a new method of driving a power MOSFET or IGBT. This resonant gate driver recycles the energy stored in the gate capacitance to reduce the CV/sup 2/f losses associated with a conventional gate driver. Reducing the CV/sup 2/f losses reduces the power consumption and hence the subsequent power dissipation in the resonant gate driver. Less power dissipation enables the driver to operate to higher frequencies. In addition, this topology allows the resonant gate driver to drive the MOSFET gate with a much higher peak to peak voltage swing than it is supplied with and to drive the gate negative in its off cycle. The resonant gate driver can drive the gate with a variable frequency and duty cycle, and very fast switching of the power MOSFET is obtained. An introduction into the low loss capacitance driver circuit topology (patent pending) is presented. The design considerations of implementing a practical MOSFET gate driver using this topology are discussed. Practical implications and considerations of using this topology to drive power MOSFETs/IGBTs are briefly put forward. Experimental test circuits and results are then presented.

Voltage balancing method for IGBTs connected in series

Abstract: This paper presents a new method for balancing voltages of series-connected insulated gate bipolar transistors (IGBTs). This method can be implemented only by adding simple circuits to the gate drive system of the IGBTs, and its effect of balancing the IGBT's collector-emitter voltages during the switching transients is remarkable. This principal strategy and experimental results with series-connected IGBTs are first described. After that, further experimental results are shown from the switching tests of four 2.5-kV flat-packaged IGBTs connected in series. Through the switching tests, superior characteristics of the proposed method have been confirmed.

Characterization and modeling of high-voltage field-stop IGBTs

Abstract: The high-voltage field-stop (FS) insulated gate bipolar transistor (IGBT) is a promising power device for high-power applications thanks to the robust characteristics offered by the FS technology, which combines the inherent advantages offered by punch-through and nonpunch-through structures while overcoming the drawbacks of each structure. In this paper, an electrothermal physics-based model for the FS IGBT is developed. The model contains a detailed description of the FS layer and it is validated using experimental results for a commercial 1200-V/60-A FS IGBT over the entire temperature range specified in the data sheets. The validated model is then used to simulate a 6.5-kV FS IGBT. The simulation results are compared with experimental results published in the literature and good agreement is obtained.

Driving of data lines used in unit circuit control

Abstract: The display matrix section 200 has pixel circuits 210 arranged in the form of a matrix, a plurality of gate lines Y 1, Y 2 . . . that extend in the row direction, and a plurality of data lines X 1, X 2 . . . that extend in the column direction. The scan lines are connected to a gate driver 300, and the data lines are connected to a data line driver 400. A pre-charging circuit 600 or additional current generation circuit is installed for each data line as means for accelerating the charging or discharging of the data line. For each data line, charging or discharging is accelerated by pre-charging or current addition prior to the completion of the setting of the light emission level in the corresponding pixel circuit 210.

Gate driver apparatus having an energy recovering circuit

Abstract: The present invention provides a novel gate driver apparatus in which an energy recovery circuitry is incorporated in a square-wave gate driver. The energy recovery circuitry comprises a first loop circuit for discharging the energy from the gate capacitor to an inductor when the gate driver is turned off, and a second loop circuit for discharging the energy from the inductor to the power supply. Thus, the energy of the gate capacitor is transferred to the power source when the gate driver is turned off, and the gate driver apparatus still maintains its operating flexibility as the square-wave driver and is independent of switching frequency.

Driving circuit and method of driving an organic electroluminescence device

Abstract: A driving circuit in an organic electroluminescent device includes a gate driver unit for sequentially outputting a control signal to select gate lines in a luminescent array unit and a current driver unit for supplying picture data to a data lines in the luminescent array unit corresponding to the gate lines selected by the gate driver unit and selectively driving organic electroluminescent devices of the selected line. The driving circuit includes a minimum gray level judgment unit for determining whether the picture data is of a predetermined minimum gray level; and a switching unit for receiving a control signal according to the determination made by the minimum gray level judgment unit and for selectively supplying a reference voltage or a reference current to the selectively driven organic electroluminescent devices.

Method for making multiple threshold voltage fet using multiple work-function gate materials

Abstract: A shorter gate length FET for very large scale integrated circuit chips is achieved by providing a wafer with multiple threshold voltages. Multiple threshold voltages are developed by combining multiple work function gate materials. The gate materials are geometrically aligned in a predetermined pattern so that each gate material is adjacent to other gate materials. A patterned linear array embodiment is developed for a multiple threshold voltage design. The method of forming a multiple threshold voltage FET requires disposing different gate materials in aligned trenches within a semiconductor wafer, wherein each gate material represents a separate work function. The gate materials are arranged to be in close proximity to one another to accommodate small gate length designs.

High frequency excitation system

Abstract: A power module is adapted to be connected to a voltage source and to supply power to a load. The power module includes a switching bridge that includes a first power transistor and a second power transistor, a first gate controller for driving the first power transistor and a second gate controller for driving the second power transistor. The first gage controller includes a first gate transformer, and a leakage inductance of the first gate transformer forms a resonant circuit with an input capacitance of the first power transistor. The second gate controller includes a second gate transformer, and a leakage inductance of the second gate transformer forms a resonant circuit with an input capacitance of the second power transistor.

Signal transmission film and a liquid crystal display panel having the same

Abstract: A liquid crystal display of compact size is disclosed. The liquid crystal display has a signal transmission film and a single integrated PCB for processing a gate driving signal and data driving signal. The signal transmission film includes a base substrate, a gate driver IC formed on said base substrate, an input pattern formed on said base substrate that applies gate driving signals input from an external device to the gate driver IC, a first output pattern formed on said base substrate that outputs a first gate driving signal processed in said gate driver IC, and a second output pattern formed on said base substrate, that outputs a second gate driving signal bypassing the gate driver IC among the gate driving signals.

Display device having driving circuit

Abstract: A display device of the present invention has a drain driver mounted to a display substrate and having a gate driver and a controller therein, and also has a power source mounted to a flexible printed board and supplying a power voltage to the gate driver. The wiring of a common control signal outputted from the controller and commonly used in control of the gate driver and the power source is formed on the display substrate so that the number of pads for connecting the display substrate and the flexible printed board is reduced. Thus, the construction of the flexible printed board is simplified, and the entire display device can be made compact.

Liquid crystal display having gray voltages with varying magnitudes and driving method thereof

Abstract: A liquid crystal display (“LCD”) having a plurality of gray voltages with varying magnitudes and a driving method thereof. An LCD includes a reference voltage generator changing level of a supply voltage based on a first signal to generate a reference voltage. The first signal varies depending on the surrounding brightness of the LCD, the brightness of the on-screen images of the LCD, and user's manipulation. The LCD also includes a gray voltage generator generating a plurality of gray voltages with magnitudes varying dependent on the magnitude of the reference voltage and a predetermined voltage such as a ground voltage. The LCD further includes a plurality of gate lines transmitting a plurality of gate signals, a plurality of data lines transmitting the gray voltages, and a plurality of pixels. Each pixel has a switching element connected to one of the gate lines and one of the data lines and transmitting the gray voltages to the pixels under the control of the gate signal. The LCD includes a gate driver supplying the gate signals to the gate lines and a data driver selecting the gray voltages based on gray data from an external source to supply to the pixels via the data lines.

Apparatus and method for driving electro-luminescence panel

Abstract: An apparatus and method for driving an electro-luminescence panel wherein pixels in a current driving type electrode-luminescence panel are pre-charged to change a storage voltage of the pixel into the corresponding voltage within a limited scanning time. In the apparatus, a plurality of electro-luminescence cells are arranged at crossings between gate lines and data lines. A gate driver is connected to the gate lines to sequentially drive the gate lines. A data driver is connected to the data lines to apply pixel signals, via the data lines, to the electro-luminescence cells. A pre-charger is provided within the data driver to pre-charge a current into the data lines before the pixel signals are applied via the data lines.

Investigation of parallel operation of IGBTs

Abstract: Widespread application of IGBTs in the past decade has resulted in dramatic improvement in performance of power electronic converters, with simultaneous reduction in costs. In order to further reduce the cost of power electronics systems and improve their reliability it is imperative that techniques for standardized and integrated architectures be adopted, allowing them to be mass-customized for a larger class of applications. One of the key factors that allow broad application of a power switching devices rated at a lower power level across large power levels is ease of parallel operation. This paper is devoted to presenting the results from investigation of parallel operation of IGBT devices. Experimental and computer simulation results are presented.

Experimental demonstration of an ultra-fast double gate inversion layer emitter transistor (DG-ILET)

Abstract: In this letter we demonstrate experimentally a novel ultra-fast power device structure termed the double gate inversion layer emitter transistor (DG-ILET). The device is made in HV CMOS technology and its operation is based on a new physical injection mechanism previously reported and demonstrated experimentally (Udrea et al., 1996), namely the use of a MOS inversion layer as a minority carrier injector. The DG-ILET offers very fast turn-off associated with anode shorted lateral IGBT structures and low on-state voltage drop similar to standard lateral IGBTs without anode shorts. Unlike anode shorted structures, the DG-ILET does not exhibit a long, undesirable on-state snapback.

Switch mode converter that allows 100% duty cycle on gate driver

Abstract: A switch mode converter uses the bootstrap capacitor 30 to operate all the way to 100% duty cycle by adding only a very small amount of low-area extra circuitry. The additional circuitry includes a charge pump 40 and a duty cycle detect device 42. When the duty cycle detect device 42 detects that the converter is attempting to operate in 100% duty cycle, the charge pump 40 provides additional charge to the bootstrap capacitor 30 to ensure that the 100% duty cycle is maintained. Performance into dropout (when the input supply is actually lower than the desired output) is improved. A significant advantage in some applications (notably battery operation) is provided.

Design of IGBT with integral freewheeling diode

Abstract: A new power structure integrating a freewheeling diode in the termination region of a punch-through (PT) insulated gate bipolar transistor (IGBT) is presented. The proposed solution requires virtually no silicon area penalty with respect to a standard IGBT. Static and dynamic experimental results show the correct behavior of both IGBT and freewheeling diode. Further, it is shown that the lateral diode surrounding the multicellular IGBT can support IGBT direct current with low on-state voltage drop. The operation mechanisms of the composite structure and design techniques to improve structure dynamic behavior are investigated through two-dimensional numerical device simulations.

Half-bridge gate driver circuit

Abstract: A half-bridge gate driver cicuit including two separate floating high-side driver cicuits (8 and 8') for operating a switch cicuit having a high-side switch (7) and a low-side swich (9). Each of the driver cicuits (8 and 8') include input control logic wich is referenced to a supply signal with a potential that becomes negative relative to the negative common terminal (12) of the switches, thereby enchancing the operation of the switch cicuit. The circuit may further include signal translation stages (70) for translation control signals to the control logic of the driver cicuits (8 and 8'). The signal translation stages (70) include a plurality of cascoded parasitic transistor (71) which provide a neutralizing capacitance to minimize noise.

Investigation of gate voltage oscillations in an IGBT module under short circuit conditions

Abstract: The gate voltage oscillations in IGBT modules under short circuit conditions were investigated. In IGBT modules containing two chips in parallel, the amplitudes of the gate voltage oscillations were considerably larger than those in modules with single chip configurations. To investigate the gate voltage oscillations, a small signal analysis was performed on parallel circuits containing two IGBT chips. The gate voltage oscillations in parallel chips configurations could be described by a feedback amplifier model. The results of this analysis showed that a high resistive impedance between the gates of the two chips in parallel and a low inductance between their emitters were effective in suppressing the gate voltage oscillations. These effects were confirmed by experiments.

Driving device of liquid crystal display device and driving method thereof

Abstract: A driving device of a liquid crystal display device includes a timing controller for receiving image information and a control signal from a graphic processor through an interface unit; a gate driver integrated circuit for receiving the control signal from the timing controller and a gate on/off power from a DC/DC converter and for supplying a scan signal to a gate pad area in a periphery of a liquid crystal panel; a data driver integrated circuit for receiving the image information and the control signal and for supplying the image information to a data pad area in a periphery of the liquid crystal panel; a first gamma voltage generator for supplying a first gamma voltage to the data driver integrated circuit in a general driving mode; and a second gamma voltage generator for supplying gamma voltages to the data driver integrated circuit in a halftone gray driving mode.

Inrush limiter circuit

Abstract: A junction field effect transistor (JFET), acting as a switch, is coupled between the source and gate of a metal oxide semiconductor field effect transistor (MOSFET). A capacitor is connected in parallel with the MOSFET's “Miller capacitance” by being coupled between the gate and drain of the MOSFET in series with a current limiting resistor. When the JFET is on, it has a low impedance with zero gate voltage and forces the gate to source voltage of the MOSFET to remain near zero and, thus, the MOSFET in a high impedance state, until the capacitor charges to the supply voltage.

A 1V CMOS power amplifier for Bluetooth applications

Abstract: A two-stage power amplifier operated at 2.4GHz has been designed and fabricated in a standard 0.35/spl mu/m CMOS technology. A common-gate Class E power amplifier is employed. A common-gate switch is suitable for low supply voltage operation without degrading the PAE. A pre-amplifier with positive feedback configuration is used to drive the common-gate output stage. The amplifier delivers 18dBm output power with 33% power-added efficiency (PAE) under a 1V supply voltage. With a 1.2V supply, the amplifier delivers 20dBm output power with 35% PAE and can be integrated for class 1 Bluetooth application.

Liquid crystal display control circuit

Abstract: A liquid crystal display control circuit receives a data enable signal DE in synchronization with per-line based display data from a computer, and thereby controls a liquid crystal display. A gate drive signal outputted from a gate driver 23 is generated according to a vertical clock signal VCK in synchronization with a rise of the signal DE. In order to avoid a variation in the period of charging the pixel electrodes which is caused by a delay in the rise timing of the signal DE and a delay in the signal VCK after the last line, a gate enable signal generation circuit 10 is provided in the liquid crystal display control circuit 1, whereby the extended output of the pulse of the gate drive signal caused by the above-mentioned delays is inhibited. This avoids display inhomogeneity caused by a variation in the data enable signal and the like.

Multi-chip module semiconductor devices

Abstract: In a multi-chip module semiconductor device (1), at least one first semiconductor die (20) is mounted on the base portion (11) of a lead-frame (10). A flip chip IC die (30) is mounted by first bump electrodes (31) to electrode contacts (G, S() on the at least one first die (20) and by second bump electrodes (32) to terminal pins (14) of the lead frame. The integrated circuit of the flip chip (30) does not require any lead-frame base-portion area for mounting, and low impedance circuit connections are provided by the bump electrodes (31, 32). The first die (20) may be a MOSFET power switching transistor, with a gate driver circuit in the flip chip (30). The circuit impedance for the switching transistor may be further reduced by having distributed parallel gate connections (G), which may alternate with distributed parallel source connections (S(), and furthermore by having distributed and alternating power supply connections (VCC, GND). The module may comprise two series connected transistors (201, 202) and a control circuit flip chip (300), with bump electrodes (31, 32) and strap connections (181,182) for providing a dc-dc converter without any wire bonds.

Liquid crystal display device and its driving method

Abstract: PROBLEM TO BE SOLVED: To reduce power consumption while providing two screens employing two liquid crystal display panels. SOLUTION: Video display is collectively and simultaneously presented on a main panel and a subpanel by providing a first liquid crystal display panel (the main panel) and a second liquid crystal display panel (the subpanel) having different amounts of display data and a drain driver and a gate driver on the main panel side. On a main panel PNL1 side, a source driver 52 which is provided with a timing controller (TCON) 520 and a video memory (a graphic RAM) 521 and a gate driver 51 are provided. Under the control of the controller 520, the driver 52 supplies video signals to common source lines DLm (DLs) which are connected to the panel PNL1 and a subpanel PNL2. The driver 51 respectively supplies scanning signals to gate lines GLm and GLms which are individually provided to the panels PNL1 and PNL2. COPYRIGHT: (C)2004,JPO

CMOS class AB power amplifier with cancellation of nonlinearity due to change in gate capacitance of a NMOS input transistor with switching

Abstract: To an existing class AB amplifier receiving at a gate of one of a NMOS or a PMOS type CMOS transistor an input signal, the gate of this CMOS transistor having a nonlinear gate capacitance with its switched operation, is added another, opposite-type, one of a NMOS or a PMOS type CMOS transistor that also receives at its gate the same input signal. The nonlinear gate capacitance of this other CMOS transistor is essentially opposite to the nonlinear gate capacitance of the existing CMOS transistor that receives the input signal within the class AB amplifier. This other transistor serves to compensate for the nonlinear gate capacitance of the existing CMOS transistor. Any nonlinearity due, in particular, to any nonlinear change in gate capacitance of a CMOS transistor that is used in particular within a class AB amplifier is thus substantially canceled.

Key power semiconductor device concepts for the next decade

Abstract: The paper presents a comparison of the latest device concepts like the super junction MOSFET, the IGBT and the actual trends in SiC devices. All these devices are capable of blocking voltages in the range of 1000 V, and optimized for different fields of applications. Silicon carbide switching devices exhibit superior properties compared to silicon devices. Low specific on-resistance for high breakdown voltages is believed to be the most outstanding feature of SiC power switching devices. MOSFETs and JFETs capable of blocking 1800 V with a specific on-resistance of 47 m/spl Omega/ cm/sup 2/ are SiC devices attractive for the system designer.

Half-bridge gate driver optimized for hard-switching

Abstract: A half-bridge gate driver circuit including two separate floating high-side driver circuits for operating a switch circuit having a high-side switch and a low-side switch. Each of the driver circuits include input control logic which is referenced to a supply signal with a potential that becomes negative relative to the negative common terminal of the switches, thereby enhancing the operation of the switch circuit. The circuit may further include signal translation stages for translating control signals to the control logic of the driver circuits. The signal translation stages include a plurality of cascoded parasitic transistors which provide a neutralizing capacitance to minimize noise.