Showing papers on "Gate oxide published in 1974"

Double polycrystalline silicon gate memory device

Abstract: A double polycrystalline silicon gate memory device having a floating gate for storing charge and a control gate. The memory device may be used as a single device cell in a memory array. A double self-aligning method is used to form the source and drain regions while doping the gates. Through a predeposition step a lightly doped secondary source and drain regions are formed in alignment with the floating gate prior to the formation of the primary source and drain regions in alignment with the control gate.

Famos—A new semiconductor charge storage device

Abstract: A new non-volatile charge storage device is described. The floating gate avalanche injection MOS (FAMOS) structure is a p -channel silicon gate field effect transistor in which no electric contact is made to the silicon gate. It combines the floating gate concept with avalanche injection of electrons from the surface depletion region of a p - n junction to yield reproducible charging characteristics with long term storage retention.

Deep depletion insulated gate field effect transistors

Abstract: A deep depletion insulated gate field effect transistor is made in a silicon layer on a sapphire substrate, so that its threshold voltage is relatively independent of the thickness of the silicon layer. The silicon layer has two parts, namely, a lower part adjacent to the sapphire substrate which is relatively lightly doped, and an upper part, preferably formed by ion implantation, having a doping concentration on the order of about 2 × 10 15 atoms/cm 3 .

Process for the production of a pair of complementary field effect transistors

Abstract: A process for the production of a pair of complementary field effect transistors which have very short channel lengths. A lightly doped semiconductor layer is deposited on an electrically insulating substrate. A gate insulator layer is applied onto which first and second gate electrodes are formed for the two transistors. A masking oxide layer is applied to the exposed surface regions of the gate insulating layer and the gate electrodes. An opening is etched into the masking layer and gate insulator layer lying adjacent each gate electrode. Charge carriers of first and second types are diffused through the respective openings into the region of the semiconductor layer lying below to dope the same. This doping extends partially into the semiconductor region lying beneath a portion of the respective gate electrodes. All parts of the gate insulator layer except those parts lying beneath the gate electrodes are removed. Charge carriers of the second and first type are diffused into the semiconductor layer on opposite sides of the first and second gate electrodes, respectively, while leaving a portion of the first and second doped regions unchanged beneath the first and second gate electrodes. The doped regions of the semiconductor layer on opposite sides of the first and second gate electrodes provide the source and drain regions of the first and second field effect transistors, respectively.

Drain voltage limitations of MOS transistors

Abstract: A comprehensive investigation has been carried out into the factors which influence the maximum drain voltage of an M.O.S. transistor for normal pentode-like operation. The drain voltage is limited by two principal mechanisms, namely punch-through of the drain depletion region to the source, and breakdown, due to impact ionization in the high field region at the drain edge. A two-dimensional analysis technique for determining the drain voltage at the onset of either punch-through or avalanche breakdown, from a solution of Poisson's equation within the substrate depletion region, is described. The solutions are obtained using finite difference numerical methods which take into account the gate-induced potential profiles at the edge of the source and drain junctions. Boundary conditions of zero effective gate bias and channel current are imposed which simplify the solution of Poisson's equation to an electrostatic one. The punch-through voltage VPT is defined as the drain-to-source voltage at which the longitudinal field at any point along the edge of the source region inverts in sign to permit the drift of minority carriers from source to drain. Breakdown voltage, VBD, however, is determined by the drain voltage at which the maximum field in the device reaches the critical value for avalanche multiplication. Good agreement is achieved between theoretical and practical results for both mechanisms on a wide variety of devices. It is shown that VPT decreases as the channel length and substrate doping concentration decrease and as the oxide thickness and diffusion depth increase. VBD, however, decreases as the channel length, oxide thickness and diffusion depth decrease. Punch-through and breakdown are discussed for gate bias conditions above and below threshold. The sharp fall in breakdown voltage as the gate bias rises above threshold is explained on the basis of injected charge from the channel into the drain depletion region.

Method of making an insulated gate field effect transistor

Abstract: An improved insulated gate field effect transistor is achieved by using a material such as silicon nitride as an ion implantation and oxidation mask overlying a channel region, forming source and drain regions or extensions thereof by implanting ions of a conductivity modifier into a semiconductor substrate, and subjecting the implanted ions to a drive-in diffusion whereby the conductivity modifier ions are redistributed. The ion implantation allows greater control over the amount of conductivity modifier implanted in the lightly doped source and drain regions, the more uniform distribution of conductivity modifier increases the source-drain breakdown voltage, while the use of the silicon nitride mask provides simultaneously for general alignment of the channel region with the effective gate length.

Enhancement mode, Schottky-barrier gate gallium arsenide field effect transistor

Abstract: Disclosed is a new process for fabricating field effect transistors, and particularly enhancement mode and depletion mode Schottky-gate field effect transistors. The process includes the steps of forming a thin layer of gate metalization over the FET channel region, and this gate metalization is then exposed to the bombardment of protons with sufficiently high energy to penetrate through the gate metalization layer and enter the channel region of the FET and there produce deep level energy traps in the channel region. These traps serve to tie up carriers and create donor and acceptor vacancy complexes in the FET channel. This step has the effect of raising the resistivity of the FET channel and is used to make the FET device non-conducting with zero voltage on the gate metalization, i.e., an enhancement mode device.

Method of MOS transistor manufacture

Abstract: An MOS transistor is constructed such that the insulation covering the field of the device and in direct contact with the top surface of the semiconductor material in which the source and drain regions are formed, tapers gradually in thickness to that of the insulation under the gate electrode thereby to prevent abrupt step-heights in the transition region between the field insulation and the gate insulation.

High reliability, low leakage, self-aligned silicon gate FET and method of fabricating same

Abstract: An improved FET structure and method of making same is disclosed. The gate structure of the FET includes a phospho-silicate glass as the insulator and polysilicon as the gate conductor. A thin layer of silicon nitride is formed over the polysilicon and selectively etched so as to remain only over gate areas and other areas where it is desired to extend the polysilicon as a conductor. The unmasked polysilicon is oxidized to form the thick oxide surface coating. The disclosure also describes the use of oxide rings and epitaxial layers to reduce parasitic effects between adjacent FET devices in an integrated circuit.

IGFET on an insulating substrate

Abstract: The breakdown voltage of a novel insulated gate field effect transistor (IGFET), comprising silicon on sapphire (SOS), is substantially doubled by a novel structure wherein a dielectric layer, formed over a channel region of the IGFET, also extends continuously over the surface of the sapphire on opposite sides of the channel region. A polysilicon gate electrode is disposed over the dielectric layer, the gate electrode extending beyond the channel region and being separated from the sapphire substrate by the dielectric layer. The novel method of making the IGFET comprises providing an island of epitaxially deposited doped silicon on the sapphire substrate, and dielectric layer extending continuously over both the island and over portions of the substrate on opposite sides of the island.

Method for manufacturing a semiconductor device having self-aligned implanted barriers with narrow gaps between electrodes

Abstract: An improved method for manufacturing a semiconductor device is disclosed, wherein self-alignment is achieved between implanted barrier regions in the semiconductor substrate and gate portions of the device. The method includes the step of forming an oxide insulating layer over a polycrystalline silicon layer followed by the step of forming a nitride layer over the oxide layer. In this process the gate electrodes that are formed in the device are separated by very narrow gaps.

MOSFET's in the 0°K approximation: Static characteristics of MOSFET's in the 0°K approximation☆

Abstract: The static electrical characteristics below current saturation of MOSFET's with degenerate source and drain regions are calculated for operation at 0°K. The expression for current takes the same form as at room temperature although the flat-band voltage and the voltage across the depletion region at threshold are altered slightly. Potential hills occur in the channel if the gate does not overlap source and drain or if the oxide thickness is increased in the overlap regions. Although these barriers do not affect operation appreciably at room temperature, at 0°K a finite drain voltage (source-drain threshold voltage) is required to initiate conduction. This threshold voltage is included in the theory and the theory is compared with experimental results on p -channel enhancement mode MOSFET's at 4·2°K using hole mobility in the channel as a matching parameter. The channel hole mobility (assumed constant along the channel) is found to be relatively independent of gate voltage but to increase with increasing (negative) drain voltage. Values ranging between 500 and 1000 cm 2 /V-sec are deduced for drain voltages ranging from −1·2 V to −7 V. This compares to channel hole mobility values of 200–300 cm 2 /V-sec at room temperature. It is found that the channel width is on the order of 30–50 A—appreciably less than that at room temperature.

Complementary field effect transistor having p doped silicon gates and process for making the same

Abstract: An insulated gate complementary field effect transistor integrated circuit uses silicon as the gate electrode. The gates of both N- and P- channel transistors are doped with P type impurities, thereby balancing the voltage threshold characteristics of the transistors. After the P type diffusions are completed, a dip etch is used in the process to open the windows for the N type diffusions, thereby avoiding the necessity for applying photo-resist as a mask.

Surface State Generation in MOS Structure by Applying High Field to the SiO 2 Film

Abstract: Effects of high electric fields applied to the gate oxide on MOS devices have been investigated. It is found that conventional MOS devices exhibit a shift of flatband voltage in the negative direction and a decrease of channel conductance as a consequence of the higher field applied (<7×106V/cm) to the gate electrode. These degradations become significant as the applied field is increased regardless of its polarity. They are ascribed to surface state generation at the Si–SiO2 interface and to defect formation in the oxide. The surface state density takes a maximum value, typically 1013/cm2, for an applied field of 8.5×106V/cm at 0.29eV below the conduction band edge. The equivalent parallel conductance vs. gate voltage curve with a gate-controlled diode shows a peak in the weak inversion region in addition to the ordinary peak in the depletion region. The peak in the weak inversion region can be attributed to minority carrier transitions between the surface states and the minority carrier energy band.

Rapid annealing in irradiated CMOS transistors

Abstract: Data characterizing the transient annealing of the gate threshold voltage of contemporary CMOS transistors following exposure to pulsed ionizing radiation are presented and discussed. Devices tested during the study include those fabricated on both bulk silicon and silicon-on-sapphire substrates. Silicon dioxide and aluminum oxide gate dielectrics are evaluated. Leakage current phenomena associated with charge formation in dielectric substrates or dielectric isolation layers are also considered.

High band width emitter coupled logic gate

Abstract: A high band width logic gate including a basic current switch logic block and emitter-follower output transistors. A switchable active circuit current sink is connected between an internal voltage switching node associated with the current switch logic gate and the emitter terminal of the emitter-follower output transistor. The active current sink is switched between a relatively low conductive state to a relatively high nonsaturating conductive state in order to maintain substantially constant current flow through the emitter-follower output transistor during switching of the logic gate in order to significantly improve AC beta roll off characteristics.

Self aligned drain and gate field effect transistor

Abstract: A method for manufacturing a field effect transistor device utilizing the intentional buildup of material on the source region of the device to mask the gate region of the device and obtain an edge on the drain region which closely follows the contour of the edge on the source region thus permitting a narrow, constant width gate region and more uniform capacitance and current flow between the source and drain regions. The material buildup on the source region of the device is a film of metal which is evaporated on a semiconductor wafer so as to define a pattern with one straight edge.

Method and apparatus for measurement of trap density and energy distribution in dielectric films

Abstract: Trap densities in dielectric films can be determined by tunnel injection measurements when the film is incorporated in an insulated-gate field-effect transistor (IGFET). Under applied bias to the transistor gate, carriers (electrons or holes) tunnel into traps in the dielectric film. The resulting space charge tends to change channel conductance. By feeding back a signal from the source contact to the gate electrode, channel conductance is held constant, and by recording the gate voltage as a function of time, trap density can be determined as a function of distance from the dielectric-semiconductor interface. The process is repeated with the gate bias voltage at different levels in order to determine the energy distribution of traps as a function of distance from the interface.

Punchthrough resetting jfet image sensor

Abstract: A solid-state picture pick-up device according to the invention comprises a number of field effect transistors in which the channel region is bounded by two oppositely located gate electrodes each forming a rectifying junction with the channel region and in which the photosensitive junction is formed by a gate electrode which shows a floating potential. Said gate electrode may be charged by simultaneously applying to the other gate electrode a voltage pulse of a sufficiently large amplitude so that punch-through occurs between the gate electrodes. Since in this manner each transistor may be adjusted at its own threshold voltage, the influence of the spreading in the threshold voltages on the output signals is considerably reduced.

Techniques in Failure Analysis of MOS Devices

Abstract: The greatest concern on MOB devices is the physical integrity of the gate oxide. Leakage paths and/or shorts through defect sites in the oxide are a major device reliability problem. Optical microscopy is tedious and often does not resolve the defects. With this in mind, copper decoration techniques were developed that could reveal oxide failures sites down to 0.1?m size. The technique has isolated various failure mechanisms on MOS devices. This failure analysis capability has enhanced the ability to control the MOS process.

Method for forming a field effect device

Abstract: A method for fabricating an insulated gate field effect transistor device which results in a doped polysilicon gate electrode which gate structure can be used for additional interconnection purposes. The method includes forming a thin blanket layer of an insulating material on a semiconductor substrate having source and drain regions and a surface insulating layer, depositing a blanket layer of polysilicon, depositing a blanket layer of Si3N4 and selectively removing leaving areas over the gate region and any desired interconnection pattern, oxidizing the exposed areas of the polysilicon layer, removing the remaining areas of Si3N4, and fabricating a passivation layer and an interconnection metallurgy system on the surface.

Substrate current-a device and process monitor

Abstract: Typical characteristics of an n-channel, enhancement-mode, insulated-gate field effect transistor (IGFET) are shown in Figure 1. The drain current is plotted against the drain voltage for different values of the gate voltage. It can be seen from the figure that, after saturation is reached, the drain current increases again as the drain voltage is further increased. This additional current is attributed to the substrate current and can be measured simultaneously in the substrate lead.

Analysis of interface properties in MOS transistors by means of `charge pumping' measurements

Abstract: When MOS transistors are driven from cut-off to saturation and vice-versa under the control of large gate pulses, a recombination process known as `charge pumping effect' takes place, inducing a leakage current in the substrate connection. The origin of this phenomenon is related to the presence of traps located at the Si/SiO/sub 2/ interface. Convenient experimental procedures enabling to test the influence of various parameters on the phenomenon have been set up. It appears that they provide a simple investigation means of the interface properties. Additional work resulted further in finding other sources of losses, among which the capture of carriers within the gate oxide and the effect of inversion under the bonding areas. A simple theory is developed in order to predict the contribution of these components to the substrate current.

On the effect of gate oxide thickness upon the hall mobility and other magneto-electrical characteristics in most structures

Abstract: P -Channel silicon MOS Halltrons with a different thickness of the oxide under the gate are studied. The measurements are performed in steady-state conditions at room temperature and in a weak magnetic field. Some conclusions about the surface conductivity, Hall mobility and Hall coefficient of carriers in the channel are given. The magneto-electrical characteristics are presented as a function of space charge, surface potential and free charge at the surface of the semiconductor. An explanation of the decrease of the surface conductivity in the nonlinear part of the curve of surface conductivity vs gate voltage is proposed.

Semiconductor devices with conductive layer structure

Abstract: A semiconductor device, for example an integrated circuit comprising insulate gate field effect transistors in which the gate electrodes comprise doped portions of a deposted layer of polycrystalline silicon, wherein a first conductive connection layer extends at least partly on insulating material present on one surface of a semiconductor body, said first layer being insulated from and crossing over an underlying, second conductive connection layer which is of semiconductor material locally deposited on said one surface of the semiconductor body, said second layer and the underlying portion of the semiconductor body comprising a quantity of doping substance introduced via said second layer, for example in the case of a silicon gate circuit introduced at the same time as simultaneously doping the gate electrodes and forming the source and drain regions. The form of undercrossing comprising the second conductive connection layer and the underlying doped portion of the semiconductor body can be provided in a simple manner having a very low series resistance compared with prior art forms of undercrossing.

Measurement of the mobility and concentration of carriers in diffused zones in Si with a gate controlled structure

Abstract: A gate controlled structure is described. It is shown to be a convenient device for measuring mobility and concentration profile of majority carriers in diffused zones. The values of these two parameters are derived from measurements of gate capacitance and resistivity as a function of gate voltage. Various ways of obtaining C-V deep-depletion curves are discussed in order to justify the choice of a gate controlled structure. The measurement technique is discussed. Limitations of the method are due, on one hand, to the depletion approximation and, on the other hand, to an excessive reverse current across the diffused junction induced by the gate voltage. This effect is encountered especially in low-concentration samples, such as ours, in the range of 1015-1016cm-3. For illustration purposes, profiles of a p diffusion used in the MOSC process are measured at the beginning and at the end of the fabrication process.

Electron injection into SiO 2 in the N channel stacked gate MOS tetrode

Abstract: Using a simple model an expression has been derived relating the oxide current to the offset gate voltage in the stacked gate MOS tetrode.

Thin film magnetometer using an orthogonal flux gate

Abstract: The orthogonal flux gate thin film magnetometer comprising an orthogonal flux gate utilizing a rotation magnetization mechanism consisting of a sensing coil wound on a plated wire formed by applying to a conductor a ferromagnetic thin film, an alternating excitation power means for exciting the thin film of the flux gate, an amplitude difference detection circuit means for detecting a difference between positive and negative asymmetrical peak values of the output voltage of the flux gate, and a control means for feedback of the output of the detection circuit to the sensing coil of the flux gate through a feedback circuit and for supplying the output of the control means to an indicating means The magnitude and the polarity of the external magnetic field are sensed from the feedback current which erases the external magnetic field applied to the flux gate