Showing papers on "Metal gate published in 1981"

Semiconductor integrated circuit with a response time compensated with respect to temperature

Abstract: A current-controlling MOS transistor is connected between a power source and an MOS circuit. A control voltage which has a level related to temperature is applied to the gate electrode of the control MOS transistor in order to compensate for current reduction at high temperatures due to the lowering of the mobility of minority carriers. The response time of the MOS circuit is made less dependent on temperature as a result of the current compensation.

Self-refreshing memory cell

Abstract: A self-refreshing non-volatile memory cell having two cross-coupled transistors includes a first floating gate formed between the gate and the channel of said first transistor, said first floating gate overlying by means of a tunnel oxide a portion of the drain of said second transistor and a second floating gate formed between the gate and channel of said second transistor, a portion of said second floating gate overlying by tunnel oxide a portion of the drain of the first transistor. Disturbances in the supply voltage and the gate voltage of the device normally enhance rather than degrade the state of data stored in the cell, thereby providing an extremely long storage time for the cell. The cell is capable of operating simultaneously in a volatile and a non-volatile state.

High performance submicron metal-oxide-semiconductor field effect transistor device structure

Abstract: A novel metal-oxide-semiconductor (MOS) field effect transistor having enhanced oxide thickness at the edge of the gate electrode and having metal silicide regions in the gate electrode and source and drain areas. The enhanced oxide thickness improves interconnect-to-interconnect breakdown voltage in multilevel interconnect devices as well as minimizing gate overlap of source and drain. The metal silicide regions reduce series resistance and improve device speed and packing density.

Data sense apparatus for use in multi-threshold read only memory

Abstract: A read only memory in which the memory cells are single metal gate or silicon gate field effect transistors. Each FET has one of several different thresholds or states. The size or area of the FET gates at the surface of the semiconductor chip are substantially the same regardless of the cells threshold or state. The input to the gates is a ramp, and the cells are rendered conducting by the amplitude of the ramp at a given instant. The output of a cell is fed to several flip-flops, which are synchronized with the input ramp, thereby setting the flip-flops in accordance with the threshold or state of the cell. An encoder converts the output from the flip-flops to a bit binary signal. This permits a very high density ROM, e.g. 128K on a single chip. In another embodiment the input to the gates is a step, and the cells are all rendered conducting simultaneously. The amount of current drawn by each gate however, depends upon the doping in the gate region. The amplitude of the current being drawn by a selected cell is compared with the reference , this in turn is decoded to indicate the state of that cell.

Method of making MOS device by forming self-aligned polysilicon and tungsten composite gate

Abstract: A process is described for forming MOS circuits which include underlying polysilicon members such as gate members covered with metal. In one embodiment, a self-aligning tungsten process is used to cover the polysilicon members. Low temperature "rear end" steps are used to prevent deterioration of the underlying metal. For example, a plasma nitride protective layer is used to cover the metal. The polysilicon/metal members provide reduced resistance and increase the speed of the resultant MOS circuits.

Method of producing a monolithically integrated two-transistor memory cell in accordance with MOS technology

Abstract: A method of producing a monolithically integrated two-transistor memory cell, including a silicon crystal for accommodating the memory cell, a first MOS field effect transistor having a current-carrying channel and both a control gate and a floating gate disposed between the control gate and surface of the crystal, a second MOS field effect transistor having a current-carrying channel and a control gate, an SiO 2 film supporting the gates, a doped polycrystalline silicon layer deposited on the SiO 2 film, the control gates and the floating gate being formed from the doped polycrystalline silicon layer, and an erase area for the floating gate, the improvement which includes covering a part of the silicon crystal intended for the memory cell with an SiO 2 film, forming a part of the gate oxide of the first MOS field effect transistor, forming a window through the SiO 2 film at a location intended for the erase area, re-oxidizing the exposed area of the surface of the crystal in the window and increasing the remaining areas of the SiO 2 film, depositing a first doped polycrystalline silicon layer forming a base of the floating gate, covering the polycrystalline silicon layer with another SiO 2 film, depositing a second doped polycrystalline silicon layer, and forming the control gate of the first MOS field effect transistor from the second doped polycrystalline silicon layer and producing the source and drain zone of the two MOS field effect transistors.

One-dimensional writing model of n-channel floating gate ionization-injection MOS (FIMOS)

Abstract: A physical writing model for an n-channel floating gate ionization-injection MOS (FIMOS) is described. Strength of accelerating field for the injection is calculated, taking the two-dimensional components near the drain junction into account. A new expression for the channel hot electron injection efficiency is also derived, using Baraff's analytic electron distribution function. The gate current, which shows a complicated dependence on the floating gate and drain voltages, has been reasonably formulated by the model. Integrating the gate current, time behavior of the threshold shift is predicted. The result is in reasonable agreement with experimental results.

Storage cell for nonvolatile electrically alterable memory

Abstract: A storage cell of a nonvolatile electrically alterable MOS memory (EAROM) comprises a p-type silicon substrate with n-doped drain and source areas interlinked by an n-channel which is partly overlain by a floating gate extending over part of the drain area. An accessible gate overlaps the floating gate and has an extension overlying a gap between the latter gate and the source area to act as a common control electrode for two series IGFETs defined by the source and gate areas, namely a main or storage transistor and an ancillary or switching transistor. The capacitance of the floating gate relative to the drain area accounts for about half the overall capacitance of that gate relative to the entire semiconductor structure.

Self-aligned gate method for making MESFET semiconductor

Abstract: A MESFET is fabricated using a self-aligned gate process. This process uses a vertical (anisotropic) etch to self-align the gate and source/drain. The vertical etch, in conjunction with a two-level insulator, creates a barrier between the gate and source/drain, so that when metal is deposited and reacted, and any excess removed, the gate is self-aligned with the source/drain, and contacts to the source/drain and gate are well isolated. The alignment obtained by this process is advantageous in that series channel resistance is reduced, and a more compact structure is attained for improvement in packing density.

Method of fabricating high-conductivity silicide-on-polysilicon structures for MOS devices

Abstract: It is known to deposit a refractory metal silicide on a polysilicon gate layer to form a low-resistivity composite structure. For VLSI MOS devices, very-high-resolution patterning of the composite structure is required. In accordance with this invention, a silicide pattern is formed on polysilicon by a lift-off technique. In turn, the patterned silicide is utilized as a mask for anisotropic etching of the underlying polysilicon. High-conductivity composite silicide-on-polysilicon gate structures for VLSI MOS devices are thereby achieved.

Circuit including an mos transistor whose gate is protected from oxide rupture

Abstract: A protected MOS transistor circuit includes an input MOS transistor and a depletion mode MOS transistor having a drain-source current path connected between ground and the gate of the input MOS transistor of obviating rupture of the gate oxide of the input MOS transistor when power is off. The depletion mode MOS transistor's gate receives a control signal only when power is on which renders the depletion mode MOS transistor nonconductive when power is on. The depletion mode MOS transistor is conductive when power is off.

Method of fabricating self-aligned MOS devices and independently formed gate dielectrics and insulating layers

Abstract: A method is described for fabricating MOS devices of the type found in very large scale integrated circuits. According to the method described herein, various gate oxides and insulating layers are fabricated independently of each other in order to independently tailor their thicknesses and thereby provide improved isolation between gate electrodes and interconnects, and independently controllable operating characteristics for multiple gate electrode structures. The fabrication of a dynamic RAM memory cell, an overlapping gate CCD device and a self-aligned MNOS transistor cell are described using the disclosed method.

Power static induction transistor fabrication

Abstract: A method for fabricating a gate-source structure for a recessed-gate static induction transistor. The method is characterized by use of doped polysilicon to fill the recessed gate grooves after the gate grooves have been etched and diffused. The gate grooves have depth greater than width and therefore the surface of the polysilicon layer deposit is substantially planar. The planar surface allows photolithographic techniques to be used for formation of gate contact regions and for depositing of metal gate and source electrodes.

The Feasibility of Electrical Monitoring of Resin Cure with the Charge-Flow Transistor.

Abstract: A new technique for the electrical monitoring of polymerization reactions such as resin cure is described. The technique is based on the charge-flow transistor, which resembles a conventional metal-oxide-semiconductor field-effect transistor (MOSFET), but with a portion of the metal gate replaced by the resin under study. Electrical signals obtained from several resins undergoing cure are presented, along with an electrical circuit model that can account for the principal features of these signals. The dramatic change in signal shape during cure can be related to corresponding changes in both the real and imaginary parts of the dielectric constant.

MOS Transistor circuit with a power-down function

Abstract: An MOS transistor circuit contains at least one "zero" threshold mode transistor to provide a power-down function for the circuit. The "zero" threshold mode transistor is connected between an enhancement-mode MOS driver transistor and a depletion-mode MOS load transistor.

Fabrication method for high power MOS device

Abstract: This disclosure relates to a high power VMOS semiconductor device and fabrication method therefor This VMOS semiconductor device uses a doped polysilicon gate electrode in the V groove and an overlying metal electrode located over an insulation layer protecting the doped polysilicon gate electrode This overlying metal electrode layer covers substantially the entire surface area (except for a small area where electrical contact is made to the doped polysilicon gate electrode) of one surface of the device Another embodiment discloses the use of a self-aligned metal contact to the source or drain region of the VMOS device between adjacent V groov

Short Channel Effects in MOS-Transistors

Abstract: Metal gate MOS-transistors with channel lengths down to approximately 0.5 μm and with gate oxide thicknesses of 19 nm and 34 nm have been fabricated and evaluated. For devices shorter than 1 μm we have found significant short channel effects on threshold voltage, transconductance and subthreshold current. The experimental results have been compared with computer model calculations. A good agreement between measured and calculated values was found regarding the geometry dependence.

Performance of integrated dynamic MOS amplifiers

Abstract: The letter presents measured data of two different types of dynamic amplifier which have been integrated in a standard CMOS metal gate technology. For a supply voltage of ±5 V, gains of 70 dB were obtained with a power dissipation of 58 μW and 500 μW at clock frequencies of 10 kHz and 100 kHz, respectively. The dynamic range exceeds 100 dB.

Implant programmable metal gate MOS read only memory

Abstract: An MOS read only memory or ROM is formed by a process compatible with standard P or N channel metal gate manufacturing methods. The ROM is programmed at a late stage of the process after the metal level of contacts and interconnections has been deposited and patterned. Address lines and gates are polysilicon with an overlying patterned metal layer and output and ground lines are defined by elongated heavily doped regions. Thin gate oxide is formed for every gate position, rather than for only the selected gates as in the prior standard programming method. Each potential MOS transistor in the array is programmed to be a logic "1" or "0" by ion implanting through the polysilicon gates where metal has been removed, using photoresist as a mask.

Isolated gate JFET structure

Abstract: A JFET having the top gate isolated from the bottom gate by an annulus source region and thin channel region and a top gate ohmic contact region isolated from the bottom gate by a deep isolation region. The isolation region and the top gate contact region are exterior the active channel region.

Negative resistance device

Abstract: A negative resistance device utilizing a substrate bias effect is comprised of two MOS transistors of n-channel type and p-channel type. The two transistors are connected at the sources and the gates. The drain of the n-channel MOS transistor is connected to the substrate of the p-channel MOS transistor. The drain of the p-channel MOS transistor is connected to the substrate of the n-channel MOS transistor.

Mos transistor circuit with breakdown protection

Abstract: A protected MOS transistor circuit includes an input (or output) MOS transistor (1) and a protective circuit (10) including a depletion mode MOS transistor (TrP) having a drain-source current path connected between ground and the gate of the MOS transistor and arranged to prevent breakdown of the gate oxide of the protected MOS transistor when power is off as a consequence of stray voltages. When power is on, the depletion mode MOS transistor's gate receives a control signal which renders the depletion mode MOS transistor non-conductive but, when power is off, the depletion mode transistor is conductive so as to ground currents caused by the stray voltages.

Method for fabricating complementary semiconductor devices

Abstract: In a process for forming a CMOS integrated circuit (10) having polysilicon gate electrodes (28, 38) the polysilicon gate electrodes (28, 38) are simultaneously doped with impurities of a single conductivity type, independently of the semiconductor substrate (18). The invention enables the avoidance of the penetration problem which arises when boron is utilized to dope polysilicon. After forming the gate electrodes (28, 38) from a polysilicon layer (128), they are covered by a mask including a silicon oxide layer (130) and a silicon nitride layer (132). Then sources (22, 34) and drains (24, 32) of the n-channel and p-channel transistors (12, 14) are formed and an implantation or diffusion barrier (148) is grown over the sources (22, 34) and drains (24, 32). The mask (130, 132) is removed over the gate electrodes (28, 38) which are then doped with an n-type impurity. Polysilicon resistors (50) may be formed by initially doping the polysilicon layer (128) to a low level of conductivity and protecting the resistor areas (50) by a further mask (138), which may be of polysilicon or silicon nitride, during subsequent doping to a high level of conductivity.

Method of making electrically programmable control gate injected floating gate solid state memory transistor

Abstract: A non-volatile memory structure of the floating gate type is described wherein current carriers are injected onto the floating gate from the control gate as distinguished from the prior art which injects current carriers into the floating gate from the substrate This invention teaches that by tailoring the capacitance between the control gate and the floating gate and the capacitance between the floating gate and the substrate different field intensities are created in the region between the floating gate and the control gate and in the region between the substrate and the floating gate When the field intensity across the capacitor formed between the control gate and the floating gate is greater than the field intensity across the capacitor formed between the floating gate and the substrate, current carriers will be injected onto the floating gate from the control gate

Semiconductor integrated circuit device including a protective resistor arrangement for output transistors

Abstract: An abnormal surge voltage such as frictional static electricity is often applied to the external terminals of a MOSIC. In the past, the output MOS transistor in the MOSIC during normal handling of the device frequently will have its gate insulating film broken down by the application of such an abnormal surge voltage to the drain thereof. In order to prevent the gate insulating film from being broken down, in this manner a resistor is connected between the gate of the output MOS transistor and a drive circuit for driving that output MOS transistor. This construction using a resistor is superior to the construction in which the voltage to be applied to the drain of the output MOS transistor is clamped by the use of suitable clamp means only because, with the resistor arrangement, the output characteristics of the MOSIC are not restricted.

Retro-etch process for forming gate electrodes of MOS integrated circuits

Abstract: A method of electrically isolating a plurality of semiconductor integrated circuit components and for forming gate elements for silicon gate transistors is disclosed whereby extremely narrow line widths can be formed which heretofore have been unattainable by practicing conventional photolithography.

Theoretical study of a channel-doped separate gate Si MOSFET (SG-MOSFET) by two-dimensional computer simulation

Abstract: A new device structure is proposed for Si MOSFET, featuring an insulated gate structure, channel doping, and finite spacing between gate and source and between gate and drain. Two-dimensional numerical analysis shows that punchthrough is suppressed and that minimum gate length, limited bypunchthrough or V T shift, is extended into the submicrometer range.

Method of manufacturing a buried contact in semiconductor device

Abstract: Method of forming buried contact in recessed gate MOSTEK technology is provided. When the buried contact is desired, a MOS transistor is formed and the gate and underlying gate oxide layer removed to expose the substrate. A conducting layer through the aperture formed makes contact to the substrate.