Showing papers on "Multiplexer published in 2001"

Design and results from the APV25, a deep sub-micron CMOS front-end chip for the CMS tracker

Abstract: The APV25 is a 128-channel analogue pipeline chip for the readout of silicon microstrip detectors in the CMS tracker at the LHC. Each channel comprises a low noise amplifier, a 192-cell analogue pipeline and a deconvolution readout circuit. Output data are transmitted on a single differential current output via an analogue multiplexer. The chip is fabricated in a standard 0.25 μm CMOS process to take advantage of the radiation tolerance, lower noise and power, and high circuit density. Experimental characterisation of this circuit shows full functionality and good performance both in pre- and post-irradiation (20 Mrad) conditions. The measured noise is significantly reduced compared to earlier APV versions. A description of the design and results from measurements prior to irradiation are presented.

High-speed architectures for Reed-Solomon decoders

Abstract: New high-speed VLSI architectures for decoding Reed-Solomon codes with the Berlekamp-Massey algorithm are presented in this paper. The speed bottleneck in the Berlekamp-Massey algorithm is in the iterative computation of discrepancies followed by the updating of the error-locator polynomial. This bottleneck is eliminated via a series of algorithmic transformations that result in a fully systolic architecture in which a single array of processors computes both the error-locator and the error-evaluator polynomials. In contrast to conventional Berlekamp-Massey architectures in which the critical path passes through two multipliers and 1+[log/sub 2/,(t+1)] adders, the critical path in the proposed architecture passes through only one multiplier and one adder, which is comparable to the critical path in architectures based on the extended Euclidean algorithm. More interestingly, the proposed architecture requires approximately 25% fewer multipliers and a simpler control structure than the architectures based on the popular extended Euclidean algorithm. For block-interleaved Reed-Solomon codes, embedding the interleaver memory into the decoder results in a further reduction of the critical path delay to just one XOR gate and one multiplexer, leading to speed-ups of as much as an order of magnitude over conventional architectures.

64-bit carry-select adder with reduced area

Abstract: A carry-select adder can be implemented by using a single ripple-carry adder and an add-one circuit instead of using dual ripple-carry adders. A multiplexer-based add-one circuit is proposed to reduce the area with negligible speed penalty. The proposed 64 bit carry-select adder requires 42% fewer transistors than the conventional carry-select adder.

Multifunction interface facility connecting wideband multiple access subscriber loops with various networks

Abstract: An device, called a facilities management platform (FMP) connects current digital and analog carrier networks and packet switched networks of interexchange carriers with high speed multiple access subscriber links implemented over twisted pair lines. The subscriber line is terminated by an access module containing one or more modems. In preferred embodiments, the modems are high-speed digital tethered virtual radio channel or xDSL modems. The FMP interface applies and receives signaling and voice through a digital loop carrier (DLC) via a multiplexer connected directly to the DLC backplane. The multiplexer is controlled by a controller of an access module. It translates data from the subscriber link to the form compatible with the digital backplane to create the appearance of one or more line cards. The FMP also may contain a sound generator to allow it to handle calls through an analog carrier network. The FMP, through the same access module transmits data to and from the modems directly through connected digital networks, such as ATM or SONET, of an interexchange carrier. Through this interface, different network companies can offer competing products through different networks all seamlessly connected through a high speed subscriber line.

256 Meg dynamic random access memory

Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

Method and apparatus for incorporating a multiplier into an FPGA

Abstract: One or more columns of multi-function tiles are positioned between CLB tiles of the FPGA array. Each multi-function tile includes multiple function elements that share routing resources. In one embodiment, a multi-function tile includes a configurable, dual-ported RAM and a multiplier that share routing resources of the multi-function tile. The RAM includes first and second input ports coupled to first and second input data buses, respectively, and includes first and second output ports coupled to first and second output data buses, respectively. The multiplier includes first and second operand ports coupled to receive operands from the first and second input data buses, and in response thereto provides a product. In one embodiment, the most significant bits (MSBs) of the product are selectively provided to the first output data bus using bus multiplexer logic, and the least significant bits (LSBs) of the product are selectively provided to the second output data bus using bus multiplexer logic.

Delay insensitive system-on-chip interconnect using 1-of-4 data encoding

Abstract: The demands of System-on-Chip (SoC) interconnect increasingly cannot be satisfied through the use of a shared bus. A common alternative, using unidirectional, point-to-point connections and multiplexers, results in much greater area requirements and still suffers from some of the same problems. This paper introduces a delay-insensitive, asynchronous approach to interconnect over long paths using 1-of-4 encoded channels switched through multiplexers. A reimplementation of the MARBLE SoC bus (as used in the AMULET3H chip) using this technique shows that it can provide a higher throughput than the simpler tristate bus while using a narrower datapath.

Optical routing element for use in fiber optic systems

Abstract: An optical routing element (ORE) that can be incorporated into a variety of configurations to provide the basis for such devices as crossbar switches, wavelength division multiplexers, and add/drop multiplexers. The ORE (20) includes first, second, and third waveguide segments (15a,15b,15c). The first and second waveguide segments (15a,15b) extend along a common axis and are separated by a routing region. The third waveguide segment (15c) extends from the routing region at a non-zero angle with respect to the common axis. The routing region is occupied by a selectively reflecting element (20) that selectively reflects light based on a state of the element or a property of the light. The selectively reflecting element may be a thermal expansion element (TEE), a wavelength-selective filter, or a mechanically actuated element (MAE).

Timing-insensitive glitch-free logic system and method

Abstract: A timing insensitive glitch-free (TIGF) logic device which can take the form of any latch or edge triggered flip-flop In one embodiment, a trigger signal is provided to update the TIGF logic device The trigger signal is provided during a short trigger period that occurs at adjacent times from the evaluation period (figure 59) In latch form, the TIGF latch includes a flip-flop that holds the current state of the TIGF latch until a trigger signal is received (figure 59) A multiplexer is also provided to receive the new input value and the old stored value The enable signal functions as the selector signal for the multiplexer In flip-flop form, the TIGF flip-flop includes a first flip-flop that holds the new input value, a second flip-flop that holds the current stored value, and a clock edge detector Hold time violations are avoided because one dedicated flip-flop stores the new input value which effectively blocks input changes during evaluation

Single superconducting quantum interference device multiplexer for arrays of low-temperature sensors

Abstract: We present the design and experimental evaluation of a superconducting quantum interference device (SQUID) multiplexer for an array of low-temperature sensors. Each sensor is inductively coupled to a superconducting summing loop which, in turn, is inductively coupled to the readout SQUID. The flux-locked loop of the SQUID is used to null the current in the summing loop and thus cancel crosstalk. The sensors are biased with an alternating current, each with a separate frequency, and the individual sensor signals are separated by lock-in detection at the SQUID output. We have fabricated a prototype 8 channel multiplexer and discuss the application to a larger array.

Piezoelectric identification device and applications thereof

Abstract: An identification device having a piezoelectric sensor array is used to obtain biometric data. In one embodiment, a piezo ceramic sensory array is used to obtain biometric data. In another embodiment, a multi-layer sensor array structure having a PVDF layer in between two conductor grids orthogonal to one another is used to obtain biometric data. Urethane can be added to one side of the sensor array where a finger is placed. A foam substrate can be used as a support. Multiplexers are switched to control the sensor. The device has several operating modes for obtaining a variety of biometric data, including an impedance detection mode, a voltage detection mode, an imaging mode, and a Doppler-shift detection mode. The presence of a fingerprint on the sensor can be used to turn-on the device. The device is capable of capturing a fingerprint, forming a three-dimensional map of a finger bone, and/or determining the direction and speed of arteriole and/or capillary blood flow in a finger. A single pixel or a group of pixels can be detected and readout to a memory. The device can be used as an electronic signature device. The device can operate as part of a personal area network, using a public service layer according to the invention.

Configuration bus interface circuit for FPGAs

Abstract: A bus interface circuit for a programmable logic device (PLD) including an interface multiplexer connected between two or more external communication circuits and a configuration memory array. The interface multiplexer coordinates communication between a selected one of the external communication circuits and a packet processor. The packet processor interprets command/data information transmitted in a bit stream from the selected external communication circuit. In a default state, the interface multiplexer connects dual-purpose input/output pins of the PLD to the packet processor. In an alternative state, the interface multiplexer connects a JTAG interface circuit to the packet processor to facilitate configuration operations through the JTAG pins of the PLD.

Multiplexer, multimedia communication apparatus and time stamp generation method

Abstract: In order to allow the generation of a time stamp in consideration of a frame skip even in the case where the frame skip is generated, a PES generation section of a multiplexer detects the number of skipped frames by analyzing elementary video streams output from a video encoder to determine a PTS on the basis of the time difference between frames calculated on the basis of the number of skipped frames. Then, a frame to which a PTS is to be placed with the above stream analysis is cut out to insert the PTS into a PES header of this frame to be transmitted to the transmission channel.

Signal transmission systems

Abstract: Signal transmission systems for second and third generation mobile communications networks are described. A signal distribution system comprises a plurality of rf transmitters for serving a plurality of network cells. The system is characterised by a multiplexer coupled to the transmitters for multiplexing the transmitter outputs, a signal transporter for transporting the multiplexed signals to each of the network cells, and a multiplexed signal receiver at each cell for selecting and receiving a signal from a transmitter serving the cell. The invention also provides a complementary signal reception system, and corresponding methods. Preferably, the multiplexed signals are transported over a fibre optic network such as an existing cable TV network. The system simplifies the deployment of network infrastructure for third generation mobile communications systems.

Vertically coupled microring resonators using polymer wafer bonding

Abstract: A new technique is presented to make vertically coupled semiconductor microring resonators that eases the fabrication process with devices more robust to ring-to-waveguide misalignments. Single-mode microring optical channel dropping filters are demonstrated for the first time in this configuration with Qs greater than 3000 and an on-resonance channel extinction greater than 12 dB. A 1/spl times/4 multiplexer/demultiplexer crossbar array with second-order microrings was also made and exhibited channel-to-channel crosstalk lower than 10 dB.

Athermal all-polymer arrayed-waveguide grating multiplexer

Abstract: An athermal arrayed-waveguide grating (AWG) multiplexer relying on an all-polymer approach is reported. The all-polymer AWG consisting of polymer waveguides fabricated on a polymer substrate exhibits excellent performance. By properly adjusting the coefficient of thermal expansion of the polymer substrate, athermal and polarisation-independent AWG devices featuring a wavelength shift of less than /spl plusmn/0.05 nm in the 25-65/spl deg/C temperature range could be demonstrated.

Digital phase lock loop

Abstract: A system includes a digital phase lock loop (PLL) constructed from an all digital circuit implementation and standard cell construction. The digital PLL includes a digital frequency synthesizer and a digital phase detector. The digital frequency synthesizer includes a digital DLL including a plurality of delay chains, each of the delay chains including at least one digitally programmable delay element for configuring the plurality of delay chains to achieve a phase lock with an input reference signal. The digital frequency synthesizer also a non-glitching MUX electrically coupled to the digital DLL for selecting a tap output from one of the at least one digitally programmable delay element to select at least one pulse glitch-free from the selected output tap, and a phase accumulator electrically coupled to the non-glitching MUX for precisely dividing a timing period of the input reference signal and for selecting a tap output from one of the at least one digitally programmable delay element to select at least one pulse at a precise point in the timing period from the output tap. The digital phase detector, is electrically coupled to the digital frequency synthesizer to compare an edge of the input reference signal to an edge of a synthesized signal to provide a digital code information representing a phase error between the edge of the input reference signal and the edge of the synthesized signal.

System and method for voice and data over digital wireless cellular system

Abstract: A method of combining voice and data for transmission in a single digital wireless telephone call comprises the steps of establishing a circuit-switched data call connection from a mobile phone to a destination, routing the call through a pair of modems connected in-line with the call connection path, multiplexing non-voice digital data with vocoded voice digital data to form a multiplexed digital data stream, and sending the multiplexed digital data stream from the mobile phone to the destination through the pair of modems. A telephone for combining voice and data into a digitized data stream for delivery to a destination using a single digital wireless telephone call comprises a vocoder, a microphone, a speaker, a multiplexer having an encoded voice input and a data input, and a demultiplexer having a converted data input and a voice data output. The multiplexer is operatively connected to receive encoded voice output from the vocoder and the data. The demultiplexer is operatively connected to provide received voice data from a decoder in the vocoder and non-voice data. A system for managing a combined data stream comprises a telephone and a destination, wherein the telephone is for combining voice and data into the combined data stream which is transmitted from the telephone to the destination.

Miniature monolithic optical add-drop multiplexer

Abstract: A miniature monolithic optical add-drop multiplexer that comprises a dispersive optical element, a wavelength filter array and a diverter. The miniature monolithic optical DWDM add-drop multiplexer can be fabricated using micro- and nano-scale techniques common to the semiconductor industry. The operating principles and some characteristics of the DWDM add-drop multiplexer are described. The device will be useful in the field of optical communication as a component within networks that perform all of the necessary switching, adding, dropping, and manipulating of optical signals entirely in the optical domain.

Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources

Abstract: A Variable Grain Architecture (VGA) is used for synthesizing from primitive building elements (CBE's) an appropriate amount of dynamic multiplexing capability for each given task. Unused ones of such Configurable Building Elements (CBE's) are reconfigured to carry out further logic functions in place of the dynamic multiplexing functions. Each CBE may be programmably configured to provide no more than a 2-to-1 dynamic multiplexer (2:1 DyMUX). The dynamically-selectable output of such a synthesized 2:1 DyMUX may then be output onto a shared interconnect line. Pairs of CBE's may be synthetically combined to efficiently define 4:1 DyMUX's with each such 4:1 multiplexer occupying a Configurable Building Block (CBB) structure. Pairs of CBB's may be synthetically combined to efficiently define 8:1 DyMUX's with each such synthesized 8:1 multiplexer occupying a vertically or horizontally-extending leg portion of an L-shaped, VGB structure (Variable Grain Block). The so-configured leg portion of the VGB may then output the signal selected by its 8:1 DyMUX onto a shared interconnect line that is drivable by the VGB leg. Pairs or quartets of VGB's may be synthetically combined to efficiently define higher order, N:1 DyMUX's.

System and method for integrating a fiber optic fixed access network and a fiber optic radio access network

Abstract: A system and method are described for integrating a fiber optic fixed access network and a fiber optic radio access network. At least one radio unit transmits and receives communications with at least one mobile unit. A first multiplexer transmits and receives the communications with the at least one radio unit and fixed access communications with at least one fixed access subscriber. The first multiplexer is connected to each of the at least one radio unit and to each of the at least one fixed access subscriber using fiber optic connections. Each of the at least one radio unit transmits and receives the communications with the first multiplexer using a wavelength that is different for each of the at least one radio unit and different from that used to transmit and receive the fixed access communications from the at least one fixed access subscriber. The communications and the fixed access communications are transmitted and received together between the first multiplexer and a second multiplexer through the fiber optic fixed access network using the different wavelengths.

Optical configuration for a dynamic gain equalizer and a configurable add/drop multiplexer

Abstract: An optical device for rerouting and modifying an optical signal that is capable of operating as a dynamic gain equalizer (DGE) and/or a configurable optical add/drop multiplexer (COADM) is disclosed. The optical design includes a front-end unit for providing a collimated beam of light, an element having optical power for providing collimating/focusing effects, a diffraction element for providing spatial dispersion, and modifying means which in a preferred embodiment includes one of a MEMS array and a liquid crystal array for reflecting and modifying at least a portion of a beam of light. The modifying means functions as an attenuator when the optical device operates as a DGE and as a switching array when the optical device operates as a COADM. Advantageously, this invention provides a 4-f system wherein a preferred embodiment the element having optical power is a concave reflector for providing a single means for receiving light from the front-end unit, reflecting the received light to the dispersive element, receiving light from the dispersive element, and providing dispersed light to the modifying means. Conveniently and advantageously, this same concave reflector is utilized on a return path, obviating the requirement of matching elements. In one embodiment a single focussing/collimating lens is provided substantially at a focal plane of the element having optical power.

Methods and apparatus for implementing a cryptography engine

Abstract: Methods and apparatus are provided for implementing a cryptography engine for cryptography processing. A variety of techniques are described. A cryptography engine such as a DES engine can be decoupled from surrounding logic by using asynchronous buffers. Bit-sliced design can be implemented by moving expansion and permutation logic out of the timing critical data path. An XOR function can be decomposed into functions that can be implemented more efficiently. A two-level multiplexer can be used to preserve a clock cycle during cryptography processing. Key scheduling can be pipelined to allow efficient round key generation.

Wavelength division multiplexed device

Abstract: A wavelength division multiplexed device is based on a transmission grating spectrometer having at least two diffractive optical elements. The WDM device provides flexible use and may be widely applied in WDM systems. The device is useful for multiplexing and demultiplexing, channel monitoring, and for adding and dropping channels. The device provides programmability in use as an add/drop multiplexer.

System and method for time dithering a digitally-controlled oscillator tuning input

Abstract: A technique of time dithering a fully digitally-controlled oscillator (DCO) tuning input employs a shift register 1306 and a multiplexer 1308 responsive to a sigma-delta modulated delay control to minimize spurious tones generated by a DCO 200 . The shift register 1306 is clocked via a divided-down high-frequency reference provided by the DCO 200 output signal. The multiplexer 1308 is clocked via a frequency reference that is reclocked and synchronized to the DCO 200 output signal. The multiplexer 1308 output is thus time dithered in response to a delay control to minimize perturbations caused by switching.

Technique for increasing optical spectral efficiency in millimetre-wave WDM fibre-radio

Abstract: A novel technique for increasing the spectral efficiency of millimetre-wave fibre-radio systems by employing wavelength interleaving in conjunction with optical single sideband modulation, is proposed and demonstrated. The technique has been demonstrated experimentally by employing a wavelength interleaved optical add-drop multiplexer and transmission of a 155 Mbit/s BPSK signal at 36 GHz over 20 km of fibre.

High-speed decoder for a multi-pair gigabit transceiver

Abstract: A method and a system for providing an input signal from a multiple decision feedback equalizer to a decoder based on a tail value and a subset of coefficient values received from a decision-feedback equalizer. A set of pre-computed values based on the subset of coefficient values is generated. Each of the pre-computed values is combined with the tail value to generate a tentative sample. One of the tentative samples is selected as the input signal to the decoder. In one aspect of the system, tentative samples are saturated and then stored in a set of registers before being outputted to a multiplexer which selects one of the tentative samples as the input signal to the decoder. This operation of storing the tentative samples in the registers before providing the tentative samples to the multiplexer facilitates high-speed operation by breaking up a critical path of computations into substantially balanced first and second portions, the first portion including computations in the decision-feedback equalizer and the multiple decision feedback equalizer, the second portion including computations in the decoder.

Optical photonic band gap devices and methods of fabrication thereof

Abstract: An optical device includes a waveguide bounded by a region containing a photonic band gap the properties of which determined the transfer characteristic of the waveguide. Such a device may serve as a component of, for example a wavelength division multiplexer, a monochromatic laser or a chemical sensor. It may serve as an optical bus for an electronic component such as a microprocessor. These devices are particularly suitable for incorporation in optical and opto-electronic integrated circuits as they permit the fabrication of waveguides having right-angle bends with a radius of the order of 2 μm.

Gate lines driving circuit and driving method

Abstract: The present invention provides a driving circuit and the driving method for driving gate control lines G — 1 . . . G_N. The gate control lines G — 1 . . . G_N are evenly divided into L groups. The driving circuit comprises a gate line control logic circuit, a first level shifter module, a second level shifter module and a multipliexer. The first level shifter module is controlled by the gate line control logic circuit, and scans the driving lines D — 1 . . . D_K in each time slot to drive the driving lines one by one, wherein L*K=N. The second level shifter module is controlled by the gate line control logic circuit, and scans the L groups in each time frame to select the L groups one by one. The multiplexer is used to connect the driving lines D — 1 . . . D_K to the gate control lines of a selected group, and connect the gate control lines of unselected groups to a predetermined power line.

Design considerations in optical add/drop multiplexers based on grating-assisted null couplers

Abstract: The performance of a fully optimized optical add/drop multiplexer (OADM), based on null couplers and tilted Bragg gratings, is studied in detail. It is shown that maximization of the device performance involves three main optimization steps. First, the waveguide asymmetry (V/sub 2//V/sub 1/ ratio) should be optimized in order to minimize the extinction ratio of the unwanted mode at the null coupler waist. Second, the coupler taper shape should he optimized in order to further minimize the aforementioned extinction ratio. Third, the grating tilt angle and relative width can be also optimized to give negligible backreflections at the input port and minimize radiation losses. The results show that the proposed high-performance OADM configuration can meet stringent telecom specifications.