Showing papers on "Multiplier (economics) published in 2008"

Design of a Novel Reversible Multiplier Circuit Using HNG Gate in Nanotechnology

Abstract: Reversible logic circuits are of interests to power minimization having applications in low power CMOS design, optical information processing, DNA computing, bioinformatics, quantum computing and nanotechnology. In this paper we propose a novel 4x4 bit reversible multiplier circuit. The proposed reversible multiplier is faster and has lower hardware complexity compared to the existing counterparts. It is also better than the existing counterparts in term of number of gates, garbage outputs and constant inputs. Haghparast and Navi recently proposed a 4x4 reversible gate called "HNG". The reversible HNG gate can work singly as a reversible full adder. In this paper we use HNG gates to construct the reversible multiplier circuit. The proposed reversible multiplier circuit using HNG gate can multiply two 4-bits binary numbers. The proposed reversible 4x4 multiplier circuit can be generalized for NxN bit multiplication. We can use it to construct more complex systems in nanotechnology.

Novel Reversible Multiplier Circuit in Nanotechnology

Abstract: Reversible computation is of the growing interests to power minimization having applications in low power CMOS design, quantum computing, optical information processing, DNA computing, bioinformatics and nanotechnology. This paper proposes a novel 4x4 bit reversible Multiplier circuit. It is faster and has lower hardware complexity compared to the existing designs. In addition, the proposed reversible multiplier is better than the existing counterparts in term of number of gates and number of garbage outputs. Haghparast and Navi recently proposed a 4x4 reversible gate called "MKG". The reversible MKG gate can work singly as a reversible full adder. In this paper we use MKG gates to construct the reversible multiplier circuit. The proposed reversible multiplier circuit can multiply two 4-bits binary numbers. It can be generalized for NxN bit multiplication.

Bidirectional Current-Mode Capacitor Multipliers for On-Chip Compensation

Abstract: Single-ended and two-ended bidirectional capacitor multipliers for providing on-chip compensation, soft-start, and fast transient mechanisms are proposed in this paper. The bidirectional current mode capacitor multiplier technique can effectively move the crossover frequency toward to the origin in the start-up period for a smoothly rising of the output voltage. Besides, the small time constant is set by the fast transient control circuit in order to get a higher crossover frequency. Thus, the output voltage can be regulated to its stable value as fast as it can when large load current changes. A test chip fabricated by the Taiwan Semiconductor Manufacturing Corporation (TSMC) 0.35-m process verifies the correctness of the bidirectional current mode capacitor multiplier technique. Experimental results demonstrate the transient speed by our proposed technique is faster than that by conventional control by about 2 times, and there is only about 76% dropout voltage of the conventional design with off-chip compensation. The proposed circuits consume more quiescent current about 10 in single-ended capacitor multiplier and 20 in two-ended capacitor multiplier. With the proposed bidirectional current mode capacitor multiplier technique, the performance of dc-dc converters is improved significantly and the external pins and footprint area are minimized.

Microchip Laser Feedback Interferometer with an Optical Path Multiplier

Abstract: We present a microchip laser feedback interferometer with an optical path multiplier to enhance the resolution of traditional laser feedback interferometers (LFI). The optical path multiplier has a unique device, i.e. diffusive reflector. As class B microchip lasers have extremely high sensitivity to laser feedback, the diffusive reflector can easily reflect or diffuse back the laser beam without much manual adjustment to the optical system, which ensures the system's easy-adjustment and practical feature. The optical path multiplier is a two-mirror system which enables the laser beam to reflect between the two mirrors by N times. When the target shifts a distance of Δd, the variation of the optical path will be about (AN × Δd). Thus the system's resolution is about 4N times as high as the traditional LFI. Under typical room conditions, the optical path multiplier can effectively enhance the system's resolution by more than 26 times as high as a traditional LFI system and even to the level of 0.1 nm.

Bipartite Modular Multiplication Method

Abstract: This paper proposes a new modular multiplication method that uses Montgomery residues defined by a modulus M and a Montgomery radix R whose value is less than the modulus M. This condition enables the operand multiplier to be split into two parts that can be processed separately in parallel - increasing the calculation speed. The upper part of the split multiplier can be processed by calculating a product modulo M of the multiplicand and this part of the split multiplier. The lower part of the split multiplier can be processed by calculating a product modulo M of the multiplicand, this part of the split multiplier, and the inverse of a constant R. Two different implementations based on this method are proposed: One uses a classical modular multiplier and a Montgomery multiplier and the other generates partial products for each part of the split multiplier separately, which are added and accumulated in a single pipelined unit. A radix-4 version of a multiplier based on a radix-4 classical modular multiplier and a radix-4 Montgomery multiplier has been designed and simulated. The proposed method is also suitable for software implementation in a multiprocessor environment.

Apparatus and method for reducing peak to average power ratio in an orthogonal frequency division multiplexing system

Abstract: A transmitter apparatus and method for reducing PAPR in an OFDM system. The transmitter apparatus performs a masking process on an input signal block using a plurality of mask sequences in an OFDM system, and selects a specific sequence having a lowest PAPR among IFFT-processed results. The apparatus includes a single IFFT for performing an IFFT process on the received signal block, and generating an IFFT-processed sequence; a plurality of shift registers for storing individual bits of the IFFT-processed sequence, cyclically shifting them, and generating the cyclically-shifted bits; a plurality of multiplier groups for multiplying coefficients determined by corresponding mask sequences by the output bits of the shift registers; and a plurality of adders corresponding to the plurality of multiplier groups for adding the multiplied results of the multiplier groups, thereby reducing system complexity and production costs.

High-speed and low-power multipliers using the Baugh-Wooley algorithm and HPM reduction tree

Abstract: The modified-Booth algorithm is extensively used for high-speed multiplier circuits. Once, when array multipliers were used, the reduced number of generated partial products significantly improved multiplier performance. In designs based on reduction trees with logarithmic logic depth, however, the reduced number of partial products has a limited impact on overall performance. The Baugh-Wooley algorithm is a different scheme for signed multiplication, but is not so widely adopted because it may be complicated to deploy on irregular reduction trees. We use the Baugh-Wooley algorithm in our High Performance Multiplier (HPM) tree, which combines a regular layout with a logarithmic logic depth. We show for a range of operator bit-widths that, when implemented in 130-nm and 65-nm process technologies, the Baugh-Wooley multipliers exhibit comparable delay, less power dissipation and smaller area foot-print than modified-Booth multipliers.

An efficient Modified Booth multiplier architecture

Abstract: We present the design of an efficient multiplication unit. This multiplier architecture is based on radix 4 booth multiplier. In order to improve his architecture, we have made 2 enhancements. The first is to modify the Wen-Chang's modified booth encoder (MBE) since it is the fastest scheme to generate a partial product. However, when implementing this MBE with the simplified sign extension (SSE) method, the multiplication's output is incorrect. The 2nd part is to improve the delay in the 4:2 compressor circuit. The redesigned 4:2 compressor reduced the delay of the carry signal. This modification has been made by rearranging the Boolean equation of the carry signal. This architecture has been designed using Quartus II. The Gajski rule has been adopted in order to estimate the delay and size of the circuit. The total transistor count for this new multiplier is being a slightly bigger. This is due to the new MBE which is uses more transistor. However in performance speed, this efficiency multiplier is quite good. The propagation delay is reduced by about 2% - 7% from other designers.

Design of a Simple Current-Mode Multiplier Topology Using a Single CCCII+

Abstract: In this paper, an analog current-mode (CM) multiplier circuit employing a single plus-type second-generation current-controlled conveyor (CCCII+) and a grounded resistor is proposed. The developed circuit can provide two-quadrant multiplication, four-quadrant multiplication, and frequency doubling all from the same topology with the selection of the applied input currents. In addition to the signal limitations of the multiplier configuration, the nonideality effects of the CCCII+ and the nonideal gain and parasitic impedance effects on the proposed circuit are investigated. The realized circuit is simulated with SPICE to exhibit its performance. In addition, a CM multiplier derived from the proposed multiplier is set up with commercially available active components to easily perform its experimental test.

A variant of a radix-10 combinational multiplier

Abstract: We consider the problem of adding the partial products in the combinational decimal multiplier presented by Lang and Nannarelli. In the original paper this addition is done with a tree of decimal carry-save adders. In this paper, we treat the problem using the multi-operand decimal addition previously published by Dadda, where the sum of each column of the partial product array is obtained first in binary form and then converted to decimal. The multiplication, using a 90 nm CMOS technology, in this modified scheme takes 2.51 ns, while in the original scheme it takes 2.65 ns. The area of the two schemes is roughly the same.

A current-mode analog multiplier/divider based on CCCDTA

Abstract: A novel simple current-mode analog multiplier/divider, based on current-controlled current-differencing transconductance amplifier (CCCDTA), is presented. The proposed circuit employs only single CCCDTA without any external passive element requirement and it can work as multiplier and divider without changing its topology. In addition, the proposed circuit can work as gain-controllable current amplifier. The circuit performances are depicted through PSPICE simulations. The simulated results show that: for ±1.5 V power supply, the total harmonic distortion is about 0.1%, the −3 dB bandwidth is more than 26.94 MHz, maximum input range is about 100A and the output current is low sensitive to temperature variations. 2007 Elsevier GmbH. All rights reserved.

Cost-Effective Triple-Mode Reconfigurable Pipeline FFT/IFFT/2-D DCT Processor

Abstract: This investigation proposes a novel radix-42 algorithm with the low computational complexity of a radix-16 algorithm but the lower hardware requirement of a radix-4 algorithm. The proposed pipeline radix-42 single delay feedback path (R42SDF) architecture adopts a multiplierless radix-4 butterfly structure, based on the specific linear mapping of common factor algorithm (CFA), to support both 256-point fast Fourier transform/inverse fast Fourier transform (FFT/IFFT) and 8times8 2D discrete cosine transform (DCT) modes following with the high efficient feedback shift registers architecture. The segment shift register (SSR) and overturn shift register (OSR) structure are adopted to minimize the register cost for the input re-ordering and post computation operations in the 8times8 2D DCT mode, respectively. Moreover, the retrenched constant multiplier and eight-folded complex multiplier structures are adopted to decrease the multiplier cost and the coefficient ROM size with the complex conjugate symmetry rule and subexpression elimination technology. To further decrease the chip cost, a finite wordlength analysis is provided to indicate that the proposed architecture only requires a 13-bit internal wordlength to achieve 40-dB signal-to-noise ratio (SNR) performance in 256-point FFT/IFFT modes and high digital video (DV) compression quality in 8 times 8 2D DCT mode. The comprehensive comparison results indicate that the proposed cost effective reconfigurable design has the smallest hardware requirement and largest hardware utilization among the tested architectures for the FFT/IFFT computation, and thus has the highest cost efficiency. The derivation and chip implementation results show that the proposed pipeline 256-point FFT/IFFT/2D DCT triple-mode chip consumes 22.37 mW at 100 MHz at 1.2-V supply voltage in TSMC 0.13-mum CMOS process, which is very appropriate for the RSoCs IP of next-generation handheld devices.

Performance Analysis of a 32-Bit Multiplier with a Carry-Look-Ahead Adder and a 32-bit Multiplier with a Ripple Adder using VHDL

Abstract: This study presents a performance analysis of two different multipliers for unsigned data, one uses a carry-look-ahead adder and the second one uses a ripple adder. The study's main focus is on the speed of the multiplication operation on these 32-bit multipliers which are modeled using VHDL, A hardware description language. The multiplier with a carry-look-ahead adder has shown a better performance over the multiplier with a ripple adder in terms of gate delays. Under the worst case, the multiplier with the fast adder shows approximately twice the speed of the multiplier with the ripple adder. The multiplier with a ripple adder uses time = 979.056 ns, while the multiplier with the carry-look-ahead adder uses time = 659.292 ns.

A new high compression compressor for large multiplier

Abstract: A new high compression compressor is proposed in this paper. This compressor has 7 inputs, 2 output, 2 carry-ins from adjacent two cells and 2 carry-outs to the next two cells. It achieves higher compression ratio than 4:2 compressor, 5:2 compressor and 6:2 compressor. Simulation shows that a 64x64 bit multiplier using this proposed 7:2 compressor is not only 16% faster than multiplier built with 3:2 compressors, but also outperforms multiplier built with other commonly used compressors.

A well-structured modified Booth multiplier design

Abstract: This paper proposes a well-structured modified Booth encoding (MBE) multiplier architecture. The design adopts an improved Booth encoder and selector to achieve an extra-row- removal and a hybrid spare-tree approach to design two's complementation circuit to both reduce the area and improve the speed. Experimental results on a 32 bit multiplier show that it obtains area and power savings of 15.8% and 11.7% respectively over the classical design and of 7.5% and 5.5% respectively over the design of the best performance reported so far.

Power Attack Resistant Efficient FPGA Architecture for Karatsuba Multiplier

Abstract: The paper presents an architecture to implement Karatsuba Multiplier on an FPGA platform. Detailed analysis has been carried out on how existing algorithms utilize FPGA resources. Based on the observations the work develops a hybrid technique which has a better area delay product compared to the known algorithms. The results have been practically demonstrated through a large number of experiments. Subsequently, the work develops a masking strategy to prevent power based side channel attacks on the multiplier. It has been found that the proposed masked Hybrid Karatsuba multiplier is more compact compared to existing designs.

A transition probability based delay measurement method for arbitrary circuits on FPGAs

Abstract: This paper proposes a novel test method for measuring the worst case path delay of any circuit on an FPGA, combinatorial or sequential, where little prior knowledge of the circuitpsilas internal structure is required. The method is based on detecting changes in the transition probability profile on the circuitpsilas output nodes while a range of test clock frequencies is stepped through. The method is applied to three classes of circuits, all implemented on an Altera Cyclone III FPGA: an adder carry chain, an embedded multiplier and a linear-feedback shift-register. The measured delays are compared to that found by a previously published, but much more time consuming, method and their results match to within 12%.

Low error truncated multipliers for DSP applications

Abstract: The paper presents a new technique to design signed and unsigned truncated multipliers. Simple formulae are developed in the paper to describe the truncated multiplier with minimum mean square error for every inputspsila bit-width. With respect to previously proposed techniques, our analytical approach is more general and improves the accuracy of the multiplier. We have also compared the accuracy achievable with the proposed truncated multiplier with respect to the accuracy of a standard full-width multiplier in a typical DSP application. The results show that the proposed multiplier causes only a negligible loss in accuracy. On the other hand, the area and the power dissipation of the DSP datapath are both improved by 16%.

Energy-Efficient, High Performance Circuits for Arithmetic Units

Abstract: Adders and multipliers are the most important arithmetic units in a general microprocessor and the major source of power dissipation. Various architecture styles exist to implement these units, each having their own merits and demerits. However, due to continuing integrating intensity and growing needs of portable devices, low power design is of prime importance. In addition, much power is dissipated due to a large number of spurious transitions on internal nodes in power hungry multiplier structures. We present a new full adder structure based on complementary pass transistor logic (CPL) which is faster and more energy efficient than the existing structures. We also propose a new technique of implementing multiplier circuit using decomposition logic which improves speed and reduces power consumption by reducing the spurious transitions on internal nodes. Combined with the new adder structure and the decomposition logic, there is substantial improvement in the performance of the multiplier structures. With the help of these state of the art designs, it would be possible to design highly power efficient processors, especially digital signal processors. We have used TSPICE for simulation in the TSMC 180 nm technology.

A 1.5V, wide-input range, high-bandwidth, CMOS four-quadrant analog multiplier

Abstract: A low-voltage low-power CMOS four quadrant analog multiplier based directly on a cross-coupled squarer topology and suitable for the deep submicron technology is presented. Simulation results using 0.35-mum process parameters show that, when operated under a 1.5 V single supply, the proposed multiplier consumes 290 muW of quiescent power, its linear range with respect to both differential input voltages is plusmn0.4 V and its bandwidth is about 100 MHz.

Integrated optic vector-matrix multiplier

Abstract: A vector-matrix multiplier is disclosed which uses N different wavelengths of light that are modulated with amplitudes representing elements of an N×1 vector and combined to form an input wavelength-division multiplexed (WDM) light stream. The input WDM light stream is split into N streamlets from which each wavelength of the light is individually coupled out and modulated for a second time using an input signal representing elements of an M×N matrix, and is then coupled into an output waveguide for each streamlet to form an output WDM light stream which is detected to generate a product of the vector and matrix. The vector-matrix multiplier can be formed as an integrated optical circuit using either waveguide amplitude modulators or ring resonator amplitude modulators.

A power-aware 2-dimensional bypassing multiplier using cell-based design flow

Abstract: This paper presents a low power digital multiplier design by taking advantage of a 2-dimensional bypassing method in cell-based design flow. The proposed bypassing cells constituting the multiplier skip redundant signal transitions when the horizontally partial product or the vertically operand is zero. Thorough cell-based design flow post-layout simulations show that the power delay product of the proposed 8times8 multiplier design is reduced by more than 13.8% compared to prior designs.

R/D converter and angle detecting apparatus

Abstract: An RD converter has: a multiplier multiplying a resolver signal S1 by an output of a SIN ROM; a multiplier multiplying a resolver signal S2 by an output of a COS ROM; a subtractor subtracting an output of the multiplier from an output of the multiplier; a synchronous detecting circuit detecting synchronously an output of the subtractor with reference to an excitation signal; a controller controlling an output angle .theta.' to make an output of the synchronous detecting circuit equal to 0; a correction data part outputting a correction angle .theta.c for the output angle .theta.'; an adder adding the output angle .theta.' and the correction angle .theta.c; the SIN ROM producing a sine value of a result from the adder; and the COS ROM producing a cosine value of the result.

Multiplier, Mixer, Modulator, Receiver and Transmitter

Abstract: A multiplier is provided, for example, for use as a mixer in a modulator of a radio frequency transmitter. The multiplier multiplies a first alternating signal of constant amplitude by a second signal, for example, in the form of a carrier wave from a local oscillator. The multiplier comprises a transconductance stage for converting the first signal to a differential output current and a current switching stage for switching the differential output current in accordance with the second signal. The transconductance stage comprises a plurality of offset pairs of transistors, whose inputs and outputs are connected in parallel. The switching stage comprises cross-coupled pairs of transistors which, together with the transconductance stage, form a Gilbert cell. The relative gains of the transistors of each offset pair are such that a minimum in the third harmonic distortion characteristic of the multiplier occurs substantially at the amplitude of the first signal.

The Case for HPM-Based Baugh-Wooley Multipliers

Abstract: The modified-Booth algorithm is extensively used for high-speed multiplier circuits. Once, when array multipliers were used, the reduced number of generated partial products significantly improved multiplier performance. In designs based on reduction trees with logarithmic logic depth, however, the reduced number of partial products has a limited impact on overall performance. The Baugh-Wooley algorithm is a different scheme for signed multiplication, but is not so widely adopted because it may be complicated to deploy on irregular reduction trees. We use the Baugh-Wooley algorithm in our High Performance Multiplier (HPM) tree, which combines a regular layout with a logarithmic logic depth. We show for a range of operator bit-widths that, when implemented in 130-nm and 65-nm process technologies, the Baugh-Wooley multipliers exhibit comparable delay, less power dissipation and smaller area foot-print than modified-Booth multipliers.