Showing papers on "p–n junction published in 1989"

Electroluminescence from sulfur impurities in a p‐n junction formed in epitaxial silicon

Abstract: We characterize the behavior of electroluminescence from a sulfur‐related impurity complex in a p‐n junction formed in epitaxial silicon. The spectrum of the electroluminescence matches that of previously reported photoluminescence from sulfur impurities and persists to ∼150 K. In our structure, we find that the electroluminescence exhibits an external quantum efficiency of 0.2–0.5%.

Electroluminescence in an Oxygen-Doped ZnSe p-n Junction Grown by Molecular Beam Epitaxy

Abstract: Blue electroluminescence has been obtained from ZnSe p-n junctions. ZnSe films were grown on n-type GaAs(100) substrates by molecular beam epitaxy. The dopants used for n-and p-type ZnSe were Ga and O, respectively. The electron-beam-induced current strongly suggests the formation of a p-n junction. The built-in Potential of the p-n junction and carrier concentration of p-type ZnSe layer estimated from the capacitance-voltage relation were about 2.3 V and 1.2×1016cm-3, respectively. The electroluminescence spectra from the p-n junction were dominated by band-edge emissions of 466 nm at room temperature and 446 nm at 77 K.

Study of novel chemical surface passivation techniques on GaAs pn junction solar cells

Abstract: Novel methods of GaAs surface passivation are investigated. Passivation is acheived by simple chemical treatments using aqueous solutions of Na2S, KOH, RuCl3, and K2Se. GaAs pn homojunction solar cells are used to evaluate the effectiveness of these passivation techniques. A significant reduction in minority‐carrier surface recombination velocity is demonstrated. In the best case, the surface recombination velocity decreased from 5×106 cm/s (untreated surface) to 103 cm/s. In addition, we observe improvements in solar cell photogenerated current, short wavelength spectral response, open‐circuit voltage, and junction ‘‘dark’’ current.

Breakdown in p‐n junction diodes made on polycrystalline silicon of large grain size

Abstract: This communication describes the voltage‐current characteristics in the breakdown region of p‐n junctions made on polycrystalline silicon of large grain size. The observed soft breakdown characteristics have been explained by taking into account the effect of curvature of the junction near the grain boundaries.

High‐power fundamental mode AlGaAs quantum well channeled substrate laser grown by molecular beam epitaxy

Abstract: We demonstrate a high‐power AlGaAs single quantum well graded‐index separate confinement heterojunction laser grown by molecular epitaxy over channeled substrates. Fundamental mode operation up to 130 mW for reflection modified devices has been achieved at a high differential quantum front‐facet efficiency of 81%. This device structure allows extremely low threshold currents to 6 mA for power lasers due to the incorporation of lateral current blocking pn junction by crystallographic plane‐dependent doping of amphoteric dopants. We obtained a very high‐power continuous‐wave fundamental mode operation of this type of laser at extremely low threshold currents and very high overall efficiency of more than 50%. This laser shows considerable potential for applications in optical storage and printer technology.

Deep-level impurity analysis for p- n junctions of a bipolar transistor from low-frequency g- r noise measurements

Abstract: Deep-level impurity analysis for p-n junctions of bipolar transistors from g-r noise is less developed than for homogeneous materials In the present study we attempt to elucidate: 1 1 The features of g-r noise associated with a p-n junction 2 2 A new method to separate g-r noise, and experimental results 3 3 Deep-level impurity analysis for p-n junctions of bipolar transistors By doing low-frequency noise measurements and g-r noise separation at room temperature, evidence for five g-r noise components in a p-n junction of a bipolar transistor was discovered The region of the corner frequencies is 05 Hz–100 kHz, and five distinct deep-levels of impurities in the p-n junction are suggested

Electroluminescence from a ZnSe p-n Junction Fabricated by Nitrogen-Ion Implantation

Abstract: Electroluminescence has been obtained from ZnSe p-n junctions. ZnSe films were grown on n-type GaAs substrates by molecular beam epitaxy. The dopant used for n-type ZnSe was Ga, and p-type ZnSe was formed by nitrogen ion implantation into undoped ZnSe which was grown on the Ga-doped ZnSe layer. Rapid thermal annealing was performed using an infrared lamp in N2 ambient. The formation of a p-n junction was confirmed by measuring electron beam-induced current. The electroluminescence spectra were dominated by two peaks of band-edge emission at 446 and 459 nm at 77 K.

Electrically active defects in shallow pre-amorphisedp+n junctions in silicon

Abstract: An examination of shallow pre-amorphisedp + n junctions in silicon has revealed three distinct defect related phenomena determined largely by the annealing temperature and relative location of the junction and the amorphous-crystalline (α-c) boundary. For temperatures below 800‡ C all samples displayed leakage currents of ∼10−3 A/cm2 irrespective of the amorphising atom (Si+, Ge+ or Sn+). The generation centres responsible were identified to be near mid-gap deep level donors lying beyond the α-c interface. For samples annealed above 800‡ C, the leakage current was determined by the interstitial dislocation loops at the α-c boundary. If these were deeper than the junction, a leakage current density of ∼10−5 A/cm2 resulted. From the growth of these loops during furnace annealing it was concluded that the growth was supported by the influx of recoil implanted silicon interstitials initially positioned beyond the α-c boundary. In the case where the as-implanted junction was deeper than the α-c boundary, annealing above 800° C resulted in a transient enhancement in the boron diffusion coefficient. As with the dislocation loop growth, this was attributed to the presence of the recoil implanted silicon interstitials.

Silicon carbide light emitting diode having a pn junction

Abstract: A silicon carbide light emitting diode having a pn junction is disclosed which comprises a semiconductor substrate, a first silicon carbide single-crystal layer of one conductivity formed on the substrate, and a second silicon carbide single-crystal layer of the opposite conductivity formed on the first silicon carbide layer, the first and second silicon carbide layers constituting the pn junction, wherein at least one of the first and second silicon carbide layers contains a tetravalent transition element as a luminescent center.

Semiconductor light emitting element and manufacture thereof

Abstract: PURPOSE:To obtain a high intensity blue light emission by alternately laminating a BP layer and a GaAl1-XN (O<=x<=1) layer, and employing a superlattice layer having a sphalerite (ZP) type crystalline structure in the GaAl1-XN layer. CONSTITUTION:A n-type GaP layer 12, a n-type BP layer 13 are formed as buffer layers on a n-type Gap substrate 11, a n-type Ga0.5Al0.5N/BP superlattice layer 14 and a p-type Ga0.5Al0.5N/BP superlattice layer 15 are sequentially formed thereon to form a pn junction, and ohmic electrodes 16, 17 are formed on both side faces of an element. That is, the GaAl1-XN layer is alternately laminated with the BP layer to be easily pn-controlled with small ion properties in a ZB structure with substantially the same coupling length to form a superlattice layer to provide a compound semiconductor material of the ZB structure having both nitride direct transition type wide band gap characteristic and BP low ion properties with scarce defect occurring properties. A pn junction is composed of it. Thus, a high intensity blue light emission is obtained.

Process for manufacturing a thyristor with proton irradiation

Abstract: A process for making a thyristor device protected against breakover firing is to generate in the semiconductor body (1) of the thyristor an area (A) which has a lower breakdown voltage than the rest of the semiconductor body. This area is protected by suitable measures when the thyristor is overloaded. The invention features a process in which the area (A) of the semiconductor body (1) is irradiated locally with protons, with the proton energy being measured in such a manner that the maximum of the defect density and doping generated by the proton irradiation lies between the PN junction (15) of the first base region (9) and the second base region (10) and the half thickness of the second base region (10), and the semiconductor body (1) is subsequently heat-treated.

Semiconductor memory device and manufacture thereof

Abstract: PURPOSE: To lessen a semiconductor memory device in required area and to improve it in resistance to soft error by a method wherein the PN junction of the memory node of a flip-flop FF circuit is micronized in area in a self- aligned manner, a laminated capacitive element is added to the memory node, and the FF circuit is composed of a complementary inverter of laminated structure CONSTITUTION: The area of the PN junction of a FF circuit is made smaller than those of channel sections 18c and 18d of insulated gate field effect transistors T 1 -T 4 , and a gate electrode 11b of the transistor T 1 out of a pair of the insulated gate field effect transistors T 1 and T 2 and a drain region 18b of the other transistor T 2 and a drain region 18a of the transistor T 1 and a gate electrode 11c of the transistor T 2 are electrically cross-connected through a first and a second conductive film, 16a and 16b By this setup, a semiconductor memory device of this design can be lessened in required area, improved in resistance to soft error, and stabilized in operation of a memory cell COPYRIGHT: (C)1990,JPO&Japio

Shallow, silicided p+/n junction formation and dopant diffusion in SiO2/TiSi2/Si structure

Abstract: Shallow silicided p+/n junctions have been formed by implanting boron ions into titanium disilicide layers and the subsequent drive‐in of the implanted boron into the Si substrate by rapid thermal annealing (RTA). Results of boron diffusion in titanium disilicide layer, its segregation at both silicide/Si and oxide/silicide interfaces, and the junction quality are presented. The precipitation of boron at the SiO2/TiSi2 interface is identified for the first time in the form of B2O3. p+/n diodes and short‐channel metal‐oxide‐semiconductor field‐effect transistors with good electrical characteristics have been fabricated using doped silicide technology.

Tunneling Structures Fabricated by Silicon Wafer Direct Bonding

Abstract: Tunneling diodes with highly doped and abrupt pn-junctions, and p+nn+ diodes were fabricated by bonding 4 inch silicon wafers at room temperature. After low temperature annealing (300–800°C) the electrical properties of the bonding interface could be changed by applying high currents up to 500 A/cm2. For tunneling diodes stressed with high current densities negative resistance effects have been obtained. The p+nn+ diodes with bonded n+ and p+ emitters showed S-shaped current switching observed in p-n-I-M structures. It is shown that due to the presence of an oxide at the bonding interface the current is limited in bonded pn-junctions.

Fabrication process for photodiodes responsive to blue light

Abstract: A method is provided for the fabrication of a photodiode sensitive to blue light. This photodiode has a very flat pn junction (2) in order to achieve a high blue sensitivity. The pn-junction (2) is formed in an n-conducting (100)-oriented silicon monocrystal (1) through implantation of B+ ions. Subsequently, an upper layer (3) generated during the implantation with relatively low p-doping is eroded through anisotropic etching to extend into a region of a deeper lying layer (4) having a relatively high p+ -doping. This high p+ -doping layer is then located to provide high sensitivity of the silicon photodiodes light corresponding to blue in the visual spectrum.

Method of making a passivated P-N junction in mesa semiconductor structure

Abstract: A process for forming a semiconductor device begins by diffusing an N layer having a relatively high concentration into a P wafer having a relatively low concentraton. Next, the wafer is etched to yield a plurality of mesa semiconductor structures, each having a P-N junction intersecting a sidewall of the mesa structure. Then, a layer of oxide is grown on the sidewalls of the mesas, which oxide layer passivates the device. The oxidizing step curves the P-N junction toward the P layer in the vicinity of the oxide layer. Then, the P-N junction is diffused deeper into the P layer with a diffusion front which tends to curve the P-N junction back toward the N layer in the vicinity of the oxide layer. This diffusion is carried out to such an extent as to compensate for the curvature caused by the oxidizing step and thereby substantially flatten the P-N junction. A plurality of successive oxidation/diffusion steps can be undertaken to further flatten the junction adjacent the mesa sidewall. The resultant P-N junction has a greater breakdown voltage in the vicinity of the oxide layer due to the substantial flatness of the P-N junction. The decreased concentration gradient of the linearly graded junction in the vicinity of the oxide layer caused by the oxidizing step increases the breakdown voltage in the vicinity of the oxide layer above the bulk breakdown voltage.

Sub‐100‐nm p+‐n shallow junctions fabricated by group III dual ion implantation and rapid thermal annealing

Abstract: The fabrication of p+‐n junctions with depth less than 100 nm using dual ion implantation of group III species (69Ga, 115In, 11B, 49BF2) in various combinations is reported. We have investigated both the single use of heavy group III (Ga and In) ions for creating shallow junctions and the dual implant approach where Ga or In was first used for preamorphization (and doping) followed by a B or BF2 implant. The optimum cases for sub‐100‐nm shallow junction formation among the group III combinations evaluated are Ga/B dual ion implantation followed by low‐temperature (550–600 °C) rapid thermal annealing (RTA) for 15–30 s and In/B(B or BF2) dual ion implantation with higher temperature (900–1000 °C) RTA for 10 s. Junction depths of 60–100 nm and sheet resistances of 150–300 Ω/⧠ were obtained. Shallow junction diodes fabricated by this dual ion implant technology exhibit low leakage current densities of 8–30 nA/cm2 and good ideality factors of 1.01–1.05.

P-n junction diode

Abstract: PURPOSE:To improve switching speed, by providing, at least one of an anode and a cathode with both a carrier injection region and a region whose potential for a carrier and an inverse conductivity type carrier is lower than the carrier injection region. CONSTITUTION:An anode region 7 being a high concentration P-type semiconductor layer, and an anode short region 8 being a high impurity N-type semiconductor layer are alternately formed on an anode electrode 6 of Al formed at anode short interval d1. Life time killer is not introduced, and by providing at least one of a cathode 2 and an anode 7 with a semiconductor region whose potential for carrier is low, the carrier stored at the time of turn-off is led out from the semiconductor region whose potential for carrier is low. Thereby enabling high speed switching without increasing ON-voltage and leak current.

A semiconductor photo-diode

Abstract: An APD according to the present invention comprises a substrate (1A) formed of n⁺-type AlxGa1-xSb or AlxGa1-x­SbyAs1-y semiconductor, whose aluminum content ratio x is typically 0.1 to 0.3; a light absorbing layer (2) formed of n-type GaSb semiconductor on the substrate; an avalanche multiplication layer (3,3˝) formed of n-type AlxGa1-xSb or AlxGa1-xSb­yAs1-y semiconductor, whose aluminum content ratio x is from 0.02 to 0.1, typically 0.065, so that an ionization rate ratio of positive and negative carriers is essentially maximized by a resonant ionization phenomena; and a p⁺-region (5) formed in a surface layer (4A) formed of n⁻-type AlxGa1-xSb or AlxGa1-xSb­yAs1-y semiconductor on the avalanche multiplication layer or directly in the avalanche multiplication layer so as to form a pn junction. Electrodes (6,7) are formed on the p-type region and the substrate so as to apply a bias voltage to the APD. Via an opening of the electrode (7) for the substrate, a light to be detected is injected through the substrate, while producing no carriers therein, into the light absorbing layer. The avalanche multiplication layer (3,3˝) generates the resonant impact ionization purely with only the positive carriers from the light absorbing layer (2), thus, low noise as well as fast operation of the APD is achieved. Furthermore, the APD structure of the invention facilitates the APD design.

The effects of X-rays on p-n junction leakage currents

Abstract: The effects of X-ray exposure on two types of p-n junction leakage current are presented. X-rays generate surface states at the oxide-silicon interface and lower the junction electric field at the surface. As a result, the usual field-insensitive generation-recombination current (type 1) increases and the field-sensitive leakage current (type 2) decreases. The type 1 current increases linearly with the incident energy density. From the increment of the type 1 leakage, the surface recombination velocity increases by 1*10/sup 3/ cm/s for every 120 mJ/cm/sup 2/ of incident X-ray exposure. Some surface states are responsible for the reduction of the surface electric field and thus the surface component of the type 2 current. The results resemble that of the late stage of hot-carrier stress. The surface states affecting these two types of leakage have different annealing properties. The ones that increase the type 1 current can be annealed out with a short heat cycle, while the ones that lower the type 2 current require a very long heat cycle to remove. >

Semiconductor device and a process for producing a semiconductor device

Abstract: The present invention relates to semiconductor device, a e.g., a CMOS, comprising a denuded region and a bulk-defect region, as well as the process for producing, e.g., a CMOS. In a conventional CMOS, the distance (dp) between the bulk-defect region and P+ -type source of drain region--(dp)--is greater than the distance (dn) between the bulk--defect--region and the P well--(dn)--. As a result, a leakage current can be generated in the PN junction. In order to eliminate the problems caused due to dp>dn, the present invention forms in a--semiconductor-substrate a bulk-defect region having a depth which is nonuniform in accordance with the nonuniform depth of the semiconductor elements.

High-temperature leakage current suppression in CMOS integrated circuits

Abstract: It has been found that the diffusion component of the pn junction drain-to-body reverse leakage current in a MOS transistor differs by as much as three orders of magnitude depending on whether it is fabricated in a substrate well or directly in the substrate. A theoretical description of the leakage suppession exhibited by a pn junction in a well is confirmed by measurement using a commercially available 3µm CMOS process, operating at temperatures up to 250°C.

Electron transit time through depletion layer of GaInAs pn junction

Abstract: Using an empirical formula for the electron velocity, the transist time through a Ga0.47In0.53As pn junction as a function of the applied voltage and other parameters is calculated. It is shown that a minimum transit time exists and that it can be used for modelling of the response time of a pin or avalanche photodiode made on an epitaxial Ga0.47In0.53As layer on InP substrate.

Junction breakdown prevention

Abstract: To provide protection against reverse breakdown of a pn junction (5), at least two annular moats (6) are provided to surround the region (4) within the junction. The innermost moat (6a) laterally bounds the region (4) so that the pn junction terminates along its length and the moat lies within the depletion region of the reverse-biased junction. The region of semiconductor body (2a) lying between the moats is of such a doping concentration that the depletion region extends to the surface (11) before the reverse breakdown voltage of the junction is reached. The moats are covered with a passivating material (7).

Semiconductor integrated circuit

Abstract: PURPOSE:To secure dielectric isolation between elements of a semiconductor integrated device even when a structure is made finer, by providing a high concentration n type impurity diffusion region in an inter-element separating region of the semiconductor integrated device formed on the same n type semiconductor layer. CONSTITUTION:First and second semiconductor element regions 1, 2 are constructed, each forming p type impurity diffusion regions 5, 6 on a n type semiconductor substrate 4. In addition, an inter-element separating region 3 is constructed forming a thick isolating oxide film 7 on the surface of the substrate 4 located on the region 3 and forming a high concentration n type impurity diffusion region 8 in a region located just under the film 7. If a back-biass voltage is applied to a pn junction with the above construction, a depletion layer tends to extend in a direction of the region 8. However, the extension of the depletion layer is restricted by the region 8 because the region 8 is highly concentrated, thereby preventing the depletion layers extending from the pn junctions from making contact with each other and interfering therebetween. Hereby, dielectric isolation between the regions 1, 2 can securely be executed.

Ultraviolet Light-Emitting Diode of Cubic Boron Nitride PN Junction

Abstract: The present paper deals with light-emitting diode action of a cubic boron nitride(cBN) pn junction; after explaining our substantiation of the LED action1), we show recent experimental results, then discuss light-emitting mechanisms and potentialities of the junction as light emitting devices.

Method of producing a field effect transistor with self-aligned gate metallization

Abstract: of EP01978381. A method for the production of a junction field effect transistor (JFET) with an autoaligned metallized gate, comprising, supported on a substrate (10), at least one layer (11) of a semiconductor material of a first type of conductivity, said method being characterized in that it comprises the following steps : - the deposit on the semiconductor layer (11) of a mineral protective layer (18), - the deposit on the protective layer (18) of a double layer (19 and 20) of organic resins, and the provision in this double layer (19 and 20) of a groove (22), the outer layer of the resin (20) running cantileverwise (21) over the groove (22), - the partial elimination of the protective coating (18) by ionic etching, through the groove (22) so as to leave an opening (23) with dimensions equal to these of the opening of the cantilever (21) and to those of the future gate, - low energy implantation, through the opening (23) in the protective layer (18), of atoms which form a pit (12) in the semiconductor layer (11), the conductivity of the pit (12) being opposite that of the said layer (11) so as to form a PN junction, the depth of implantation being greater than the diffusion path of metal atoms in the semiconductor layer (11), - low pressure and low power sputter deposition of the refractory metallized gate layer (13) in the form of a mushroom resting on the protective layer (18), - elimination of the double resin layer (19 and 20), - high energy implantation of two overdoped pits (16 and 17) in the semiconductor layer (11) with a self-alignment with respect to the gate metallized layer (13), which serves as a mask, and - completion of the transistor by the local elimination of the protective layer (18) and the deposit of two source and drain metallized layers (14 and 15) on the overdoped pits (16 and 17).

Laser programming of semiconductor devices using diode make-link structure

Abstract: A semiconductor device is programmed by a laser beam which causes a PN junction in a silicon substrate to be permanently altered. This produces a leakage path between a program node and a tank region in the substrate; the program node can be an input to a transistor in a CMOS circuit, for example, so this node will always hold the transistor on or off depending whether or not it has been laser-programmed. Preferably, the tank region is of opposite type compared to the substrate, so the program node is electrically isolated from the substrate in either case.

Scanning tunneling microscopy on cleaved silicon pn junctions

Abstract: A scanning tunneling microscope (STM) was used in air on cleaved Si pn junctions for junction delineation. Two-dimensional STM scans of a 0.3- mu m-deep pn junction localized the junction position to within 50 nm. One-dimensional scans of the same junction have a resolution of 7 nm. A dependence of the tunneling current on the local impurity concentration of the sample is also observed. The minimum detectable impurity concentration is below 10/sup 15/ cm/sup -3/. >