Showing papers on "p–n junction published in 1997"

Theory of Semiconductor Superjunction Devices

Abstract: A new theory of semiconductor devices, called "semiconductor superjunction (SJ) theory", is presented. To overcome the trade-off relationship between breakdown voltage and on-resistance of conventional semiconductor devices, SJ devices utilize a number of alternately stacked, p- and n-type, heavily doped, thin semiconductor layers. By controlling the degree of doping and the thickness of these layers, according to the SJ theory, this structure operates as a pn junction with low on-resistance and high breakdown voltage. Analytical formulas for the ideal specific on-resistance and the ideal breakdown voltage of SJ devices are theoretically derived. Analysis based on the formulas and device simulations reveals that the on-resistance of SJ devices can be reduced to less than 10-2 that of conventional devices.

Product wafer junction leakage measurement using corona and a kelvin probe

Abstract: Corona charge is applied to a semiconductor product wafer to reverse bias PN junctions. Measurements of voltage decay in the dark and in the light are made and combined to determine a PN junction leakage characteristic. A portion of the dark measurement is taken in the light to permit normalizing the light and dark measurements.

Edge termination structure

Abstract: An edge termination structure is created by forming trench structures (14) near a PN junction. The presence of the trench structures (14) extends a depletion region (13) between a doped region (12) and a body of semiconductor material or a semiconductor substrate (11) of the opposite conductivity type away from the doped region (12). This in turn forces junction breakdown to occur in the semiconductor bulk, leading to enhancement of the breakdown voltage of a semiconductor device (10). A surface of the trench structures (14) is covered with a conductive layer (16) which keeps the surface of the trench structures (14) at an equal voltage potential. This creates an equipotential surface across each of the trench structures (14) and forces the depletion region to extend laterally along the surface of semiconductor substrate (11). The conductive layers (16) are electrically isolated from an electrical contact (17) which contacts the doped region (12) and from the conductive layers (16) of neighboring trench structures (14).

Silicon diodes in avalanche pulse-sharpening applications

Abstract: Silicon diodes operated in an avalanche breakdown mode can he used to reduce, or sharpen, the rise times of driving pulses. Proper operation of a diode in this manner requires the application of a driving pulse with sufficient time rate of change of voltage dV/dt. The rapidly changing reverse bias produces an electron-hole plasma of sufficient density that the electric field strength in the n region of a p/sup +/-n-n/sup +/ structure is significantly reduced and the plasma is essentially trapped. In effect, the plasma generation causes the device to transition from a high-impedance state to a low-impedance state in a short period of time, and thus acts as a fast closing switch. This paper provides an overview of this mode of operation. A simplified theory of operation is presented. A comparison is made among the results of numerical modeling, the theory of operation of the silicon avalanche shaper (SAS) diode, and the theory of operation of the trapped-plasma avalanche-triggered transit (TRAPATT) mode of operation of a diode. Based on the results of numerical modeling, conclusions are drawn on what factors most greatly affect the performance of avalanche shaper diodes, and one optimized design is provided.

Positive temperature coefficient of breakdown voltage in 4H-SiC pn junction rectifiers

Abstract: It has been suggested that once silicon carbide (SiC) technology overcomes some crystal growth obstacles, superior SiC semiconductor devices would supplant silicon in many high-power applications. However, the property of positive temperature coefficient of breakdown voltage, a behavior crucial to realizing excellent power device reliability, has not been observed in 4H-SiC, which is presently the best-suited SiC polytype for power device implementation. This paper reports the first experimental measurements of stable positive temperature coefficient behavior observed in 4H-SiC pn junction rectifiers. This research indicates that robust 4H-SiC power devices with high breakdown reliability should be achievable after SiC foundries reduce material defects such as micropipes, dislocations, and deep level impurities.

Semiconductor Devices a Simulation Approach

Abstract: 1. Introduction. I. BASICS. 2. Fundamentals of Electromagnetism and its Numerical Analysis. 3. Transport Phenomena and Their Numerical Analysis. II. SEMICONDUCTOR SIMULATION. 4. The Semiconductor Equations. 5. Numerical Solution of PDEs. 6. The SGFramework. III. SEMICONDUCTOR DEVICES. 7. PN Junction Diodes. 8. Bipolar Junction Transistors. 9. Junction Field-Effect Transistors. 10. Metal-Oxide-Semiconductor Structures. 11. Power Semiconductor Devices. IV. ADVANCED TOPICS. 12. Mixed-Mode Simulations. 13. Kinetic Transport Models. 14. Related Work. 15. The SGFramework User's Manual.

Fabrication of a SiC semiconductor device comprising a pn junction with a voltage absorbing edge

Abstract: A semiconductor component and a method for processing said component, which comprises a pn junction, where both the p-conducting (3) and the n-conducting layers (2) of the pn junction constitute doped silicon carbide layers and where the edge of the higher doped conducting layer of the pn junction exhibits a charge profile with a stepwise or uniformly decreasing total charge or effective surface charge density from the initial value at the main pn junction to a zero or almost zero total charge or charge density at the outermost edge of the junction following a radial direction from the central part of the junction towards the outermost edge.

Infrared solid state image sensing device

Abstract: An infrared solid state image sensing device is characterized by an infrared absorbing section (400) which is formed corresponding to each of pixels arrayed in a two-dimensional manner and adapted for absorbing and transducing incident infrared rays into heat, a temperature detector section (300) arranged on a semiconductor substrate (1) corresponding to each of pixel arrays constituted by a plurality of serially connected silicon pn junction diodes which are biased in a forward direction, a cavity section (200) formed in each region on the semiconductor substrate (1) where the temperature detector section (300) is formed, a supporting mechanism (supporting legs 21, 22) constituted with a material of high thermal resistivity for supporting the temperature detector section on the semiconductor substrate above the cavity section, and a junction column (140) for holding the infrared absorbing section (400) away from the temperature detector section (300) and for thermally coupling the infrared absorbing section (400) and the temperature detector section (300). Thus, all manufacturing processes except for removal of a sacrifice layer may be carried out on a silicon VLSI process line, and no active element except for the silicon pn junction diodes for the temperature detector is necessary in the pixel portion. Therefore, an inexpensive infrared image sensing device having improved productivity and high uniformity may be stably manufactured.

Formation of ultra-shallow semiconductor junction using microwave annealing

Abstract: The present invention is a method of utilizing microwave energy for annealing of ion implanted wafers. By controlling the time, power density and temperature regime, it is possible to substantially fully anneal the wafer while limiting (and substantially preventing) the diffusion of dopant into the silicon, thereby producing higher performance scaled semiconductor devices. It is also possible, using different conditions, to allow and control the dopant profile (diffusion) into the silicon. Another aspect of the present invention is a method of forming a PN junction in a semiconductor wafer having a profile depth less than about 50 nm and a profile wherein the net doping concentration at said PN junction changes by greater than about one order of magnitude over 6 nm wherein the surface concentration of said dopant is greater than about 1×10 20 /cm 3 . The method includes providing a semiconductor wafer which can be single crystal or amorphous surface; implanting into said surface a dopant; exposing the surface to an energy source; the energy source being applied to supply energy at a rate such that the surface is substantially fully annealed before the dopant diffuses greater than about 50 nm. Another aspect of the present invention is having a PN junction formed between a first material of a first conductivity type and a second material of a second conductivity type, the junction has a depth of less than about 50 nm, in the first material the net doping concentration at the junction changes by greater than about one order of magnitude over 10 nm, the maximum value of said first conducting material of said wafer has a surface concentration of greater than about 1×10 20 /cm 3 .

SiC semiconductor device comprising a pn junction

Abstract: A semiconductor device of planar structure, comprises a pn junction, formed of a first type conducting layer and on top thereof a second type conducting layer, both layers of doped silicon carbide, the edge of the second of the layers being provided with an edge termination (JTE), enclosing stepwise or continuously decreasing effective sheet charge density towards the outer border of the termination, wherein the pn junction and its JTE are covered by a doped or undoped SiC third layer.

Bidirectional lateral insulated gate bipolar transistor having increased voltage blocking capability

Abstract: A bidirectional lateral insulated gate bipolar transistor (IGBT) includes two gate electrodes. The IGBT can conduct current in two directions. The IGBT relies on a double RESURF structure to provide high voltage blocking in both directions. The IGBT is symmetrical, having an N-type drift region in contact with an oxide layer. A P-type region is provided above the N-type drift region, having a portion more heavily doped with P-type dopants. The double RESURF structure can be provided by a buried oxide layer, a floating doped region, or a horizontal PN junction. The IGBT can be utilized in various power operations, including a matrix switch or a voltage source converter.

Molecular rectification in oriented polymer structures

Abstract: Polymeric semiconductor devices are receiving increasing attention in view of potential applications requiring low-cost processing over large areas.'"*] In this respect, unlike with evaporated molecules, the wet-processing capability of polymers offers total compatibility with other complemen-tary technologies. The concepts from which organic-semi-conductor devices are designed are mostly derived from in-organic-semiconductor physics and technology.''] In order to build efficient organic-semiconductor devices such as electroluminescent or photovoltaic solar cells, a rectifying junction is required. Such junction can be of two main typed4] Schottky junctions between an organic semi-conductor and a metal, and p-n junctions between two p-and n-type organic-semiconductors. The Schottky junctions often suffer from degradation problems originating from electrochemical potential differences at the rectifying con-tacts, which induce diffusion of electrode material into the polymer.'" Such a drawback is corrected with p-n junctions in which metal to polymer contacts are ohmic. However, p-n junctions require the use of two polymer layers with wet-processing compatibility. Moreover n-type organic-semiconductors are less common than p-type ones owing to their lower stability under oxygen which is a consequence of their reductive behavior. We report here a different approach in which oriented diode-like molecules, the so-called push-pull molecules used in nonlinear optics,[6] are contained inside a polymer binder. Oriented molecules induce a rectifying effect, be-having as a distributed homojunction within a single poly-mer thin film. In order to demonstrate the principle, we start with an initially symmetric structure: the polymer film is sandwiched between two identical electrodes. The cur-rent-voltage characteristics of the device are also symme-trical. By application of a static electric field through the polymer film, while heating near the glass transition tem-perature (T,,) dopant molecules are oriented in the field with an order parameter (cosO).['] The current-voltage characteristics then become strongly asymmetric. Experimentally, molecular order is controlled using sec-ond harmonic generation (SHG): it appears that

Insulated gate type bipolar transistor

Abstract: PURPOSE: To eliminate a latchup by controlling a first carrier electric resistance value by a source layer shape between a first contact and a channel region, and preventing conduction of a pn junction. CONSTITUTION: A p + type silicon substrate is prepared, and an n - type layer of low impurity concentration semiconductor is formed by an epitaxial growth. A p + type drain layer 1, an n - type drain layer 2 are formed of the substrate and the n - type layer, and the surface of the layer 2 is oxidized to form a gate oxide film 3. A gate electrode 4 of a polysilicon film is formed thereon. With the electrode 4 as a mask boron is diffused to form a p-type base layer 5. Then, the center of the window of the electrode 4 is covered with a resist film patterned in a shape opened in a T shape, phosphorus ions are implanted to form an n + type source layer 6. Since carrier electric resistance value R 1 is controlled by the shape of the layer 6 to prevent conduction of the pn junction, a source resistance is improved to prevent a latchup. COPYRIGHT: (C)1992,JPO&Japio

Field-assisted photoemission from InP/InGaAsP photocathode with p/n junction

Abstract: A high quantum efficiency of photoemission to a 1.35 μm threshold has been achieved from an externally biased InP/InGaAsP photocathode which has a p/n junction instead of a Schottky contact. The quantum efficiency at 1.3 μm is 5% (electron per incident photon) with the photocathode cooled to −80 °C. The photocathode consists of a n+InP contact layer, a p−InP photoelectron-emitting layer and a p−InGaAsP photon-absorbing layer on a p+InP substrate.

Low-frequency noise and performance of GaN p-n junction photodetectors

Abstract: We report on low-frequency noise characteristics of visible-blind GaN p-n junction photodetectors Carrier hopping through defect states in the space charge region, believed to be associated with dislocations, is identified as the main mechanism responsible for the dark conductivity of the photodiodes The dark current noise has the 1/f character and obeys the Hooge relation with /spl alpha//spl ap/3

Method for fabricating a field effect transistor having elevated source/drain regions

Abstract: A method of making a semiconductor device with a shallow (on the order of 50 nm) PN junction depth includes the steps of forming, on a region of a semiconductor substrate in which an impurity diffusion region having the shallow PN junction depth is to be formed, a selectively grown silicon layer (raised layer) containing a substance such as carbon which easily combines with point defects in the semiconductor substrate or a substance such as nitrogen which prevents an impurity providing an electrical conductivity from diffusing, ion-implanting an impurity of one conductivity type into the selectively grown silicon layer, and forming the diffusion region by activating the implanted impurity of one conductivity type and diffusing the impurity of one conductivity type into the semiconductor substrate, by means of heat treatment

Theory of noise in p-n junction light emitters

Abstract: The intensity noise of light generated by semiconductor lasers and light-emitting diodes is treated by semiclassical Langevin equations. An independent equation for the junction voltage dynamics is considered, and the non-Markoffian nature of the pump current is decomposed into Markoffian carrier injection and a regulation mechanism due to charging effect at the junction. The intensity noise power spectrum and squeezing bandwidth predicted by these equations agree well with recent experimental results. External current noise generated as a result of the internal noise process and subsequent relaxation process is calculated. Also, correlations between the carrier-number fluctuation and the junction-voltage fluctuation, and between the emitted photon flux fluctuation and the junction-voltage fluctuation are studied in detail.

Method of producing a solar cell

Abstract: A solar cell and a method of producing the same which realizes electrical separation of the p n junction in a simple manner, and a method of producing a semiconductor device a method of producing a semiconductor device in which an electrode is formed by using a metallic paste material on a substrate covered with a silicon nitride film or a titanium oxide film, wherein a glass paste 104 composed mainly of glass which has a property of melting silicon is provided on an n type diffusion layer 101 in the p n junction; the substrate is baked so that penetration of the n type diffusion layer 101 is effected by the glass paste; aluminum is diffused in the n type diffusion layer 101 below a p electrode 103 formed of an aluminum silver paste to thereby form a p type inversion layer 105 inverted to a p type, whereby the electrical separation of the p n junction can be realized. Further, when a metallic paste material is provided on an insulating film and the metallic paste material is baked, the material penetrates the insulating film to electrically contact with the semiconductor substrate.

Hot-implantation of nitrogen donors into p-type a-SiC and characterization of n + -p junction

Abstract: N+ implantation into p-type a-SiC (6H-SiC, 4H-SiC) epilayers at elevated temperatures was investigated and compared with implantation at room temperature (RT). When the implant dose exceeded 4 × 1015 cm−2, a complete amorphous layer was formed in RT implantation and severe damage remained even after post implantation annealing at 1500°C. By employing hot implantation at 500~800°C, the formation of a complete amorphous layer was suppressed and the residual damage after annealing was significantly reduced. For implant doses higher than 1015 cm−2, the sheet resistance of implanted layers was much reduced by hot implantation. The lowest sheet resistance of 542Ω/ was obtained by implantation at 500 ~ 800°C with a 4 × 1015 cm−2 dose. Characterization of n+-p junctions fabricated by N+ implantation into p-type epilayers was carried out in detail. The net doping concentration in the region close to the junction showed a linearly graded profile. The forward current was clearly divided into two components of diffusion and recombination. A high breakdown voltage of 615 ∼ 810V, that is almost an ideal value, was obtained, even if the implant dose exceeded 1015 cm−2. By employing hot implantation at 800°C, the reverse leakage current was significantly reduced.

High voltage P+ polysilicon/N- 6H-SiC heterojunction diodes

Abstract: A novel P/sup +/ polysilicon/N 6H-SiC heterojunction diode is reported which combines the advantages of both Schottky barrier diodes and pn junction diodes. The unterminated heterojunction diodes have excellent rectification characteristics and a high breakdown voltage of 220 V. The forward voltage drop measured at 100 A/cm/sup 2/ is 2.7 V, close to the calculated value of 2.4 V. The suitability of this device for high speed switching applications was experimentally confirmed using reverse recovery measurements.

Semiconductor device with deliberately damaged layer having a shorter carrier lifetime therein

Abstract: A technique of improving a reverse recovery characteristic of a semiconductor device which solves a technical problem of breakdown voltage reduction which has conventionally caused in enhancing soft recover. To solve the technical problem, in a PN junction between a P type layer and an N type layer, a heavy metal such as platinum is firstly diffused into an—layer and N+ layer of the N type layer. Subsequently, helium ion is implanted into the inside of the—layer from the interface between the P type layer and the N+ layer to a predetermined depth, so that the N− layer in the vicinity of the junction is damaged to form, in the—layer, a low lifetime region having a carrier lifetime smaller than that of the N type layer and a resistibility that decreases monotonically. Such a technique may be applied to diodes, and particularly, free-wheel diodes in power modules.

Method of manufacturing trench-isolated semiconductor device

Abstract: The top surface of a P-type semiconductor substrate is partitioned into an active region to be formed with an element and an isolation region surrounding the active region. The isolation region is composed of trench portions and dummy semiconductor portions. An interlayer insulating film is deposited on the substrate, followed by a wire formed thereon. In each of the semiconductor portions, an impurity diffusion layer is formed simultaneously with the implantation of ions into the element so that a PN junction is formed between the impurity diffusion layer and the silicon substrate. A capacitance component of the wiring-to-substrate capacitance in the region containing the semiconductor portions is obtained by adding in series the capacitance in the impurity diffusion layer to the capacitance in the interlayer insulating film, which is smaller than the capacitance only in the inter layer insulating film. What results is a semiconductor device having lower total wiring to-substrate capacitance and a higher operating speed.

Analog switching circuit

Abstract: An analog switching circuit comprises an insulated-gate field-effect transistor (Q20) having two n-type input-side and outpu-side semiconductor regions (201, 202) and a p-type semiconductor substrate region 203, for controlling conductiveness between an input terminal (IN) and an output terminal (OUT) based on a gate potential. A surge pulse detecting circuit (1020), responsive to an electric potential (Vi) of the input terminal (IN), produces a detection signal of a surge pulse equivalent to a forward bias of a PN junction formed between the semiconductor substrate region (203) and the input-side semiconductor region (201). A substrate potential setting circuit (1010) varies an electric potential of the semiconductor substrate region (203) in response to the electric potential (Vi) of the input terminal (IN) when aby detection signal is produced. Furthermore, a gate potential control circuit (1030) varies the gate potential of the insulated-gate field-effect transistor (Q20) in the same direction as the electric potential of the semiconductor substrate region (203) when the detection signal is produced.

Solar cell and its manufacturing method, and manufacturing method of semiconductor device

Abstract: PROBLEM TO BE SOLVED: To provide a solar cell, together with its manufacturing method, of the structure wherein electrical separation of pn junction is realized with a simple method while manufacturing cost is reduced and productivity is significantly improved, and to provide a method for manufacturing a semiconductor device comprising a new electrode formation method for the case where a metal paste material is used with a structure comprising on its substrate surface a silicon nitride film or titanium oxide film. SOLUTION: On an n-type diffusion layer 101 of pn junction, a glass paste 104 whose main component is glass capable of melting silicon is provided and sintered to allow the glass paste 104 to etch the n-type diffusion layer 101, so that an aluminum is diffused in the n-type diffusion layer 101 under a p- electrode 103 of aluminum silver paste to form a p-type inversion layer 105 which is inverted into p-type, thus realizing electrical separation of pn junction. A metal paste material is provided on an insulating film and then sintered, for coming into contact electrically with a semiconductor substrate through an insulating film.

Semi-insulating surface light emitting devices

Abstract: Light emitting devices are requiring greater switching speeds to achieve greater modulation bandwidths. The problems of intrinsic capacitance associated with conventional semiconductor heterojunction devices are reduced by the reduction of pn junction capacitance as well as the use of a semi-insulating blocking layer and a conductive substrate. Non-linearity of optical power output versus bias current is addressed by a heat dissipation scheme using the semi-insulative and conductive layers of the device.

Electrically programmable antifuse using metal penetration of a P-N junction

Abstract: An antifuse is described that can be formed without masks or mask steps beyond those required for a conventional CMOS process. The antifuse includes adjacent p-type and n-type diffusion regions that together form a P-N junction. The diffusion regions are tapered toward one another such that the P-N junction is located at a necked-down region of the antifuse. The diffusion regions are connected to respective terminals of a programming-voltage source via first and second metal electrical contacts, typically of aluminum metal. Each of the first and second electrical contacts includes a point directed toward the other of the first and second electrical contacts. The antifuse is programmed by providing a reverse-bias programming voltage across the electrical contacts. This programming voltage exceeds the breakdown voltage of the P-N junction so that current flows through the necked-down region of the antifuse between the points on the respective first and second electrical contacts. This current heats the region between the opposite points to create a hot filament between the first and second metal contacts. Metal from the metal contacts then diffuses along the filament to form a conductor between metal contacts.

Junction type field-effect semiconductor device and its manufacture

Abstract: PROBLEM TO BE SOLVED: To sharply minimize a leakage current by a method wherein the 0001 surface of a silicon carbide single crystal of a hexagonal crystal or an equivalent surface thereto is made the main surface, a groove part is formed thereon and a sidewall of the groove part is made parallel with the surface with a face index 1-100 of the silicon carbide single crystal or an equivalent face thereto. SOLUTION: In contact with an n-type layer 11 having low resistivity an n-type drain layer 12 having higher resistivity than this layer is provided. On the source side, a groove part 16 is formed and the semiconductor surface has projections and depressions. A n-type source layer 14 is formed on a region of the main surface 20 of the projection part by ion implantation and a p-type layer 13 is formed on the base part of the groove part 16 by epitaxial growth. At this time, the main surface 20 is made to be parallel with a hexagonal crystal silicon carbide 001 crystal face and a side wall 21 of a groove part 16 is to be parallel with a 1-100 face. Thereby, even if a pn junction face with a p-type layer may become zigzag, there is no danger of causing breakdown due to the concentration of an electric field on the projection part so as to sharply minimize a leakage current and improve reliability.

A Comparative Study of n+/p Junction Formation for Deep Submicron Elevated Source/Drain Metal Oxide Semiconductor Field Effect Transistors

Abstract: Ultrashallow elevated n'/p junctions (∼75 nm) incorporating selectively deposited epitaxial silicon layers were fabricated. The undoped epi layers (∼100 nm) were deposited on exposed diffusion areas in an Advanced Semiconductor Material Epsilon I system specifically designed for low thermal budget single-wafer processing. Shallow junctions (∼75 nm) were formed by ion implantation (As, 4 x 10 15 /cm 2 , 80 keV) into undoped epi layers and out-diffusion into the underlying substrate. Alternatively, an ion implanted (As, 4 x 10 15 /cm 2 , 60 keV) elevated layer was utilized to contact a shallow junction, which was formed (As, 1.5 x 10 15 /cm 2 , 15 keV) before the epi deposition. All junctions were annealed at 950°C for 10 s. Nonsilicided elevated junctions and conventional nonelevated (As, 1.5 x 10 15 /cm 2 , 15 keV) ones displayed very similar junction characteristics. Silicided nonelevated ultrashallow junctions, however, showed large reverse leakage current due to the substrate consumption. Both silicided elevated (post-epi and pre-epi) junctions exhibited excellent forward characteristics and low reverse leakage current. The difference in the reverse leakage characteristics of these two elevated junctions was attributed to the epi faceting formed at the sidewall edge of localized oxidation of silicon isolation. Deep submicron n = channel metal oxide semiconductor field effect transistors incorporating these junctions were also fabricated and electrically tested. Both elevated source/drain (S/D) devices show superior current driving capability compared to nonelevated ones as a result of much reduced parasitic resistance from contact source/drain junctions.