Showing papers on "Parasitic element published in 1995"

Current controlled bandpass filter based on translinear conveyors

Abstract: A new concept to take advantage of the parasitic resistance that appears on port X of the second-generation current conveyors is introduced. This parasitic resistance, which is controllable in current, leads to the definition of the second generation current controlled conveyors (CCCII). A current controlled bandpass filter, operating in the current mode, is also described. It uses only two CCCII+s and two capacitors. Its central frequency can be adjusted by acting on the bias current of the conveyors. SPICE simulation results, in agreement with theory, are given for central frequencies around 30 MHz.

Current-dependent light-emitting element drive circuit for use in active matrix display device

Abstract: In a light-emitting element drive circuit in an active matrix display device, at least one current-control transistor controls a current flowing through a light-emitting element. The current-control transistor and the light-emitting element are connected in parallel to each other. A constant current source is connected to a junction between one electrode of the light-emitting element and one electrode of the transistor through which the current 8s controlled to flow. The other electrodes of the light-emitting element and the transistor are connected to a common electrode which may be grounded via a resistor. In other configuration, it may be arranged that the light-emitting element and a capacitance are connected in parallel to each other. In this case, the current-control transistor is connected to a function between the light-emitting element and the capacitance so as to use charging and discharging operations of the capacitance for driving the light-emitting element.

Semiconductor device having built-in high frequency bypass capacitor

Abstract: A high frequency bypass capacitor (36, 36') is built into a thin-film portion (16, 16') of a polymer carrier substrate (15) of a PBGA (10). The carrier substrate (15) has both a stiffener (18) and a thin-film portion (16, 16') which has multiple metal layers (24, 28, 30, 32). The power supply planes (28, 30) of these metal layers are used to form built-in bypass capacitors (36, 36'), wherein the power supply planes are specifically designed to be adjacent and parallel layers. An ultra thin film laminate construction provides thin dielectric films (26) between the metal layers to allow the bypass capacitor to be placed very dose to the attached semiconductor die (12) to further reduce parasitic inductance and resistance between die connections (14) and the bypass capacitor. The built-in feature minimizes inherent parasitic series inductance and resistance, thus enabling the filtering of unwanted low pulse width glitches on a power plane connected to VLSI devices at operating frequencies at or above 100 MHz.

Modelling winding losses in high-frequency power inductors

Abstract: A high-frequency model of iron-powder-core inductors is studied. The skin and proximity effects that cause the winding parasitic resistance to increase with the operating frequency are considered. The inductor self-resonance due to the parasitic capacitances is taken into account as well. The frequency response of the inductor model is compared to that of an experimentally tested iron-powder-core inductor. Expressions giving the ac resistance as a function of the operating frequency are given. These expressions allow for an accurate prediction of the inductor power loss over a wide frequency range. The measured and calculated values of the inductor impedance magnitude and phase, the real and imaginary parts of the inductor impedance, the inductance, and the inductor quality factor are plotted versus frequency and compared. Theoretical results were in good agreement with those experimentally measured. A design procedure for solid wire winding inductors based on the results of the inductor modelling is also given in the paper.

Module interconnect adapter for reduced parasitic inductance

Abstract: A mounting for a solderable component module (SCM™) interconnect includes an elongated trench or blind via for receiving an edge of the module. The interconnect may be adjusted to reduce the parasitic inductance associated with the connection of the SCM interconnect and the motherboard. Preferably, the design of the finger connectors associated with the SCM interconnect or other board module can be adjusted to reduce parasitic inductance. Alternatively, the capacitance associated with the SCM interconnect or motherboard may be adjusted. The SCM interconnect preferably includes finger connectors which have a rectangular shape. The finger connectors preferably have a shape wherein the length is greater than the width and have an enhanced thickness which reduces parasitic inductance. The finger connectors are spaced close together.

Novel current–voltage characteristics in an InP‐based resonant‐tunneling high electron mobility transistor

Abstract: We report novel current–voltage characteristics in an InP‐based resonant‐tunneling high electron mobility transistor (RTHEMT). This device incorporates a pseudomorphic InGaAs/AlAs/InAs resonant‐tunneling diode into the source of a nonalloyed ohmic contact InAlAs/InGaAs high electron mobility transistor. Both pronounced negative differential resistance and negative transconductance are observed at room temperature. Most significantly, a near‐flat valley current is obtained in the output current–voltage characteristics. This feature is achieved by the nonalloyed ohmic contact cap layer structure employed in the HEMT, which significantly reduces the parasitic resistance. The novel characteristics of RTHEMTs should lead to many attractive circuit applications.

Influence of impact-ionization-induced base current reversal on bipolar transistor parameters

Abstract: In this paper we describe a set of measurements representing a complete characterization of impact-ionization effects in bipolar transistors. We demonstrate that impact-ionization significantly influences the dependence of base resistance on current and voltages applied to the device. A dc method for the simultaneous extraction of all parasitic resistances in bipolar transistors is presented. The method can separate the influence of current-crowding on the base resistance from that of base width and conductivity modulation; the collector parasitic resistance is measured in the active region. Starting from the parameters extracted by means of these techniques, a complete and accurate circuit-model of impact-ionization effects can be defined. >

Semiconductor integrated circuit having elongated fixed potential lines to reduce noise on the lines

Abstract: In a semiconductor integrated circuit device of the invention, a fixed potential line is extended longer than required on the semiconductor integrated circuit device, so that a parasitic inductance of the fixed potential line is increased, and accordingly an LC filter (low pass filter) operates to absorb high frequency noises.

Capacitance elimination circuit which provides current to a node in a circuit to eliminate the effect of parasitic capacitance at the node

Abstract: A capacitance elimination circuit for eliminating known parasitic capacitance at a node in a circuit. The capacitance elimination circuit is particularly useful at a connection of multiple pass gates in a switch matrix of a programmable logic device (PLD). The capacitance elimination circuit includes a current measuring device including a measuring capacitor having a first end connected to the node having the known capacitance. A second end of the measuring capacitor is connected to a current supply mechanism which provides current to the node to replace current withdrawn by the parasitic capacitance. In one embodiment, the current supply mechanism includes a first current mirror made up of transistors having a first channel type, the first current mirror having one arm coupled to the second end of the measuring capacitor. Another arm of the first current mirror is connected to an arm of a second current mirror made up transistors having a second channel type. Another arm of the second current mirror is then connected to the node to replace current withdrawn by its parasitic capacitance. Current gain provided by the first and second current mirrors is controlled to be substantially equal to current loss due to the parasitic capacitance and the measuring capacitor.

Accurate parasitic resistance extraction for interconnection analysis

Abstract: With the further scaling down of feature sizes, parasitic resistance is becoming more important for interconnection analysis. Previous resistance modeling and extraction methods either sacrifice too much speed for accuracy or sacrifice too much accuracy for speed. Neither of which is sufficient for effective interconnection analysis. In this paper we present a parasitic resistance extraction methodology which is both fast and accurate. The strategy is to fracture the resistive polygons into regions of different electromagnetic complexity and then use different algorithms to solve each region of complexity. Experimental results show that extracted resistances are within 5% of pure FEM resistance extraction for most test cases and within 10% for a few extreme cases while performing the extraction only about an order of magnitude slower than the path-finding parasitic resistance extraction technique.

Improving the scan performance of probe-fed microstrip patch arrays on high dielectric constant substrates

Abstract: This paper presents a thorough investigation into the use of E-plane parasitic elements to remove scan blindness in probe-fed microstrip patch phased arrays using a rigorous full-wave analysis. It is shown that the addition of an E-plane parasitic element in the unit cell of the array can enhance the impedance scanning range; however, the parasitic element must be resonating. As a consequence of this, the method of scan blindness removal is only suited to microstrip patch arrays mounted on high dielectric constant material. A novel configuration incorporating a varactor diode to reduce the significant reactive nature of the input impedance at large scan angles is introduced which further improves the scanning potential of the parasitic element array. A further modification to the unit cell is proposed which allows the array to operate over a broad frequency range. For all the configurations considered, comparisons of active reflection coefficient, scan impedance behavior, efficiency, and cross-polarization levels are presented. >

Fast and accurate extraction of parasitic resistances for nonlinear GaAs MESFET device models

Abstract: A new and accurate technique for extracting the parasitic resistance values from GaAs MESFET's for nonlinear circuit models is presented. The technique makes use of only two simple dc measurements. Using this extraction method, good agreement between simulated and measured data for the nonlinear Statz MESFET model is obtained, so it is very appropriate for large-signal device and circuit modeling purposes. The presented extraction method is implemented in HP-ICCAP, a software tool for parameter extraction. In addition, all the measurements are controlled by this software, so a high level of automation is obtained.

Power substrate element topology

Abstract: An inverter circuit includes a pair of switching devices coupled in series across high and low sides of a direct current bus. An output line is coupled between the devices for conducting controlled alternating current power produced by timed switching of the devices. A flyback diode is electrically coupled a in parallel with each switching device and is physically positioned adjacent to the opposite switching device in the pair. Conducting paths between each diode and the associated switching device are preferably physically positioned adjacent to conducting paths between the switching devices and the output line. The placement of the elements cancels or reduces parasitic inductance during switching. Three similar arrangements may be provided in parallel in a three phase inverter. The inverter may be incorporated into a power substrate including a rectifying circuit for converting alternating current power to direct current power to be applied to the bus.

MISFET and complementary MISFET device having high performance source and drain diffusion layer

Abstract: A source and drain diffusion layer of a transistor has a junction of a shallow depth and low in parasitic resistance and parasitic capacitance The transistor includes a gate insulator formed on a principal plane of a semiconductor substrate, a gate electrode formed on the gate insulator, and source and drain diffusion layers of one conductivity type formed on the principal plane of the semiconductor substrate across the gate electrode A semiconductor thin film layer doped with an impurity of the same conductivity type is selectively deposited on the principal plane of the semiconductor substrate on which the source and drain diffusion layers are formed A facet face is formed at an end portion of the semiconductor thin film which opposes to a sidewall of the gate electrode The facet face has an inclination angle between a sidewall face of the gate electrode and the principal plane of the semiconductor substrate

Array element pattern shaping by a parasitic element

Abstract: The authors show that one can shape an array element pattern suitable for a wide-scanning phased array antenna by providing a parasitic element in front of the stripline dipole. The length of the parasitic element should be about 20% shorter than that from which the maximum gain of the single element is obtained. It is expected that one can fabricate a millimeter wave active phased array antenna with a wide scanning range easily by this technology.

Frequency-resolved measurements for the characterization of MOSFET parameters at low longitudinal field

Abstract: A new technique is presented to extract the main parameters required for transistor modeling at low longitudinal fields (parasitic resistance, intrinsic conductivity factor, threshold voltage, and body factor k) from a single MOSFET. The method makes use of easy-to-perform AC frequency-resolved measurements to overcome repeatability and accuracy problems encountered with DC data. The technique has been satisfactorily validated on MOSFET's down to 0.8 /spl mu/m channel length. >

Circuit for measuring the state of charge of an electrochemical cell

Abstract: The invention relates to a circuit for measuring the state of charge of an electrochemical cell that includes a parasitic resistance. The circuit comprises: means for subjecting the electrochemical cell to a reference voltage less than its nominal voltage, so as to cause it to deliver a discharge current; means for measuring the discharge current and providing an indication of the state of charge of the electrochemical cell; and correction means for correcting the reference voltage as a function of the discharge current, the correction means providing a corrected reference voltage that compensates for the parasitic resistance.

Semiconductor light emitting element drive circuit

Abstract: PURPOSE:To obtain a current pulse waveform free of overshoot and ringing, and prevent generation of parasitic inductance. CONSTITUTION:A semiconductor light emitting element drive circuit for driving a light emitting element 4 is provided with the following a bipolar transistor 1 which drives the light emitting element 4 by applying a control signal for driving the light emitting element 4 to the base, and making a current flow across the emitter and the collector in response with the control signal, and an insulated gate type transistor 3 which acts as a constant current supply connected with the bipolar transistor 1.

Mounting structure of optical semiconductor device

Abstract: PROBLEM TO BE SOLVED: To enable stable operation when a high frequency signal is inputted, by connecting a transmission board and an optical semiconductor device, through a flexible board provided with a transmission line whose impedance is set as a specified value wherein impedances of the transmission board and the optical semiconductor device are matched with each other. SOLUTION: A first board 20 constituting a second transmission line 21 is connected with a transmission board forming a first transmission line on a base, through a second signal line 21a, as a means for electrically connecting an optical semiconductor device, which is formed on an insulating layer 20a composed of polyimide or the like by metallizing or the like, and ground conducting layers 21b which are arranged on both sides of the second signal line 21a at specified intervals. Thereby parasitic components such as parasitic inductance and parasitic capacitance are not practically generated in electrically connected parts. Hence, deterioration of waveform is not caused when a high frequency signal is inputted, and mounting structure of an optical semiconductor element having excellent high frequency characteristics is realized. COPYRIGHT: (C)1997,JPO

Sub-20 ps high-speed ECL bipolar transistor with low parasitic architecture

Abstract: Reducing parasitic capacitance and resistance is an effective means of both improving ECL gate delay and increasing f/sub T/ values. In this paper, we demonstrate a device with sub-20 ps t/sub pd/ values even at f/sub T/=23 GHz, a performance which has been achieved by implementing a number of techniques. These include 1) low-stress deep- and shallow-trench isolation to reduce C/sub CB/, 2) a low-concentration collector design to reduce C/sub CB/, 3) NiSi-salicided base and emitter electrodes to reduce R/sub B/, and 4) a shallow base formed by double diffusion technology for relatively high f/sub T/ with a low-concentration collector design. The low-concentration collector design gives the device a high breakdown voltage of 6.2 V. >

Wiring parasitic load calculating method

Abstract: PROBLEM TO BE SOLVED: To accurately calculate a wiring parasitic load such as parasitic capacitance and parasitic resistance by performing pattern matching between layout pattern data that reference pattern data has and layout data consisting of layout data or symbolic data. SOLUTION: A layout pattern represented with layout data or symbolic data is read in, and a wire whose wiring parasitic load is to be found is determined as a reference wire for the read-in layout pattern data and divided into three-dimensional areas (S1). After the division is completed, combinational pattern data in the three-dimensional areas represented by the divided wiring grating spaces are detected (S2) and integrated (S3). Then the pattern matching between combinational pattern data after detection and accumulation and combinational pattern data that each reference pattern data has is performed to detect the wiring parasitic load that each reference pattern data has.

Circuit arrangement for supplying an alternating signal current

Abstract: A high frequency amplifier circuit arrangement has an output current path having one end coupled to a reference potential for supplying an alternating signal current at an output terminal. The influence of parasitic inductances in the output current path on the amplitude of the alternating signal current is reduced or cancelled in that compensation is provided for the influence of a parasitic inductance in the coupling between the output current path and the reference potential by means of a compensation circuit which applies an alternating compensation current to a (first) node between the output current path and the parasitic inductance. This compensation current is in phase opposition to and of at least substantially the same magnitude as the alternating signal current.

Semiconductor device and its manufacture

Abstract: PURPOSE:To reduce a parasitic capacity between a gate and a drain and to reduce a parasitic resistance between a channel and a source/drain regarding the method of manufacturing a semiconductor device which contains a MOS transistor. CONSTITUTION:A manufacturing method includes a process in which a gate electrode 15 composed of a semiconductor is formed on a semiconductor layer 12 via a gate oxide film 13 for a MOS transistor, a process in which an oxidation-resistant film 16 is formed on the semiconductor layer 12 situated on both sides of the gate electrode 15 and a process in which the surface of the gate electrode 15 is oxidized and in which a bird's beak oxide film 18 creeping into the inside is formed on both side parts at the bottom part of the gate electrode 15.

Complementary mosfet and its manufacture

Abstract: PURPOSE: To increase the operation speed of a complementary MOSFET and reduce its parasitic resistance, by making the junction width of the shallow junction source/drain of its N-channel MOSFET suitable CONSTITUTION: In a complementary MOSFET, a P-channel MOSFET wherein first and second sidewalls 45, 46 are formed and an N-channel MOSFET wherein only the second sidewall 46 is formed are provided, and the sidewall width of the P-channel MOSFET is made larger by the first sidewall width than the sidewall width of the N-channel MOSFET COPYRIGHT: (C)1996,JPO

Soi substrate, semiconductor device using the same, and its manufacture

Abstract: PROBLEM TO BE SOLVED: To prevent attenuation of signals and improve high frequency characteristics, by reducing the influence due to a parasitic element to a substrate. SOLUTION: Semiconductor regions 4A, 4B, 4C in which circuit elements like active elements constituted of bipolar transistors Q or passive elements constituted of load resistances RL and feedback resistances RE are formed are formed on a retaining substrate 2 whose resistivity is larger than or equal to about 50Ωcm. Since resistivity of the support substrate 2 is increased, influence due to a parasitic element to a substrate is reduced, and attenuation of signals is relieved. Thereby high frequency characteristics can be improved.

Heterodimensional technology for ultra low power electronics

Abstract: We describe new heterodimensional technology suitable for ultra low power applications. This technology uses Schottky barrier contacts between three-dimensional metal and two-dimensional electron gas. The low power performance is due to the following: the small capacitance of the 2D-3D junction; the concentration of the depletion layer electric field streamlines in the active channel; suppression of parasitic resistance; small leakage current; and, most of all, due to the total elimination of the narrow channel effect which allows us to scale the device width to submicron dimensions. We present, compare, and discuss measured and simulated I-V and C-V characteristics for the 2D-3D Schottky diode, 2D MESFET and Schottky Gated 2D-3D RTT.

Minimum parasitic resistance for ultra-thin SOI MOSFET with high-permittivity gate insulator performed by lateral contact structure

Abstract: Since the interconnect capacitance almost maintains the same level even with shrinking device dimension, high current drive of a transistor is required for ultra-high speed operation. Although the ultra-thin SOI MOSFET is a promising candidate for ultra-small devices, its enormous parasitic resistance is a significant problem. The reduction of the parasitic resistance is a key issue in achieving high-performance ultra-thin SOI devices. In this study, a lateral contact structure, unique to SOI devices, with ultra-low contact resistance, is proposed for realizing ultimate low parasitic resistance.

Resin sealed semiconductor element

Abstract: PURPOSE:To reduce the parasitic inductance in an element by connecting a bump electrode directly with the lead frame and setting the width of lead frame and the interpole distance such that the characteristic impedance of the lead frame will be equal to the impedance of an external circuit. CONSTITUTION:Windows are opened in a film at an area 31 where a bump electrode is bonded and an area 32 where a lead frame is bonded. A metallized pattern 21 can be connected electrically with the outside through the window. Since the metallized pattern 21b to be connected with the bump electrode serves as a signal path, it is designed as a coplanar line with the width W2 and the interval (interpole distance) W1 with respect to an adjacent metallized pattern 21a being set to provide an impedance of 50OMEGA. A signal having frequency of quasi-microwave band or above is then introduced through the lead frame to the 50OMEGA signal path, i.e., the metallization.

Output buffer circuit device

Abstract: PURPOSE:To reduce switching noise without sacrificing a data output by connecting plural output transistors(TRs) in parallel and setting a shortest delay time so as to maximize a ground potential rise not regarded to be a noise when each TR is operated. CONSTITUTION:When the output buffer circuit device is in operation, a signal QP is used to apply on/off operation to the device and TRs 3, 4 turn on/off signals QNA, QNB. A high or low level signal is sent from a data output terminal 5 in this way and an inductance of a package or the like is in existence between ground and the system as a parasitic element. The ground potential is changed in this way in response to the change in a switching current of the TRs 3,4. That is, a maximum potential and a minimum potential not discriminated to be a noise are made constant and the conductance and the rising time of the TRs 3, 4 are set to quicken the switching of the signal level at a terminal 5.

Sub-nanohenry inductance measurement using a zero-parasitic-inductance probe system

Abstract: A new inductance measurement method of a sub-nanohenry order is proposed using an LCR meter. Since parasitic inductances of probes usually decreases the measurement accuracy, we developed two types of special probes to minimize such parasitic inductances. The new measurement methods have special merits, such as separate measurements of each trace and a high spatial resolution. They also enable measurements of inductances not only for simple traces, but also for combined trace-and-sheet conductor systems. The results measured proved to be in good agreement with our electro-magnetic simulator. The eddy current effect was successfully demonstrated by using this method.