Showing papers on "Phase detector published in 2000"

An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance

Abstract: This paper describes an all-analog multiphase delay-locked loop (DLL) architecture that achieves both wide-range operation and low-jitter performance. A replica delay line is attached to a conventional DLL to fully utilize the frequency range of the voltage-controlled delay line. The proposed DLL keeps the same benefits of conventional DLLs such as good jitter performance and multiphase clock generation. The DLL incorporates dynamic phase detectors and triply controlled delay cells with cell-level duty-cycle correction capability to generate equally spaced eight-phase clocks. The chip has been fabricated using a 0.35-/spl mu/m CMOS process. The peak-to peak jitter is less than 30 ps over the operating frequency range of 62.5-250 MHz, At 250 MHz, its jitter supply sensitivity is 0.11 ps/mV. It occupies smaller area (0.2 mm/sup 2/) and dissipates less power (42 mW) than other wide-range DLL's [2]-[7].

A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order /spl Delta//spl Sigma/ modulator

Abstract: Fractional-N frequency synthesis based on /spl Delta//spl Sigma/ modulators offers wide bandwidth with narrow channel spacing and alleviates PLL design constraints for phase noise and reference spur. However, the synthesizer phase noise performance is significantly affected by the high-frequency out-of-band noise, which is difficult to suppress with the finite number of PLL loop filter poles. This work uses a 3b 3rd-order modulator that generates less high-frequency noise and makes the system less sensitive to the phase detector nonlinearity.

Fast-switching frequency synthesizer with a discriminator-aided phase detector

Abstract: A phase-locked loop (PLL) with a fast-locked discriminator-aided phase detector (DAPD) is presented. Compared with the conventional phase detector (PD), the proposed fast-locked PD reduces the PLL pull-in time and enhances the switching speed, while maintaining better noise bandwidth. The synthesizer has been implemented in a 0.35-/spl mu/m CMOS process, and the output phase noise is -99 dBc/Hz at 100-kHz offset. Under the supply voltage of 3.3 V, its power consumption is 120 mW.

Two-dimensional phase unwrapping using neural networks

Abstract: Imaging systems that construct an image from phase information in received signals include synthetic aperture radar (SAR) and optical Doppler tomography (ODT) systems. A fundamental problem in the image formation is phase ambiguity, i.e., it is impossible to distinguish between phases that differ by 2/spl pi/. Phase unwrapping in two dimensions essentially consists of detecting the pixel locations of the phase discontinuities, finding an ordering among the pixel locations for unwrapping the phase, and adding offsets of multiples of 2/spl pi/. In this paper, we propose a new method for detecting phase discontinuities. The method is based on a supervised feedforward multilayer perceptron neural network. We train and test the neural network on simulated phase images formed in an ODT system. For the ODT phase images, the new method detects the correct unwrapping locations where some conventional methods fail. The key contribution of the paper is a one-pass pixel-parallel low-complexity method for detecting phase discontinuities.

Digital fractional phase detector

Abstract: A digital fractional phase detector is provided to realize a frequency synthesizer architecture that naturally combines transmitter modulation capability with a wideband all-digital PLL modulation scheme to maximize a digitally-intensive implementation by operating in a synchronous phase domain. Synchronous logic is provided across a digitally controlled VCO and is synchronous to the VCO output clock by implementing a timing adjustment in association with a reference calculation to allow a frequency control word to contain both channel information and transmit modulation information. The digital fractional phase detector is capable of accommodating a quantization scheme to measure fractional delay differences between the significant edge of the VCO output clock and a reference clock by using a time-to-digital converter to express the time difference as a digital word for use by the frequency synthesizer.

Apparatus and method for a fast locking phase locked loop

Abstract: A control circuit for causing a phase lock loop (PLL) frequency synthesizer to achieve a fast phase lock time while also providing improved loop performance during normal phase locked operation. The phase locking time of the PLL is minimized by initially configuring the PLL to operate in a fractional mode with high frequency signals presented to the inputs of the loop phase detector, thereby producing a fast phase lock time. Once the PLL has achieved phase lock, its operation mode is transitioned to either an integer mode or an open loop mode without loss of phase lock, thus causing lower frequency signals or no signals, respectively, to be presented to the inputs of the loop phase detector and thereby significantly reducing spurious signal tones.

SiGe clock and data recovery IC with linear-type PLL for 10-Gb/s SONET application

Abstract: An integrated 10 Gb/s clock and data recovery (CDR) circuit is fabricated using SiGe technology, It consists of a linear-type phase-locked loop (PLL) based on a single-edge version of the Hogge phase detector, a LC-tank voltage-controlled oscillator (VCO) and a tri-state charge pump. A PLL equivalent model and design method to meet SONET jitter requirements are presented. The CDR was tested at 9.529 GB/s in full operation and up to 13.25 Gb/s in data recovery mode. Sensitivity is 14 mV/sub pp/ at a bit error rate (BER)=10/sup -9/. The measured recovered clock jitter is less than 1 ps RMS. The IC dissipates 1.5 W with a -5 V power supply.

Semiconductor device and timing control circuit

Abstract: Control on the speed of operation of a delay loop from the output of a variable delay circuit to a delay control input thereof is performed. For example, frequency-dividing circuits are respectively placed at the input and output of the variable delay circuit. A signal obtained by frequency-dividing a signal outputted from the variable delay circuit is supplied to one input of a phase comparator through a dummy delay circuit, and a signal obtained by frequency-dividing the input of the variable delay circuit is supplied to the other input of the phase comparator. Phase control is performed according to the result of comparison between the phases of both signals.

A phase assisted synchronization detector

Abstract: A synchronization detector including a phase detector and a distance metric calculator. The phase detector uses the preamble readback signal to estimate the bit periods and outputs a signal indicative of this estimate. This signal is sued by the distance metric calculator to limit its search for the synchronization mark to every mth bit position, where m is a predetermined integer greater than one (1).

Semiconductor integrated circuit device

Abstract: PURPOSE: A semiconductor integrated circuit device is provided to prevent an increase of a chip area, and to generate a clock signal, whose phase is exactly biased by 180 De, and an inverted clock signal. CONSTITUTION: A semiconductor integrated circuit device comprises input buffers(20,22)which receive external clock signals(/CLK,CLK) of mutually inverted phases. A phase comparator(44) receives the external clock signal(CLK) from the input buffer(22) and a delayed version of the external clock signal(CLK) through a delay circuit(40), a dummy output buffer(42) and a dummy input buffer(46). The phase comparator(44) compares the phases of the received clock signals to generate a phase difference signal at a rising timing of the clock signal(CLK). A delay control circuit(48) generates an m-bit delay control signal in response to the phase difference signal, and controls a delay amount of a delay circuit(40). A gate circuit(34) receives the delay control signal, and is controlled by a gate control circuit(32). A latch circuit(36) latches the delay control signal from the gate circuit(34), and outputs the latched control signal to a delay circuit(30), whose delay amount is controlled by the delay control signal from the latch circuit(36). An output buffer(50) receives clock signals(CLK,/CLK) of mutually inverted phases delayed by the delay circuits(30,40).

Wide frequency-range delay-locked loop circuit

Abstract: A delay-locked loop (DLL), including frequency detection logic and a phase detector, is described having an operating range as wide as a conventional charge pump phase locked loop. The frequency detector logic counts the number of rising edges of the multi-phase clocks generated from a reference clock during one period of the reference clock. A loop filter is used to adjust the frequency of each multi-phase clock until frequency lock is obtained by comparing the number of rising edges. After frequency lock, phase detection logic is used to finely tune out the remaining phase error.

Memory based phase locked loop

Abstract: A circuit comprising a phase detector/correction circuit, at least one column of memory cells, a control circuit and a sense amplifier. The control circuit may be configured to read a sequence from the memory cells in a predetermined order and present a first output signal. The sense amplifier may be configured to present a periodic signal in response to the first output signal.

Charge pump for low-voltage, low-jitter phase locked loops

Abstract: An integrated circuit has a phase-locked loop (PLL) frequency synthesizer circuit which has a charge pump circuit for providing an output control voltage to adjust an oscillator frequency in response to fast and slow signals provided by a phase detector. The charge pump circuit has first and second current sources, and a switching network for selectively coupling, in response to said fast signal, the first current source to one of an internal node and an output node coupled to an output capacitor and having an output voltage, and, in response to said slow signal, the second current source to one of the internal node and the output node. The charge pump circuit has first and second unity gain buffers coupled in parallel at their inputs to the output node and at their outputs to the internal node, wherein the first buffer is configured to have a voltage tracking range approximately up to a positive supply rail and the second buffer is configured to have a voltage tracking range approximately down to a negative supply rail, wherein the voltage tracking ranges of said buffers overlap each other, to provide an overall substantially rail-to-rail voltage tracking range.

Optoelectronic phase-locked loop with balanced photodetection for clock recovery in high-speed optical time-division-multiplexed systems

Abstract: An optoelectronic phase-locked loop (PLL) for clock recovery in high-speed optical time-division-multiplexed (OTDM) systems is proposed and experimentally demonstrated. The proposed scheme incorporates a pair of balanced photodetector through which the polarity ambiguity in error signal is resolved, and the cancellation of laser noise enables clock recovery with low timing jitter. Using an electroabsorption modulator as a phase detector, a 10-GHz clock signal with root-mean-square (rms) timing jitter of 300 fs is successfully extracted from 40 and 80 Gb/s return-to-zero (RZ) data stream. A 40- to 10-Gb/s demultiplexing is performed by using the recovered clock signal with no penalty introduced in the bit error rate performance.

System and method for an equalizer-based symbol timing loop

Abstract: An equalizer based symbol timing loop system incorporates existing receiver architecture to modify an input sample stream to match a transmitter's symbol rate. The system includes a phase detector that identifies a center tap in a linear equalizer in the receiver and then captures the value of the center tap at the beginning and end of a measurement period. The phase detector then multiples the captured value of the center tap at the end of the measurement period by the conjugate of the captured center tap value at the beginning of the measurement period. The phase detector then takes the arc tangent of the multiplication result. A loop filter coupled to the phase detector multiples the arc tangent result by a scalar and adds the result to a frequency difference estimate. A coefficient generator then determines the interpolation phase for an input sample stream based on the frequency difference estimate and generates interpolator coefficients based on the interpolation phase. A timing interpolator filter coupled to the coefficient generator receives the input sample stream and interpolator coefficients and modifies the input sample stream to match the transmitter's symbol rate.

System and method for detecting and correcting phase error between differential signals

Abstract: A phase error detector that detects phase error between differential signals. A quadrature oscillator provides in-phase (I) and quadrature phase (Q) differential carrier signals and receives a phase error signal from the phase error detector. The oscillator maintains a quarter cycle phase delay between the I and Q carrier signals based on the phase error signal. The phase error detector includes a summing network and first and second bipolar transistor mixer circuits. The summing network develops four sum signals by summing respective pairs of the differential components of the I and Q carrier signals. A bias circuit biases the transistors to turn on at positive base voltages. The mixer circuits may include filter capacitors so that the transistors are responsive to positive base voltages. The mixer circuits develop polarity signals based on the sum signals, and the resulting phase error signal is the differential of the polarity signals.

SiGe BiCMOS 3.3 V clock and data recovery circuits for 10 Gb/s serial transmission systems

Abstract: Two fully monolithic clock and data recovery (CDR) circuits for serial optical fiber links are presented. One CDR is targeting SONET OC-192 application while the other is a possible 10-GigaBit Ethernet application using 8B/10B coded data. The ICs are fabricated in a SiGe BiCMOS technology with a 45-GHz cut-off frequency. The CDRs extract a full rate clock and recover data from a random input bit stream. Each IC integrates a novel self-correcting phase detector, a delay-interpolating ring voltage-controlled oscillator, and a lock-to-reference loop for frequency acquisition. High-speed operation, low time jitter, and large jitter tolerance are the main features of the circuits. Each macro dissipates about 320 mW from 3.3-V supply.

A 1-GHz Portable Digital Delay-Locked Loop with Infinite Phase Capture Ranges

Abstract: Delay-locked loops (DLLs) are widely used to align signal phases in many high-speed microprocessors and memories. Phase-locked loops (PLLs) are also used but their jitter is larger than that of DLLs, because DLLs have no jitter accumulation. However, conventional DLLs have design problems. One is that their phase capture ranges are limited, and another is that a special reset sequence is required. Dual DLL architectures are developed to overcome these problems. In these architectures, the latency from the input to the output, however, is lengthened to attain high resolution, because these architectures require a number of multiplexers between the DLL input and output ports. As a result, supply-noise induced jitter increases. To reduce the jitter, a portable digital DLL uses the following techniques: (1) a master-slave architecture, which achieves infinite phase capture ranges and eliminates the special reset requirement, (2) a wave synchronous latch circuit, which maintains high resolution, and (3) a dynamic phase detector, which improves phase comparison sensitivity.

A self-calibrating 900-MHz CMOS image-reject receiver

Abstract: This paper introduces an analog phase and gain calibration technique for image-reject receivers The technique uniquely detects the phase and gain mismatches and drives their magnitudes toward zero through the use of a negative-feedback loop An experimental CMOS prototype operating at 900 MHz achieves an image rejection ratio of 57 dB by applying phase calibration to a Weaver architecture Fabricated in a 035-µm CMOS technology and running from a 3-V supply, the receiver dissipates 105 mW during the receive mode and 170 mW during the calibration mode

PLL loop filter with switched-capacitor resistor

Abstract: A phase-locked loop circuit having improved phase noise characteristics includes a voltage-controlled oscillator (12) developing an oscillating output signal responsive to a voltage control input. A reference source provides a reference frequency signal. A phase detector (30) is operatively connected to the voltage-controlled oscillator and the reference source developing an output proportional to a phase difference between the oscillating output signal and the reference frequency signal. A loop filter (46) connects the phase detector output to the voltage control input. The loop filter includes a switched-capacitor equivalent resistor (Q1, Q2, CR).

Dual mode phase measurement for optical heterodyne interferometry

Abstract: We present a new digital phase measuring scheme for optical heterodyne interferometry, which provides high measurable velocity up to 6 m s-1 with a fine displacement resolution of 0.1 nm. The main idea is combining two distinctive digital phase measuring techniques with mutually complementary characteristics; one is counting the Doppler shift frequency with a 20 MHz beat frequency for high velocity measurement and the other is synchronous phase demodulation with a 2.0 kHz beat frequency for extremely fine displacement resolution. The two techniques are operated in switching mode in accordance with the object speed in a synchronized way. Experimental results prove that the proposed dual mode phase measuring scheme is realized with a set of relatively simple electronic circuits for beat frequency shifting, heterodyne phase detection and low-pass filtering.

Slip-detecting phase detector and method for improving phase-lock loop lock time

Abstract: An improved digital phase detector is provided for detecting and compensating for a cycle slip between a reference signal and a frequency source signal, the reference and frequency source signals each comprising pulses, each pulse defined by a leading edge and a trailing edge The digital phase detector includes a detector circuit for detecting a cycle slip where two successive leading edges of one of the reference and frequency source signals are received before a leading edge of the other signal is received An output circuit is operatively coupled to the detector circuit for developing a correction signal responsive to said detecting

A 10-Gb/s CMOS clock and data recovery circuit

Abstract: A 10-Gb/s phase-locked clock and data recovery circuit incorporates a 5-GHz interpolating voltage-controlled oscillator and a half-rate phase detector. The phase detector provides a linear characteristic while retiming and demultiplexing the data with no systematic phase offset. Fabricated in a 0.18-/spl mu/m CMOS technology, the circuit exhibits an rms jitter of 6.6 ps in the recovered clock with random data input of length 2/sup 23/-1. The power dissipation is 99 mW from a 2.6-V supply.

Multi-band transceiver having multi-slot capability

Abstract: A multi-band transceiver for receiving and transmitting signals within selected GSM frequency bands. Transmission and reception occurs simultaneously and within the same time slot of a TDMA frame. The transceiver includes a first local oscillator LO1 that selectively oscillates within a bandwidth corresponding to the selected GSM band and outputs a signal having a frequency fLO1. A second local oscillator LO2 selectively oscillates at a frequency corresponding to the selected GSM band and outputs a signal having a frequency fLO2. A receiver receives a signal having a frequency fRx and mixes the signals from the first and second local oscillators to generate a demodulating signal having a frequency fRx, wherein fRx = fLO1 ± fLO2. A transmitter having a loop architecture includes a VCO that generates a signal having a transmit frequency fTx equal to fRx minus a comparison frequency fCF, and a mixer that mixes the signal from the first local oscillator with the transmit signal to generate an IF signal having a frequency fIF = fLO2 ± fCF. A quadrature mixer that modulates the IF signal with baseband 'I' and 'Q' signals, and a phase detector that compares the phases of the IF signal and the signal from the second local oscillator and outputs a control voltage to the VCO.

Magnetic disk drive with servo signal decoder using amplitude detection and phase detection system

Abstract: Disclosed are a method and a device that exhibit better performance against factors inhibiting an increase in track density than the current system. A servo pattern is constituted of a plurality of patterns arranged on both sides of the center lines of tracks, the patterns on one side of the center line being shifted in the track direction from the patterns on the other side along the center line, and patterns A and B are each constituted of two types of phase patterns arranged in the track-width direction, which are patterns 11 and 12 and patterns 13 and 14, respectively. The positional signal of a magnetic head is decoded by determining a sinusoidal function, which roughly agrees with the waveform of the reproduced signal of the servo pattern, based on the information on the frequency of the reproduced signal which has been stored in advance.

Frequency detector and phase-locked loop circuit including the detector

Abstract: A three-state phase detector, including two latches and one NAND gate, is provided with two additional latches. To detect a phase difference between first and second input clock signals R and V, the phase detector alternates among three states responsive to a rising edge of the input R or V signal. Each of the two additional latches and an associated latch in the phase detector together constitute one shift register. When the phase detector gets back to its neutral state, the NAND gate generates a reset signal, thereby resetting all of these four latches. Two isolated pulse generators are further provided. Each of the pulse generators makes the pulse width of a frequency difference pulse signal, output from associated one of the additional latches, constant and then outputs the pulse signal with the constant width.

Ultrafast two-dimensional electron gas detector and mixer for terahertz radiation

Abstract: A hot-electron bolometric detector and mixer (heterodyne detector), which uses the nonlinearities of the heated two-dimensional electron gas medium, is proposed and analyzed. The cooling process of the detector is through diffusion of the electrons into the contacts; a time constant of 1 ps and responsivity of 3000 V/W are calculated for a device which is 0.8 μm long. The predicted double-sideband receiver noise temperature for the mixer version is in the range 1000–2000 K at 1 THz, with a 100 GHz intermediate frequency bandwidth. The operating temperature would be 77 K and the local oscillator power 1 μW.

Oscillator with digitally variable phase for a phase-locked loop

Abstract: The present invention provides an improved method and apparatus for independently controlling phase and frequency using an oscillator having a plurality of stages in combination with a phase selector within a digitally controlled phase-locked loop, preferably, a read phase locked loop. The present invention provides a digitally controlled variable phase of the read timing loop in read channel integrated circuits associated with data storage devices. The phase selector has a digitally controlled fine interpolator with 12 states for further fine interpolation between at least two multiplexer phase outputs to provide a single phase output selected from a range comprising at least 2π in selectable variable phase increments of 2π/96 radian. The combined oscillator with the phase selector within a phase locked loop controls phase by exact fractional increments of equally space phases of the operating frequency within the phase locked loop, therein controlling phase at all operating frequencies.

Apparatus and method for servo-controlled self-centering phase detector

Abstract: Modern fiber optic networks typically transfer data using encoding in which the clock is transmitted along with the data, for example in NRZ format. In order to use the clock to process the data, the clock signal must be extracted from the data signal. Because the data and clock may travel through different circuit paths they may have different propagation delays and a phase offset between the clock and data may result. Data and clock phase offsets are more problematical as data transmission speed increases. Furthermore the data/phase offset is typically not constant and may change with a variety of variables. To compensate for the changing offset, one or more variable delays (1113) are inserted in the phase detector circuitry. The timing of the variable delay is controlled by a bang-bang phase detector (1105), such as an Alexander phase detector, which determines if the clock is leading, lagging, or in phase with the data. The delay control loops are low bandwidth, because the phase offset generally changes slowly, and because the loops should not respond to temporary upsets such as noise spikes. The delay control loops integrate the output of the bang-bang phase detector and use the output to control a decimated up down counter (1113), which is then further used to control one or more variable delays. The counter (1113) can be pre-loaded with a default start point, and the bandwidth of the loops can be dynamically adjusted by changing the decimation ratio and sample periods of the loop.

A 20 Gb/s CMOS multi-channel transmitter and receiver chip set for ultra-high resolution digital display

Abstract: The digital display interface for an ultra-high resolution flat panel (3200/spl times/2400-pixels) requires 16 Gb/s bandwidth; moreover, 20 Gb/s is required when using an 8B10B encoder to increase serial data transmission accuracy. Low power consumption and low cost are also essential for consumer applications. These requirements are supported by multi-channel transmission, such as four 5 Gb/s CMOS LSIs, which is an effective approach to achieving an aggregate bandwidth of 20 Gb/s. There are two system problems in developing a multi-channel transmitter (TX) and receiver (RX) LSIs. One is the phase difference between multiple chips due to the data skew caused by differences between transmission cable lengths. The other is the frequency difference between the TX and RX system clocks. In response to these problems, we have developed compensation technology featuring the use of an elastic buffer for both the phase and frequency differences. Moreover, to achieve 6 Gb/s operation, a self-alignment phase detector with parallel output for a high-speed clock and data recovery circuit (CDR) and a 500 MHz fully pipelined 8B10B encoder are developed.