Showing papers on "Sequential logic published in 1974"

MINI: a heuristic approach for logic minimization

Abstract: MINI is a heuristic logic minimization technique for many-variable problems. It accepts as input a Boolean logic specification expressed as an input-output table, thus avoiding a long list of minterms. It seeks a minimal implicant solution, without generating all prime implicants, which can be converted to prime implicants if desired. New and effective subprocesses, such as expanding, reshaping, and removing redundancy from cubes, are iterated until there is no further reduction in the solution. The process is general in that it can minimize both conventional logic and logic functions of multi-valued variables.

Testing embedded arrays

Abstract: An LSI semiconductor device includes a memory array incorporating address and data registers, and associated combinatorial and or sequential logic circuitry. The array is "embedded" in the sense that the memory array is not directly accessible, either in whole or in part, from the input and output terminals or pads of the device. To facilitate testing, the address registers and data registers are converted to counters by the addition of an EXCLUSIVE OR circuit to two or more positions of the register. The address and data registers are stepped through all of their states. The data register counter outputs may then be compared with the array outputs, thereby allowing one to check address selection as well as the ability to write or read at each of the storage locations.

Testing embedded arrays

Abstract: An LSI semiconductor device includes a memory array incorporating address, data and buffer registers, and associated combinatorial and/or sequential logic circuitry. The array is "embedded" in the sense that the memory array is not directly accessible, either in whole or in part, from the input and output terminals or pads of the device. To facilitate testing, means which bypass the associated logic circuitry are provided for scanning information directly into the address and data registers. The information so introduced is shifted through the register strings. The interconnections from the associated logic circuitry are inhibited during the testing mode while the information shifting means are inhibited during an operative mode. The information scanned into the registers may be scanned out to determine whether there is a defect or problem in the register strings. Output levels from the array are compared with an expected output.

Logic network test system with simulator oriented fault test generator

Abstract: Disclosed is a technique for testing highly complex, functional logic where long sequences of test patterns are needed. A logic network to be tested comprises a large number of logic blocks. The inputs to several of these logic blocks are also the primary inputs (PI) to the logic network to be tested while the output of several of the logic blocks are also outputs (PO) of the logic network to be tested. However, the inputs and outputs of many logic blocks of the network to be tested are inaccessible since as is well known in large scale integration (LSI), a large number of internal circuit nodes cannot be probed directly. In accordance with the present disclosure, such a logic network to be tested is simulated and each of the logic blocks as well as the inputs and outputs of each of these logic blocks is uniquely defined. A first test pattern is then applied to the primary inputs (PI) of the network to set the logic levels on these primary inputs to known values. A particular one of the logic blocks within the network is then selected and a specific fault associated with the particular logic block is assumed. A test value for this assumed specific fault in the simulated network is then propagated towards a primary output, one logic stage at a time, by backtracing through the network to a primary input to determine which primary input value must be altered in order to propagate the assumed fault towards a primary output. Without developing an entire test sequence, analysis at each step determines whether the test is in fact progressing by propagating the test value through the network toward the primary input. The term "test value" is defined as the binary vaue of a point within the logic network that is opposite from that expected in the absence of the assumed fault. When a "test value" has been successfully propagated to a primary output (PO), then it is known that the particular sequence of input test patterns is suitable for detecting the specific fault assumed in the simulator. By applying the same sequence of test patterns to the actual network under test and comparing the primary outputs of the network under test and primary outputs of the simulated network, it is determined whether the particular assumed simulated fault is actually present in the network under test. On a real time basis, each time a successive pattern is applied to the simulated network, it is analyzed, and if found unsuitable, it is discarded and a different changed input pattern is sought by backtracing to a primary input through a different path. Each successive pattern is applied to the network under test only if found to be valid.

Equivalence of memory to Random Logic

Abstract: A model of the design process for computer logic is used to estimate the number of bits of memory required to replace a so-called "random logic" circuit. The model can also be used to compare the respective time delays of array logic and random logic.

On Minimally Testable Logic Networks

Abstract: A new technique to modify any logic network to facilitate diagnosis is given. By providing extra controllable inputs (at most six) and observable outputs it is shown that any number of stuck-at-faults in a logic network can be detected by applying only three tests. This number is believed to be minimal for networks using current technologies. Example of logic module that can be used to realize any logic function such that only two tests detect stuck-at-faults is also given.

Procedures for Eliminating Static and Dynamic Hazards in Test Generation

Abstract: One problem associated with test generation algorithms for sequential circuits is that they often produce tests which, when applied to the circuit under test, create static and/or dynamic hazards which may invalidate the test. Usually, for static hazards, but not dynamic hazards, these situations can be predicted using a logic simulator. In this paper we present procedures which can be added to path sensitization test generation algorithms so that the resulting procedure will not produce tests which will be invalidated due to hazards. Incidental to this work is a new simulation technique for handling both static and dynamic hazards. The principal concepts behind this work deal with detecting when hazards are created in a circuit; propagating hazard status information related to a signal line through a circuit; detecting those conditions at flip-flop inputs which necessitate hazard free conditions; and finally, selecting test inputs so that all hazard free conditions are satisfied.

Time split array logic element and method of operation

Abstract: A standard logic array can be electrically altered at different time intervals to execute complex logic functions. Input variables to the array are processed in a network to generate sets of implicants of a complex function in one or more time periods. The implicants constituting the function are processed through a logic network or matrix as the logic personality of the matrix is altered. The implicant and logic networks may be personalized by (a) structure, (b) time signals, (c) personality signals, and (d) any combination of (a), (b) and (c). The standard array executes complex functions in a single time period or by processing one or more implicants in groups at different time periods. The testability of the array may be improved by appropriate interconnections of the array elements. The invention reduces the number of logic elements or part numbers a system designer must assemble to achieve desired objectives for a data processing machine. The arrays can be produced, stockpiled and structurally personalized at a later time as required by a system designer. The method of operating the array is compatible with data processing machine programming and operation.

Self-Synchronized Asynchronous Sequential Machines

Abstract: In this correspondence, a new circuit structure is proposed which basically supresses the possibility of hazards and critical races in asynchronous sequential machines. In contrast to many approaches which try to solve these problems by changing the form of the automaton model, we suggest a more general "hardware" solution. This configuration provides performance extremely close to that of classical circuits while allowing substantial reduction in circuit cost.

On-Set Realization of Fail-Safe Sequential Machines

Abstract: Fail-safe sequential machines can be constructed in such a way that if a failure happens in the sequential part, the ulterior functioning must carry on outside the code chosen to represent the set of states. This paper presents a study of the failures in the input combinational circuit and of the feasibility conditions of sequential machines with states coded by a k-out-of-n code. The electronic circuit is realized in a classical way (on-set realization) and must obey two hypotheses, 1) no failure on clock line C, and 2) single fault (stuck at 0 or stuck at 1) on other connections than C.

Magnetic bubble logic

Abstract: Although the literature on the bubble logic devices is limited, the concepts and device configurations are diverse. In conductor-access devices, logic can be performed by bubble transfer operations. In field-access devices, logic can be performed by providing alternative paths which are selected by interaction between bubbles. Examples include the conjugate logic gates, the resident-bubble cellular logic, and the chevron 3-3 circuits. Logic can also be performed by counting bubbles, such as in the symmetric switching function implementation. The various mechanisms for implementing bubble logic are all described by truth tables. To assess their efficiency, they are compared in terms of space and delay when they are used to implement the same logic element - a full adder. They are all comparable except for the resident-bubble cellular logic which requires excessive space and delay. However, it is important to point out that only the symmetric switching function devices offer rewrite-ability to eliminate the part number problem, and accommodation for a large number of inputs to ease interconnection and delay equalization problems.

Moving-average output interface for digital stochastic computers

Abstract: A new logic circuit suitable for use as an output interface for digital stochastic computers is presented. The logic element is based on the theory of moving averages, and is demonstrated to provide a significant improvement in transient-response characteristics, without loss in accuracy.

Lamp: Automatic test generation for asynchronous digital circuits

Abstract: An automatic test generation system has been developed to detect faults in combinational and sequential circuits. The circuit model treats logic circuits as interconnections of unit- and zero-time-delay gates. A series of time-dependent Boolean equations are derived from the logic network (starting from the network inputs) in terms of sequences of signals (input vectors) on the circuit input leads. These equations account for the effect of specific circuit faults. Many tests, each consisting of a sequence of input signals (input vectors), are needed to detect all single faults in a circuit. Tests are generated from the time-dependent equations using two different strategies: (i) a maximum-cover approach to detect a large number of faults quickly by generating tests for the faults on the circuit-input leads. The fault-detection level achieved by the maximum-cover tests is then evaluated using fault simulation; (ii) tests for individual faults not detected by the maximum-cover approach. ATG has been implemented on the IBM 360, Model 67, and IBM 370, Model 168, computers.

Analysis of d.c. chopper circuits by computer-based piecewise-linear technique

Abstract: A computer-based method for analysing the performance of d.c. chopper circuits is proposed. In the paper, a piecewise-linear description is established by considering sequential circuit modes, defined by the switching action of thyristors and diodes. The method is quite general, and could be applied to any particular chopper circuit to provide both transient and steady-state performance data. As an illustration, the method is used to describe the performance of a d.c. series motor controlled by a chopper circuit that provides both armature and field control. Control characteristics of this circuit are established, and these are compared with practical results obtained by measurement on a 220 V, 8 A series motor.

Fault-Tolerant Asynchronous Sequential Machines

Abstract: A general design technique for achieving single fault-tolerant asynchronous sequential circuits is described. The design procedures apply over a large range of fault conditions and are extremely easy to use. Generally, less than three times the logic required for a single copy is needed to achieve single fault tolerance. In addition to fault tolerance, real time fault detection is easily achieved and it is immediately known when single fault tolerant capability is exceeded.

An integrated m-out-of-n detection circuit using threshold logic

Abstract: The design of the integrated 4-out-of-9 detector is based on a threshold logic approach. A differential current-switching circuit configuration is used, and the detector is fully compatible with conventional emitter-coupled logic (ECL). The circuit has a propagation delay of 16 ns and dissipates only 100 mW. The functional power-delay product of 1600 pJ is an order of magnitude below that achieved with an efficient gate design.

Application of fuzzy logic to the detection of static hazards in combinational switching systems

Abstract: In this paper the fuzzy set as discussed by Zadeh is viewed as a multivalued logic with a continuum of truth values in the interval [0,1]. The concept of static hazard in combinational switching systems is related to fuzzy logic and various properties of this relation are established. The paper derives the necessary and sufficient conditions for a fuzzy function to adequately describe the steady-state and static hazard behavior of a combinational system, by extending the ternary method discussed by Yoeli and Rinon and using the resolution principle of mechanical theorem-proving.

Serial programmable combinational switching function generator

Abstract: A device for performing logic operations in which a Boolean equation to be solved is serially processed in a manner which results in a large reduction in the number of building blocks required while still allowing the solution of long logic equations.

Digital logical sequence controller

Abstract: A sequence controller of the digital logical circuit type, comprising a sequence program part and a processing circuit, wherein the desired sequence instruction is read from the sequence program part, and the sequence is processed and controlled by the processing circuit. A certain definite level is set at a branch point in an equivalent sequential circuit according to the path along which a signal of the sequential circuit is transmitted. This level and the on-off state of the branch point are stored in a memory. The given data are processed and controlled through the sequence program part and the memory.

Generation of Internal State Assignments for Large Asynchronous Sequential Machines

Abstract: Several algorithms have been proposed for generating satisfactory state assignments for normal fundamental mode asynchronous sequential circuits Programmed versions of minimal and near-minimal techniques have been incorporated in automated synthesis systems, but are known to require computational efforts which increase exponentially with flow table size Other methods, requiring much less effort, produce assignments with far more state variables than minimal assigments

Two-phase MOS synchronizer

Abstract: An MOS circuit synchronizes an asynchronous input signal to first and second alternating clock pulses in an integrated circuit system employing clocked ratio logic. A bistable device, such as a flip-flop, has first and second complementary inputs for establishing the state of the device and an output reflecting the state of the device. An input circuit for the bistable device receives the asynchronous signal and applies the signal to the first complementary input and the inverted asynchronous signal to the second complementary input. In addition, the input circuit has gate logic, implemented with field effect transistors, which decouples the asynchronous input for all intervals of time except during the interval of the first clock pulse. An output circuit for the bistable device employs an inverter in series with a field effect transistor which is driven into condition only during the interval of the second clock pulse. The MOS synchronizer circuit thus insures that an output signal of usable logic level is generated for an input signal occuring at any time with respect to the clock pulses of a clocked ratio MOS system.

Fail-safe logic circuitry for vehicle transportation control

Abstract: Logic circuitry in a vehicle transportation system, such logic circuitry providing fail-safe operation utilizing solid-state circuits. The logic circuitry is described relative to control of a highway crossing indicator, such circuitry selectively producing a most restrictive output signal or a least restrictive output signal in accordance with traffic conditions to the crossing indicator. A vital signal is generated that is characteristically differentiated from other signals in the circuit. The vital signal is serially transferred through gate circuits by corresponding enable signals to each gate circuit. When and only when the vital signal has been transferred along a path of gate circuits and through the logic circuitry, the crossing indicator assumes a least restrictive mode of operation.

A Method for the Realization of Fail-Safe Asynchronous Sequential Circuits

Abstract: The problem of the realization of fail-safe asynchronous sequential circuits was recently studied by Patterson and Sawin. This correspondence presents a different approach to the same subject which, in some cases, yield us simpler realization than those by the methods ever proposed, combining the notion of the ordered partition with Tracey's method for the state assignment of asynchronous sequential circuit.

A charge-transfer-device logic cell

Abstract: A logic scheme capable of performing AND-OR logic functions using charge-transfer devices is presented in this paper. Applications of the logic cell are discussed. A half-adder, a ‘flip-flop’, a majority logic gate, an analog-to-digital and a digital-to-analog converter are obtained by extending or modifying the basic scheme. An integrated MOS BBD realization of the AND-OR logic cell is described in detail. Experimental results are presented and shown to be in agreement with theoretical calculations.

Nonuniform translation between analog and digital signals by a piece-wise linear process

Abstract: A weighted resistance network under control of combinational and sequential logic circuits provides a separate reference voltage at each of the digit times of the pulse code for comparison with an amplitude sample at the coder input. The difference voltage is used to derive the pulse code which is compressed in a piece-wise manner because of the use of a weighted resistance network. A decoder operates in a similar manner to produce a quantized output from a weighted network under control of a logic circuit responsive to the incoming uniform pulse code.

Design Technique of Fail-Safe Sequential Circuits Using Flip-Flops For Internal Memory

Abstract: A method for the realization of fail-safe sequential circuits is presented where flip-flops are employed for representing the internal states. First, such a design technique where the circuit will be trapped in an erroneous state into which it is transferred by a fault is shown. Further, the condition for assuring that the circuit will be dropped into the particular (predetermined) final state when a fault exists is described. Finally, some extensions of the technique are attempted.

Combination output/input logic for integrated circuit

Abstract: Method and circuit for both outputting and inputting data by way of a single pin connector for an integrated circuit chip is disclosed. Data from the chip is fed through an output buffer on the chip and a standard pin connector to external circuitry. The input and the output of the output buffer are connected to separate logic inputs of a comparator such as an EXCLUSIVE OR gate. For data output, the external circuitry allows the output buffer to follow the input of the buffer, in which case the output of the EXCLUSIVE OR gate is a logic 0. However, when the external circuitry overrides the output of the output buffer causing the output to be different from the input to the buffer, the output of the EXCLUSIVE OR gate produces a logic 1 signal which indicates that data is being input and that the data at the pin connector is valid input data.

Coded counting sequence and logic implementation thereof to drive a display pattern

Abstract: An integrated circuit is disclosed providing the logic to generate a unique binary coded numerical counting sequence and a corresponding decoded segment select sequence to subsequently activate particular segments comprising a display pattern at predetermined times. A minimum number of logic input terms and respective logic gates are required to implement the instant sequence to thereby reduce the space consumed by the circuit and the cost thereof.

Four-by-four bit multiplier module having three stages of logic cells

Abstract: This invention is a logic design defining the interconnection of logic cells such as those Universal Logic Gates to implement either a 1''s complement (all positive) or a 2''s complement 4 X 4-bit binary multiplier. This multiplier generates the binary product of any two 4-bit binary numbers such that the input signals propagate serially through at most only three logic gating (cell) stages. An extension of the multiplier''s basic logic partition scheme permits design of larger multipliers in which adders and 4 X 4bit multipliers are used as building blocks. A detailed 8 X 8bit multiplier design is presented to concretely describe the approach. The ''''2''s-complement'''' 4 X 4-bit multiplier''s logic partition is almost identical to the one used in the (all positive) 4 X 4-bit multiplier design, incorporating subfunctions which are nearly all identical to their counterparts in the (all positive) multiplier.

Logic circuit fault detector

Abstract: One known technique for testing a digital logic circuit assembly counts the logic level transitions at output and/or test point terminals while exercising the assembly with a fixed set of Gray code related input voltages. Many faulty assemblies are detected by the production of unexpected counts. The present disclosure teaches the addition of ONEs counting to improve the rate at which faulty assemblies are detected.