Showing papers on "Sequential logic published in 2014"

Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies

Abstract: Memristors are novel devices, useful as memory at all hierarchies. These devices can also behave as logic circuits. In this paper, the IMPLY logic gate, a memristor-based logic circuit, is described. In this memristive logic family, each memristor is used as an input, output, computational logic element, and latch in different stages of the computing process. The logical state is determined by the resistance of the memristor. This logic family can be integrated within a memristor-based crossbar, commonly used for memory. In this paper, a methodology for designing this logic family is proposed. The design methodology is based on a general design flow, suitable for all deterministic memristive logic families, and includes some additional design constraints to support the IMPLY logic family. An IMPLY 8-bit full adder based on this design methodology is presented as a case study.

ASLAN: synthesis of approximate sequential circuits

Abstract: Many applications produce acceptable results when their underlying computations are executed in an approximate manner. For such applications, approximate circuits enable hardware implementations that exhibit improved efficiency for a given quality. Previous efforts have largely focused on the design of approximate combinational logic blocks such as adders and multipliers. In practice, however, designers are concerned with the quality of outputs generated by a sequential circuit after several cycles of computation, rather than an embedded combinational block.We propose ASLAN (Automatic methodology for Sequential Logic ApproximatioN), the first effort towards the synthesis of approximate sequential circuits. Given a sequential circuit and an output quality constraint, ASLAN creates an approximate version of the circuit that consumes lower energy, while meeting the specified quality bound. The key challenges in approximating sequential circuits are (i) to model how errors due to approximations are generated, re-circulate through the combinational logic over multiple cycles of operation, and eventually impact quality of the final output, and (ii) to select the most beneficial approximations, i.e., those that result in higher energy savings for smaller impact on quality. ASLAN addresses the first challenge by constructing a virtual Sequential Quality Constraint Circuit (SQCC) and utilizing formal verification techniques to ensure that the selected approximations meet the quality constraint. To address the second challenge, ASLAN identifies combinational blocks in the sequential circuit that are amenable to approximation, generates local quality-energy trade-off curves for them, and uses a gradient-descent approach to iteratively approximate the entire sequential circuit.We used ASLAN to automatically synthesize approximate versions of ten sequential benchmarks, resulting in energy reductions of 1.20X-2.44X for tight quality constraints, and 1.32X-4.42X for moderate quality constraints. We present case studies of using the approximate circuits generated by ASLAN in two popular applications --- MPEG Encoding and K-Means Clustering --- obtaining 1.32X energy savings with 0.5% PSNR degradation, and 1.26X energy savings with 0.8% increase in mean cluster radius, respectively.

Temporal logic inference for classification and prediction from data

Abstract: This paper presents an inference algorithm that can discover temporal logic properties of a system from data. Our algorithm operates on finite time system trajectories that are labeled according to whether or not they demonstrate some desirable system properties (e.g. "the car successfully stops before hitting an obstruction"). A temporal logic formula that can discriminate between the desirable behaviors and the undesirable ones is constructed. The formulae also indicate possible causes for each set of behaviors (e.g. "If the speed of the car is greater than 15 m/s within 0.5s of brake application, the obstruction will be struck") which can be used to tune designs or to perform on-line monitoring to ensure the desired behavior. We introduce reactive parameter signal temporal logic (rPSTL), a fragment of parameter signal temporal logic (PSTL) that is expressive enough to capture causal, spatial, and temporal relationships in data. We define a partial order over the set of rPSTL formulae that is based on language inclusion. This order enables a directed search over this set, i.e. given a candidate rPSTL formula that does not adequately match the observed data, we can automatically construct a formula that will fit the data at least as well. Two case studies, one involving a cattle herding scenario and one involving a stochastic hybrid gene circuit model, are presented to illustrate our approach.

Sequential Logic Operations with a Molecular Keypad Lock with Four Inputs and Dual Fluorescence Outputs

Abstract: A novel coumarin-rhodamine conjugate was prepared, and its metal binding properties were studied by UV/Vis and fluorescence spectroscopy. The conjugate serves as a ratiometric and highly selective fluorescent sensor for Hg(2+) ions. Its metal-responsive spectral properties were utilized to construct a molecular keypad lock with four inputs and dual fluorescence outputs. The complexity of this molecular logic network can greatly enhance the security level of this device.

Race logic: a hardware acceleration for dynamic programming algorithms

Abstract: We propose a novel computing approach, dubbed "Race Logic", in which information, instead of being represented as logic levels, as is done in conventional logic, is represented as a timing delay. Under this new information representation, computations can be performed by observing the relative propagation times of signals injected into the circuit (i.e. the outcome of races). Race Logic is especially suited for solving problems related to the

Designing Trusted Embedded Systems from Finite State Machines

Abstract: Sequential components are crucial for a real-time embedded system as they control the system based on the system's current state and real life input. In this article, we explore the security and trust issues of sequential system design from the perspective of a finite state machine (FSM), which is the most popular model used to describe sequential systems. Specifically, we find that the traditional FSM synthesis procedure will introduce security risks and cannot guarantee trustworthiness in the implemented circuits. Indeed, we show that not only do there exist simple and effective ways to attack a sequential system, it is also possible to insert a hardware Trojan Horse into the design without introducing any significant design overhead. We then formally define the notion of trust in FSM and propose a novel approach to designing trusted circuits from the FSM specification. We demonstrate both our findings on the security threats and the effectiveness of our proposed method on Microelectronics Center of North Carolina (MCNC) sequential circuit benchmarks.

Realizing logic gates with time-delayed synthetic genetic networks

Abstract: We demonstrate the realization of fundamental logic operations, as well as a memory element, with engineered delayed synthetic gene networks. Further, we investigate the effect of time delay in different kinds of processes, on the operational range of this biological logic gate. We show that this delay can either enhance or diminish logic behavior, depending on its functional form. Lastly, we show that the desired response to inputs can be induced, even in the absence of noise, by time delay alone.

27.8 A static contention-free single-phase-clocked 24T flip-flop in 45nm for low-power applications

Abstract: Near-threshold computing (NTC) is an attractive solution to stagnating energy efficiencies in digital integrated circuits, arising from slowed voltage scaling in nanometer CMOS [1-2]. The design of sequential elements for NTC, as well as in voltage-scaled systems operating at both near-threshold and super-threshold, has not been extensively studied. However, it is well known that sequential elements have a strong sensitivity to process variations in NTC [2], which can have a significant impact on system yield and power consumption. In order to achieve reliable energy-efficient operation across a wide operating voltage range, a flip-flop should have the following attributes: 1) static operation, since dynamic nodes are highly susceptible to PVT variations at low voltage; 2) contention-free transitions, since ratioed logic has poor robustness across the wide range of device ION/IOFF ratios incurred with voltage scaling; 3) single-phase clocking, which avoids toggling of internal clock inverters and the corresponding power penalty; 4) minimum or no area penalty compared to conventional flip-flops.

General structure for computational random access memory (CRAM)

Abstract: A cell array includes a logic connection line, a plurality of bit selection lines, and a plurality of cells. Each cell includes a memory element connected to a respective bit selection line and a logic switching element that selectively connects the memory element to the logic connection line. When logic switching elements of multiple separate cells connect their respective memory elements to the logic connection line, the memory elements connected to the logic connection line operate as a logic device with an output of the logic device stored in one of the memory elements.

Boolean Logic Gates From A Single Memristor Via Low-Level Sequential Logic

Abstract: By using the memristor's memory to both store a bit and perform an operation with a second input bit, simple Boolean logic gates have been built with a single memristor. The operation makes use of the interaction of current spikes (occasionally called current transients) found in both memristors and other devices. The sequential time-based logic methodology allows two logical input bits to be used on a one-port by sending the bits separated in time. The resulting logic gate is faster than one relying on memristor's state switching, low power and requires only one memristor. We experimentally demonstrate working OR and XOR gates made with a single flexible Titanium dioxide sol-gel memristor.

Synthesis of Dual-Rail Adiabatic Logic for Low Power Security Applications

Abstract: Programmable reversible logic is emerging as a prospective logic design style for implementation in low power, low frequency applications where minimal impact on circuit heat generation is desirable, such as mitigation of differential power analysis attacks. Adiabatic logic is an implementation of reversible logic in CMOS where the current flow through the circuit is controlled such that the energy dissipation due to switching and capacitor dissipation is minimized. Recent advances in dual-rail adiabatic logic show reduction in average and differential power, making this design methodology advantageous in applications where security is the primary design metric and operating frequency is slower, such as Smart Cards. In this paper, we present an algorithm for synthesis of adiabatic circuits in CMOS. Then, using the ESPRESSO heuristic for minimization of Boolean functions method on each output node, we reduce the size of the synthesized circuit. Our approach correlates the horizontal offsets in the permutation matrix with the necessary switches required for synthesis instead of using a library of equivalent functions. The synthesis results show that, on average, the proposed algorithm represents an improvement of 36% over the best known reversible designs with the optimized dual-rail cell libraries. Then, we present an adiabatic S-box which significantly reduces energy imbalance compared to previous benchmarks. The design is capable of forward encryption and reverse decryption with minimal overhead, allowing for efficient hardware reuse.

Slime mould logic gates based on frequency changes of electrical potential oscillation.

Abstract: Physarum polycephalum is a large single amoeba cell, which in its plasmodial phase, forages and connects nearby food sources with protoplasmic tubes. The organism forages for food by growing these tubes towards detected foodstuff, this foraging behaviour is governed by simple rules of photoavoidance and chemotaxis. The electrical activity of the tubes oscillates, creating a peristaltic like action within the tubes, forcing cytoplasm along the lumen; the frequency of this oscillation controls the speed and direction of growth. External stimuli such as light and food cause changes in the oscillation frequency. We demonstrate that using these stimuli as logical inputs we can approximate logic gates using these tubes and derive combinational logic circuits by cascading the gates, with software analysis providing the output of each gate and determining the input of the following gate. Basic gates OR, AND and NOT were correct 90%, 77.8% and 91.7% of the time respectively. Derived logic circuits XOR, half adder and full adder were 70.8%, 65% and 58.8% accurate respectively. Accuracy of the combinational logic decreases as the number of gates is increased, however they are at least as accurate as previous logic approximations using spatial growth of P. polycephalum and up to 30 times as fast at computing the logical output. The results shown here demonstrate a significant advancement in organism-based computing, providing a solid basis for hybrid computers of the future.

Boolean Computation Using Self-Sustaining Nonlinear Oscillators

Abstract: Self-sustaining nonlinear oscillators of practically any type can function as latches and registers if Boolean logic states are represented physically as the phase of oscillatory signals. Combinational operations on such phase-encoded logic signals can be implemented using arithmetic negation and addition followed by amplitude limiting. With these, general-purpose Boolean computation using a wide variety of natural and engineered oscillators becomes potentially possible. Such phase-encoded logic shows promise for energy efficient computing. It also has inherent noise immunity advantages over traditional level-based logic.

Resistive Threshold Logic

Abstract: We report a resistance-based threshold logic family useful for mimicking brain-like large variable logic functions in VLSI. A universal boolean logic cell based on an analog resistive divider and threshold logic circuit is presented. The resistive divider is implemented using memristors, and provides output voltage as a summation of weighted product of input voltages. The output of the resistive divider is converted into a binary value by a threshold operation implemented by CMOS inverter and/or Opamp. A universal cell structure is presented to decrease the overall implementation complexity and number of components. When the number of input variables becomes very high, the proposed cell offers advantages of smaller area and design simplicity in comparison with CMOS-based logic circuits.

Efficient realization of digital logic circuit using QCA multiplexer

Abstract: Quantum-dot cellular Automata (QCA), a viable alternative to current CMOS, is gaining its prominence in digital circuit due to its very high device density and clocking speed. This work targets design of efficient logic circuits based on QCA multiplexer. The design capability of the multiplexer in QCA is investigated implementing XOR, XNOR logic gate and arithmetic logic unit. Further, efficient sequential circuits like D latch, T latch, D flip-flop, Scan flip-flop, shift registers are designed using QCA multiplexer. Results obtained supports the fact that the proposed designs achieve significant improvement in terms of device density, cell count as well as clock delay than that of the other previous designs.

All-optical half-adder/half-subtractor using terahertz optical asymmetric demultiplexer.

Abstract: Logic gates are the fundamental building blocks of digital systems. Using these logic gates, one can perform different logic and arithmetic operations. All-optical logic and arithmetic operations are very much expected in high-speed communication systems. In this paper, we present a model to perform addition/subtraction operations on two binary digits based on a terahertz optical asymmetric demultiplexer (TOAD). Using four TOAD-based switches, we have designed a half-adder and half-subtractor circuit. The approach to designing all-optical arithmetic circuits not only enhances the computational speed but is also capable of synthesizing light as inputs to produce the desired outputs. The main advantages of this circuit are that synchronization between inputs is eliminated and simultaneous addition and subtraction operations are realized at the outputs. This circuit is designed theoretically and verified through numerical simulations. The impact of the control pulse energy, gain recovery time, and the input data pulse width on the extinction ratio, contrast ratio, amplitude modulation, Q-factor, and relative opening of the pseudo-eye diagram of the switching outcome is explored and assessed by means of numerical simulations.

A High-Throughput Energy-Efficient Implementation of Successive-Cancellation Decoder for Polar Codes Using Combinational Logic

Abstract: This paper proposes a high-throughput energy-efficient Successive Cancellation (SC) decoder architecture for polar codes based on combinational logic. The proposed combinational architecture operates at relatively low clock frequencies compared to sequential circuits, but takes advantage of the high degree of parallelism inherent in such architectures to provide a favorable tradeoff between throughput and energy efficiency at short to medium block lengths. At longer block lengths, the paper proposes a hybrid-logic SC decoder that combines the advantageous aspects of the combinational decoder with the low-complexity nature of sequential-logic decoders. Performance characteristics on ASIC and FPGA are presented with a detailed power consumption analysis for combinational decoders. Finally, the paper presents an analysis of the complexity and delay of combinational decoders, and of the throughput gains obtained by hybrid-logic decoders with respect to purely synchronous architectures.

Design of Reversible Synchronous Sequential Circuits Using Pseudo Reed-Muller Expressions

Abstract: Reversible logic has become very promising for low-power design using emerging computing technologies. A number of good works have been reported on reversible combinational circuit design. However, only a few works reported on the design of reversible latches and flip-flops on the top of reversible combinational gates and suggested that sequential circuits be built by replacing the latches and flip-flops and associated combinational gates of the traditional irreversible designs by their reversible counter parts. This replacement technique is not very promising, because it leads to high quantum cost and garbage outputs. In this paper, we propose a novel approach of designing synchronous sequential circuits directly from reversible gates using pseudo Reed-Muller expressions representing the state transition and the output functions of the circuit. We present designs of arbitrary synchronous sequential circuit as well as practically important sequential circuits such as counters and registers. It is found that our direct designs save 1.54%-49.09% quantum cost and 51.43%-81.82% garbage outputs than the replacement design approach suggested earlier.

An effective approach to automatic functional processor test generation for small-delay faults

Abstract: Functional microprocessor test methods provide several advantages compared to DFT approaches, like reduced chip cost and at-speed execution. However, the automatic generation of functional test patterns is an open issue. In this work we present an approach for the automatic generation of functional microprocessor test sequences for small-delay faults based on Bounded Model Checking. We utilize an ATPG framework for small-delay faults in sequential, non-scan circuits and propose a method for constraining the input space for generating functional test sequences (i.e., test programs). We verify our approach by evaluating the miniMIPS microprocessor. In our experiments we were able to reach over 97 % fault efficiency. To the best of our knowledge, this is the first fully automated approach to functional microprocessor test for small-delay faults.

Synthesizing genetic sequential logic circuit with clock pulse generator

Abstract: Rhythmic clock widely occurs in biological systems which controls several aspects of cell physiology. For the different cell types, it is supplied with various rhythmic frequencies. How to synthesize a specific clock signal is a preliminary but a necessary step to further development of a biological computer in the future. This paper presents a genetic sequential logic circuit with a clock pulse generator based on a synthesized genetic oscillator, which generates a consecutive clock signal whose frequency is an inverse integer multiple to that of the genetic oscillator. An analogous electronic waveform-shaping circuit is constructed by a series of genetic buffers to shape logic high/low levels of an oscillation input in a basic sinusoidal cycle and generate a pulse-width-modulated (PWM) output with various duty cycles. By controlling the threshold level of the genetic buffer, a genetic clock pulse signal with its frequency consistent to the genetic oscillator is synthesized. A synchronous genetic counter circuit based on the topology of the digital sequential logic circuit is triggered by the clock pulse to synthesize the clock signal with an inverse multiple frequency to the genetic oscillator. The function acts like a frequency divider in electronic circuits which plays a key role in the sequential logic circuit with specific operational frequency. A cascaded genetic logic circuit generating clock pulse signals is proposed. Based on analogous implement of digital sequential logic circuits, genetic sequential logic circuits can be constructed by the proposed approach to generate various clock signals from an oscillation signal.

A Chaos-Based Arithmetic Logic Unit and Implications for Obfuscation

Abstract: It is no secret that modern computer systems are vulnerable to threats such as side-channel attack or reverse engineering whereby sensitive data or code could be unintentionally leaked to an adversary. It is the premise of this work that the mitigation of such security threats can be achieved by leveraging the inherent complexity of emerging chaos-based computing (computer systems built from chaotic oscillators). More specifically, this paper considers a chaos-based arithmetic logic unit which consists of many unique implementations for each possible operation. Generalizing to a chaos-based computer, a large number of implementations per operation can enable the obfuscation of critical code or data. In such a system, any two functionally equivalent operations are unique in terms of control parameters, power profiles, and so on. Furthermore, many possible implementations for each operational code can be leveraged to compile a program that is uniquely defined in terms of what the user knows -- such knowledge which itself could be protected via encryption. The frequencies of the various operations are shown to approach that of a probabilistic system as the circuit is allowed to evolve in time. Further, the difficulty of a successful attack is assumed to be directly related to the number of unique op-code sets possible which is shown to grow exponentially with allowed evolution time for the proposed chaos-based arithmetic logic unit.

Exact Logic and Fault Simulation in Presence of Unknowns

Abstract: Logic and fault simulation are essential techniques in electronic design automation. The accuracy of standard simulation algorithms is compromised by unknown or X-values. This results in a pessimistic overestimation of X-valued signals in the circuit and a pessimistic underestimation of fault coverage.This work proposes efficient algorithms for combinational and sequential logic as well as for stuck-at and transition-delay fault simulation that are free of any simulation pessimism in presence of unknowns. The SAT-based algorithms exactly classifiy all signal states. During fault simulation, each fault is accurately classified as either undetected, definitely detected, or possibly detected.The pessimism with respect to unknowns present in classic algorithms is thoroughly investigated in the experimental results on benchmark circuits. The applicability of the proposed algorithms is demonstrated on larger industrial circuits. The results show that, by accurate analysis, the number of detected faults can be significantly increased without increasing the test-set size.

Reversible Logic Based Design and Test of Field Coupled Nanocomputing Circuits

Abstract: Reversible computing is based on logic circuits that can generate unique output vector from each input vector, and vice versa, that is, there is a one-to-one mapping between the input and the output vectors. Reversible computing is the only solution for non-dissipative ultra low power green computing. Conservative reversible circuits are a specific type of reversible circuits, in which there would be an equal number of 1s in the outputs as there would be on the inputs, in addition to one-to-one mapping. This work illustrates the application of reversible logic towards testing of faults in traditional and reversible field coupled nanocircuits (Portions of this chapter are based on [2]. The enhancement is comprehensive treatment of: basics of reversible computing, motivation for reversible computing, background on conservative logic, basics of QCA computing, such as QCA logic devices and QCA clocking, related work etc. Several new reversible testable designs are introduced such as design of testable reversible T latch, design of testable asynchronous set/reset D latch and master-slave D flip-flop, design of testable reversible complex sequential circuits. QCA layouts of conservative logic gates are introduced with internal design details of QCA logic devices. Complete fault patterns information and analysis are provided for conservative logic gates. The synthesis of non-reversible testable design based on MX-cqca gate is extended to MX-cqca based implementation of standard functions. The significance of this work and broader prospective for future directions is also presented.). We propose the design of two vectors testable sequential circuits based on conservative logic gates. The proposed sequential circuits based on conservative logic gates outperform the sequential circuits implemented in classical gates in terms of testability. Any sequential circuit based on conservative logic gates can be tested for classical unidirectional stuck-at faults using only two test vectors. The two test vectors are all 1s, and all 0s. The designs of two vector testable latches, master-slave flip-flops, double edge triggered flip-flops, asynchronous set/reset D latch and D flip-flop are presented. The importance of the proposed work lies in the fact that it provides the design of reversible sequential circuits completely testable for any stuck-at fault by only two test vectors, thereby eliminating the need for any type of scan-path access to internal memory cells. The reversible designs of the double edge triggered flip-flop, ring counter and Johnson Counter are proposed for the first time in literature. We are showing the application of the proposed approach towards 100 % fault coverage for single missing/additional cell defect in the QCA layout of the Fredkin gate. We are also presenting a new conservative logic gate called Multiplexer Conservative QCA gate (MX-cqca) that is not reversible in nature but has similar properties as the Fredkin gate of working as 2:1 multiplexer. The proposed MX-cqca gate surpasses the Fredkin gate in terms of complexity (the number of majority voter), speed and area.

Is Spiking Logic the Route to Memristor-Based Computers?

Abstract: Memristors have been suggested as a novel route to neuromorphic computing based on the similarity between neurons (synapses and ion pumps) and memristors. The D.C. action of the memristor is a current spike, which we think will be fruitful for building memristor computers. In this paper, we introduce 4 different logical assignations to implement sequential logic in the memristor and introduce the physical rules, summation, `bounce-back', directionality and `diminishing returns', elucidated from our investigations. We then demonstrate how memristor sequential logic works by instantiating a NOT gate, an AND gate and a Full Adder with a single memristor. The Full Adder makes use of the memristor's memory to add three binary values together and outputs the value, the carry digit and even the order they were input in.

Smart home logic control method and system based on KNX bus protocol

Abstract: The invention discloses a smart home logic control method and system based on the KNX bus protocol. The smart home logic control method comprises the steps that firstly, smart home devices are grouped according to set demands, and the addresses of the grouped smart home devices, the addresses of the smart home device groups and the initial states of the grouped smart home devices are set based on the KNX bus protocol; secondly, control orders are transmitted to a KNX bus through an upper computer in the mode of messages of the addresses of the smart home device groups, a logic controller receives the control orders from the KNX bus, and analysis and judgment based on combinational logical operation and sequential logic operation are conducted on the control orders; finally, the logic controller sends the orders according with the control logic to the KNX bus in the mode of the messages of the addresses of the groups according to the timing sequence, and then intelligent control over a smart home is achieved. By the adoption of the smart home logic control method and system based on the KNX bus protocol, combinational logic verification and sequential logic deduction of the system control orders are achieved, the intelligence level of a smart home system is improved, and the accuracy of intelligent control is guaranteed.