Showing papers on "Snapback published in 2015"
TL;DR: In this paper, an electrostatic discharge (ESD) protection structure constructed by the stacking of multiple anode gate-cathode gate directly connected silicon-controlled rectifiers (DCSCRs), fabricated in a 0.18- $\mu \text{m}$ CMOS technology is reported.
Abstract: An electrostatic discharge (ESD) protection structure constructed by the stacking of multiple anode gate–cathode gate directly connected silicon-controlled rectifiers (DCSCRs), fabricated in a 0.18- $\mu \text{m}$ CMOS technology is reported in this letter. Two embedded diodes in the DCSCR dictate the turn-ON mechanism and hence give rise to a trigger voltage equal to twice the diode’s turn-ON voltage. This approach enables the DCSCR to offer a diode-like transmission line pulsing IV characteristic with a minimal snapback and a SCR-like high-ESD robustness. At 25 °C, DCSCR has an acceptable nanoampere-level leakage current. Besides, it is verified that the DCSCR can significantly reduce overshoot voltage when stressed by very-fast-rising pulses. As such, an ESD clamp constructed by stacking a selected number of DCSCRs can offer a flexible trigger/holding voltage and is suitable for low and medium voltage ESD protection applications.
34 citations
TL;DR: In this article, a piecewise-linear model with transient relaxation (PWL-TR) is proposed to describe the nonlinear transient characteristics of EDS protection devices and circuits.
Abstract: This work presents a new type of model, i.e., piecewise-linear model with transient relaxation (PWL-TR), to describe the nonlinear transient characteristics of electrostatic discharge (ESD) protection devices and circuits. The PWL-TR model represents the device as a finite-state machine; hence, no proprietary information is disclosed. The PWL-TR model offers accuracy comparable to a compact model but enables more computationally efficient simulation.
14 citations
Patent•
03 Dec 2015
TL;DR: In this article, a non-snapback device and a snapback device are coupled between either an I/O pad or a power pad and a ground terminal, and the voltage across the two devices is held at the same holding voltage.
Abstract: An ESD protection circuit, which is coupled between either an I/O pad or a power pad and a ground terminal, includes a non-snapback device and a snapback device. When the voltage across the non-snapback device is not less than the non-snapback trigger voltage, the non-snapback device is turned on. When the voltage across the snapback device is not less than the snapback trigger voltage, the snapback device is turned on, and the voltage across the snapback device is held at the snapback holding voltage, in which the snapback holding voltage is less than the snapback trigger voltage. The non-snapback device and the snapback device are cascaded.
11 citations
TL;DR: In this paper, a no-snapback silicon-controlled rectifier (NS-SCR) in a 0.35-μm BCD technology is presented, which is constructed by embedding in a typical SCR a p-type/intrinsic/n-type diode as the trigger element and two highly doped extension regions as parts of the bases of the parasitic bipolar transistors, which allow for a high electric field to be maintained at the reverse biased n/p junction in the electrostatic discharge (ESD) current path, prevent the
Abstract: In this letter, we develop a no-snapback silicon-controlled rectifier (NS-SCR) in a 0.35- $\mu {\mathrm{ m}}$ BCD technology. This device is constructed by embedding in a typical SCR a p-type/intrinsic/n-type diode as the trigger element and two highly doped extension regions as parts of the bases of the parasitic bipolar transistors. These added features allow for a high electric field to be maintained at the reverse biased n/p junction in the electrostatic discharge (ESD) current path, prevent the onset of strong conductivity modulation, and result in a no-snapback transmission line pulsing $I$ – $V$ characteristic. Stacking the NS-SCR’s offers an ESD protection solution that is area-efficient, robust, and latch-up immune. The high temperature effect on the leakage current of NS-SCR is also studied.
9 citations
Patent•
30 Dec 2015
TL;DR: In this article, the reverse conducting IGBT (ROCI) was proposed for power semiconductor devices, and particularly relates to a reverse-conducting IGBT device, where emission electrode schottky metal is additionally arranged in source electrode metal, and an N region is arranged below an N-type electric field stop layer.
Abstract: The invention belongs to the technical field of power semiconductor devices, and particularly relates to a reverse conducting IGBT device. Compared with a conventional reverse conducting IGBT structure, emission electrode schottky metal is additionally arranged in source electrode metal, and an N-region is arranged below an N-type electric field stop layer so that a reverse recovery characteristic working under a freewheel diode mode is respectively improved and generation of the snapback phenomenon is suppressed. The beneficial effects of the reverse conducting IGBT device are that the reverse conducting IGBT device has short reverse recovery time, the snapback phenomenon can be eliminated at a shorter back P+ collector region, and the preparation technology of the reverse conducting IGBT device is compatible with the technology of the conventional IGBT device. The invention is especially suitable for the reverse conducting IGBT device.
9 citations
Patent•
23 Dec 2015
TL;DR: In this paper, a transverse RC-IGBT device with a collector electrode structure was proposed to eliminate the snapback phenomenon of a traditional RC-IBT during the positive conduction process.
Abstract: The invention belongs to the semiconductor technology field and especially relates to a transverse RC-IGBT device. Based on a traditional device structure, a N-type resistor area 11 is arranged in a collector electrode structure. Because a thin N resistor area 11 is very thin and possesses a large impedance, when the device begins to carry out positive breakover, a large voltage drop is generated on the thin N resistor area 11 under a low current so that a voltage difference is generated between a P+ collector area 9 and a N-type electric field stop layer and the device is converted into an IGBT mode from a MOSFET mode. By using the new structure provided in the invention, conversion from the MOSFET mode to the IGBT mode can be completed under the low current so that a snapback phenomenon is not generated during a conduction process. Under a follow current diode mode, a PN joint formed by a P-type base area and a N-drift area is under a positively biased state; after the voltage drop exceeds a J1 starting voltage, the device is conducted so as to conduct the current. Therefore, by using the transverse RC-IGBT device provided in the invention, the snapback phenomenon of a traditional RC-IGBT during the positive conduction process is completely eliminated.
7 citations
Patent•
04 Nov 2015
TL;DR: In this paper, a longitudinal RC-IGBT was proposed to eliminate the snapback phenomenon in the forward conducting process of the conventional RC-IBT, and the device can be switched from the MOSFET mode to the IGBT mode with a very small current, so that the phenomenon does not occur in a conducting process.
Abstract: The invention belongs to the technical field of semiconductors, and particularly relates to a longitudinal RC-IGBT device. In the device, on the basis of a conventional device structure, an N type resistance region 11 is arranged in a collector structure. The thin N type resistance region 11 is very thin and has large impedance, and a great voltage drop is generated in the thin N type resistance region 11 with a small current when forward conducting of the device is just started, so that a voltage difference is generated between a P+ collector region 9 and an N type electric field stop layer 8, and the device is switched from an MOSFET mode to an IGBT mode. According to the novel structure provided by the invention, switching from the MOSFET mode to the IGBT mode can be finished with a very small current, so that the snapback phenomenon does not occur in a conducting process. In a freewheel diode mode, a PN junction formed by a P type base region and an N-drift region is in a positively-biased state, and the device is conductived when the voltage drop exceeds a J1 threshold voltage, so that current can be conducted. Through adoption of the longitudinal RC-IGBT device provided by the invention, the snapback phenomenon in the forward conducting process of the conventional RC-IGBT is eliminated completely.
4 citations
Patent•
09 Jul 2015TL;DR: In this paper, the authors proposed a circuit configurations and related methods that may be implemented to protect circuitry from adverse effects of transistor snapback that may occur during ESD events, while at the same time providing rail-clamping capability during occurrence of ESD.
Abstract: Circuit configurations and related methods are disclosed that may be implemented to protect circuitry from adverse effects of transistor snapback that may occur during ESD events. The circuitry and methods may be implemented as part of distributed ESD rail clamping circuitry that includes ESD circuit elements that are coupled to power nodes or supply rails and not to signal nodes or signal pads of the circuitry in a manner that reduces parasitic loading on signal pads to reduce or substantially eliminate NMOS and/or PMOS transistor snapback occurrence, while at the same time providing rail-clamping capability during occurrence of ESD events. Using the disclosed circuitry and methods, at least a portion of ESD current may be diverted by clamp circuitry from or to a supply rail to reduce voltage differential across the sources of CMOS output transistors relative to their bulk terminals in a manner that reduces forward biasing of parasitic BJTs present at each of the CMOS output transistors, thus reducing or substantially eliminating occurrence of transistor snapback during an ESD event.
4 citations
Patent•
15 Jul 2015
TL;DR: In this paper, a reverse-conducting insulated gate bipolar translator (RC-IGBT) was proposed to prevent the snapback effect in power semiconductor technology, in particular in particular to the power semiconductors.
Abstract: The invention relates to the power semiconductor technology, in particular to an RC-IGBT (reverse-conducting insulated gate bipolar translator) capable of inhibiting a snapback effect. A main method of the RC-IGBT comprises steps as follows: a metal resistor with proper resistance is produced between electrode contacts of a P-type collector region and an N-type collector region, when the device is connected forwards, the current IF flows through the metal resistor R and produces voltage drop IFR on the metal resistor, the voltage difference is produced between the P-type collector region and an N-type buffer layer, and if the IFR is larger than the forward connection voltage drop of a PN junction, the PN junction is connected forwards to be in an IGBT working mode, so that the snapback effect is effectively inhibited. The RC-IGBT has the benefits that the RC-IGBT has the excellent capacity of inhibiting the snapback phenomenon under the condition that the process complexity is not increased excessively, and meanwhile, other performance parameters of the RC-IGBT cannot be affected.
4 citations
Patent•
11 Feb 2015TL;DR: In this paper, two separate metal layers are implemented to make multiple body and source contacts electrically isolated from one another throughout the active area of the device, which enables suppression of bipolar snapback without losing bidirectional switching capability.
Abstract: A bidirectional trench FET device includes a semiconductor substrate, a trench in the substrate extending vertically from the surface of the substrate, and a body region laterally adjacent the trench. A source region is disposed in the semiconductor substrate between the body region and the surface of the substrate. A dielectric layer is disposed over the surface and a body electrode is disposed over the dielectric layer. A body contact plug extends through the dielectric layer to interconnect the body region with the body electrode, and the body contact plug is electrically isolated from the source region. Two separate metal layers are implemented to make multiple body and source contacts electrically isolated from one another throughout the active area of the device. The low resistive path by the body contact plug and the separate metal layers enables suppression of bipolar snapback without losing bidirectional switching capability.
4 citations
TL;DR: In this paper, an improved grounded-gate N-channel metal-oxide semiconductor (GGNMOS) transistor triggered silicon-controlled rectifier (SCR) structure, named GGSCR, is proposed for high holding voltage ESD protection applications.
Abstract: Developing an electrostatic discharge (ESD) protection device with a better latch-up immunity has been a challenging issue for the nanometer complementary metal-oxide semiconductor (CMOS) technology. In this work, an improved grounded-gate N-channel metal-oxide semiconductor (GGNMOS) transistor triggered silicon-controlled rectifier (SCR) structure, named GGSCR, is proposed for high holding voltage ESD protection applications. The GGSCR demonstrates a double snapback behavior as a result of progressive trigger-on of the GGNMOS and SCR. The double snapback makes the holding voltage increase from 3.43 V to 6.25 V as compared with the conventional low-voltage SCR. The TCAD simulations are carried out to verify the modes of operation of the device.
Patent•
12 Aug 2015
TL;DR: In this article, the structure of an IGBT chip was revealed, which consisted of an MOS field effect transistor and a triode, and the IGBT unit was arranged in the isolating cover.
Abstract: The invention discloses a structure of an IGBT chip, which comprises an IGBT unit that is composed of an MOS field effect transistor and a triode. The IGBT chip further comprises a control switch Q, electrodes N2 and an isolating cover. The IGBT unit is arranged in the isolating cover. The isolating cover is arranged in the electrode N2 . The control switch Q is connected with the electrode N2 and the triode. When the IGBT unit is conducted in the forward direction, the control switch Q is in an off state; and when the IGBT unit is conducted in the backward direction, the control switch Q is in an on state. The structure of the IGBT chip has functions of basically settling a problem of snapback without influence to the performance parameter, effectively integrating a diode in the IGBT, truly realizing low conduction voltage drop and good switching speed of the IGBT, and greatly improving device reliability.
15 Mar 2015
TL;DR: In this paper, an Hspice macro model is presented to model the snapback characteristics of gate-grounded NMOS and GCNMOS under ESD stress, which helps in predicting the trigger voltage and holding voltage for ESD circuit application.
Abstract: In this paper an Hspice macro model is presented to model the snapback characteristics of GGNMOS (gate-grounded NMOS) and GCNMOS (gate-coupled NMOS) under ESD stress. The 5V NMOS be simulated in this paper is based on the 0.35um BCD technology as an ESD protection device. The new macro model has successfully predicted the trigger voltage and holding voltage of the GGNMOS and GCNMOS according to the silicon data. The effects of device parameters Tref and Rs exhibit a good trend curve in agreement with BJT model, which helps for the prediction of the trigger voltage and holding voltage for ESD circuit application.
01 Dec 2015
TL;DR: The equivalent circuit model is constructed using MOS transistors that represent the avalanche characteristics of Vertical Impact Ionization MOSFET and shows that 90% of the analysis subthreshold slope value of circuit simulations similar to the reference experimental value.
Abstract: -In this paper, an equivalent circuit model is proposed that describes the avalanche and snapback characteristics of Vertical Impact Ionization MOSFET (IMOS). The equivalent circuit model is constructed using MOS transistors that represent the avalanche characteristics. The main goal is to predict the vertical IMOS integrated circuits by using circuit simulations. The vertical IMOS is predicted to have a lower subthreshold slope and high ratio of current. Besides that, the equivalent circuit model is explained which is include the parasitic bipolar transistor with a generated-hole-dependent base resistance. The models for parasitic bipolar is combined with a PSPICE MOS transistor model and it is represented the gate bias dependence of snapback characteristic. The equivalent circuit parameters are extracted from the reference experimental values of previous research and modified to reproduce the measured avalanche and snapback characteristic of the vertical IMOS transistor. The results show that 90% of the analysis subthreshold slope value of circuit simulations similar to the reference experimental value. The ratio of the current also shows almost the same behavior. Therefore, the equivalent circuit model for vertical IMOS can be used in circuit simulations.
Patent•
06 Aug 2015
TL;DR: In this paper, a reverse conducting IGBT is formed of a wide gap semiconductor, and the distance Wp between collector short circuit parts 3 is set in a range where distance Xp(Si) between reverse-conducting IGBTs of the same breakdown voltage and same configuration formed by a Si semiconductor is the upper limit and the AXWp((Si) is the lower limit.
Abstract: PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device by suppressing snapback phenomenon at the time of turning a reverse conducting IGBT on, and also suppressing deterioration due to snapback phenomenon, and to provide an operation method thereof.SOLUTION: A reverse conducting IGBT is formed of a wide gap semiconductor, and the distance Wp between collector short circuit parts 3 is set in a range where distance Wp(Si) between reverse conducting IGBTs of the same breakdown voltage and same configuration formed of a Si semiconductor is the upper limit, and the AXWp(Si) is the lower limit. A coefficient A is a value obtained by dividing the product of the built-in voltage Vbi(WB) of the pn junction of a wide gap semiconductor and the characteristic on resistance RonS(WB) of a wide gap semiconductor MOSFET, by the product of the built-in voltage Vbi(Si) of the pn junction of a Si semiconductor device and the characteristic on resistance RonS(Si) of a Si-MOSFET.
Patent•
22 Jul 2015
TL;DR: In this article, an SA-LIGBT (shorted-anode lateral insulated gate bipolar transistor) capable of restraining a snapback effect has been proposed, where a metal resistor with a certain resistance value is generated between electrode contacts of a P-type collecting region and an N-type collector region, and the resistance value of the metal resistor can be controlled by adjusting the area and the length of the resistor.
Abstract: The invention relates to the power semiconductor technology, in particular to an SA-LIGBT (shorted-anode lateral insulated gate bipolar transistor) capable of restraining a snapback effect An implementing method for the SA-LIGBT mainly includes that a metal resistor with a certain resistance value is generated between electrode contacts of a P-type collecting region and an N-type collecting region, and the resistance value of the metal resistor can be controlled by adjusting the area and the length of the metal resistor When a device is turned on forwardly, current IF flows through the metal resistor R and generates a voltage drop IFR on the metal resistor to generate voltage difference between the P-type collecting region and an N-type buffering layer, if the IFR is larger than a forward turn-on voltage drop of a PN junction, the PN junction is turned on forwardly and enters an IGBT (insulated gate bipolar transistor) working mode, and thus, the snapback effect is restrained effectively The SA-LIGBT has the advantages that capability of effectively restraining a snapback phenomenon without increasing technical complexity excessively, and other performance parameters of the SA-LIGBT cannot be affected
01 Jun 2015
TL;DR: In this paper, off-state breakdown characteristics of shallow trench isolation (STI)-type drain extended NMOS (DeNMOS) devices with different drain structures are studied and compared.
Abstract: In this work, OFF-state breakdown characteristics of shallow trench isolation (STI)-type drain extended NMOS (DeNMOS) devices with different drain structures are studied and compared The drain structures include deep-drain structure and structures with heavy doping on STI-sidewall regions These devices show improved ON-state resistance without degrading breakdown voltage Devices with higher doping underneath the drain diffusion region exhibit stronger bipolar triggering and higher snapback in their breakdown characteristics, thereby sustaining higher drain current levels before device failure The devices with heavy doping only on the STI-sidewall show intermediate snapback characteristics between conventional and deep-drain devices in the breakdown region Therefore, this work provides physical insights into the impact of different drain doping profiles on low-voltage I-V characteristics and high current drain breakdown characteristics of STI-DeMOS devices for different drain doping profiles
27 Aug 2015
TL;DR: In this paper, double-snapback phenomena in transient power-rail ESD clamp circuits are reported and the reported double snapback mechanisms present latch-up free ESD protection schemes.
Abstract: Double snapback phenomena in transient power-rail ESD clamp circuits are reported in this paper. By properly sequencing different snapback mechanisms, the reported double snapback phenomena present latch-up free ESD protection schemes. Experiment results verify that both the first holding voltage (V h1 ) and second holding current (I h2 ) meet latch-up free criteria for the utilized 65-nm CMOS process. Besides, transient voltage waveforms in transmission line pulsing (TLP) tests are analyzed to fully understand the reported double snapback phenomena.
Patent•
07 Oct 2015
TL;DR: In this paper, a control method of the IGBT chip is characterized in that when an IGBT is in the positive conduction, a control switch Q is in a turn-off state, a PN junction J2 is in reverse bias state, and an electric field does not influence an electrode N2 because of the effect of an isolating cover.
Abstract: The present invention discloses a control method of an IGBT chip. The control method of the IGBT chip is characterized in that when an IGBT is in the positive conduction, a control switch Q is in a turn-off state, a PN junction J2 is in a reverse bias state, a PN junction J1 is in a positive bias state, and an electric field does not influence an electrode N2 because of the effect of an isolating cover; when the IGBT is located in the reverse conduction, the control switch Q is in a turn-on state, the PN junction J1 is in the reverse bias state, the PN junction J2 is in the positive bias state, and after flowing out to be blocked by the influence of a P potential barrier, the electrons move towards the electrode N2 , and move and flow out via the control switch Q. The control method of the IGBT chip of the present invention solves the snapback basically while not influencing the performance parameters, and enables a diode to be integrated in the IGBT effectively, thereby really realizing the situation that the IGBT has the low forward voltage drop and also has a good switching speed, and improving the reliability of a device.
01 Dec 2015
TL;DR: In this paper, a P-type implant below the channel region is presented to achieve high ruggedness with the help of this implantation, the device shows significantly improved snapback performance.
Abstract: A RF LDMOS with an additional P-type implant below channel region is presented to achieve high ruggedness. With the help of this implantation, the device shows significantly improved snapback performance. Besides on-wafer TLP test, we propose a more rigorous ‘open’-circuit test to demonstrate this fantastic robustness. The Faraday shield and drift region is finely engineered to achieve optimum Rds(on)-BV trade-off. A 1um-drift length device is shown to achieve more than 300mA/mm saturation current and 1.6W/mm power density at 1dB compression, while maintaining HCI immunity. A power amplifier is implemented from 400MHz to 470MHz to verify the broadband performance.
TL;DR: In this paper, a reverse-conducting insulated-gate bipolar transistor (RC-IGBT) with separated free-wheeling diode (FWD) is proposed, and the results show that the new structure achieves snapback-free characteristics.
Abstract: A novel reverse-conducting insulated-gate bipolar transistor (RC-IGBT) featuring separated free-wheeling diode (FWD) is proposed. The snapbacks of conventional RC-IGBT are analysed; the electrical characteristics for the proposed RC-IGBT with four kinds of anti-paralleled FWDs are discussed. The results show that the new structure achieves snapback-free characteristics. Moreover, the figures of merit I (FOM I) between V F and E off in the forward operation case and FOM II between V R and Q rr in the reverse operation case are superior to conventional RC-IGBT. Especially for the integrated merged P-i-N/Schottky (MPS, FWD-A), FOM I can be enhanced by 10%, and FOM II can be enhanced by 50%. In addition, the technological ease of fabrication is another attraction of the proposed device.
TL;DR: In this article, the authors proposed an N-path SA-IGBT, which is partially surrounded by the floating P-layer and oxide layer in the backside of the wafer, which provides a direct path to the N-collector for electronic current and achieves shorter turn-off time.
01 Jan 2015
TL;DR: This chapter begins with a review of BJT types, operation, and characteristics that are relevant to analog applications, followed by a description of JFET types, basic operation,and characteristics and concludes with simple circuit applications of both transistors.
Abstract: Bipolar junction transistors (BJT) are inherent to CMOS technologies. Understanding the basic principles of operation of a BJT and its characteristics is not only important to efficiently use the component in Bipolar-CMOS (BiCMOS) applications. It is also important to understand bipolar effects in CMOS, such as subthreshold behavior, snapback, and latch-up, and to identify process and design techniques to modify their impact on circuit performance. Similarly, a discussion of integrated Junction field-effect transistors (JFET) is important to its use in analog designs, mainly as a very low-noise, high input-impedance device. It is also important to understand its parasitic effect, referred to as “The JFET Effect” in high-voltage, high power devices. The chapter begins with a review of BJT types, operation, and characteristics that are relevant to analog applications. This is followed by a description of JFET types, basic operation, and characteristics. The chapter concludes with simple circuit applications of both transistors.
Patent•
07 Apr 2015
TL;DR: In this paper, a Snapback ESD protection device employing one or more nonplanar metal-oxide-semiconductor transistors (MOSFETs) is described.
Abstract: Snapback ESD protection device employing one or more non-planar metal-oxide-semiconductor transistors (MOSFETs) are described. The ESD protection devices may further include lightly-doped extended drain regions, the resistances of which may be capacitively controlled through control gates independent of a gate electrode held at a ground potential. Control gates may be floated or biased to modulate ESD protection device performance. In embodiments, a plurality of core circuits are protected with a plurality of non-planar MOSFET-based ESD protection devices with control gate potentials varying across the plurality.
08 Oct 2015
TL;DR: In this article, the authors investigated mutual ESD behavior dependency between multiple devices under Transmission Line Pulse stress using transient 3-D TCAD simulation and found that the transient response of drain voltage has multiple snapback profiles in the mixed-mode test.
Abstract: Mutual ESD behavior dependency between multiple devices under Transmission Line Pulse stress was investigated using transient 3-D TCAD simulation. Interestingly, the transient response of drain voltage has multiple snapback profiles in the mixed-mode test. When one of the devices in the mixed-mode test is turned on, the current waveform of the other adjacent devices shows snapback profile. This mutual relation between protection devices affects the ESD robustness. If there is a big imbalance of individual ESD characteristics between the devices under the mixed-mode test, the lattice temperature hot-spot and failure may occurs in the device even though the robustness of the other connected device is lower than that of the device in the single-device test.
01 Jun 2015
TL;DR: In this article, an analytical method to determine the electrothermal instability due to self-heating and impact ionization in terms of dissipated power and junction temperature is presented.
Abstract: This paper illustrates an analytical method to determine the electro-thermal instability due to self-heating and impact ionization in terms of dissipated power and junction temperature. The analysis is carried out for single transistors (corresponding to silicon and gallium arsenide technologies) as well as for scaled devices to appreciate the use of dissipated power for determining the safe operating region of bipolar transistors. Our analysis is supported by the already reported numerical, PSPICE and experimental data from the literature and shows that at usual operating conditions the small geometry devices have less safe operating region compared to the larger ones.