Showing papers on "Strained silicon published in 1982"

A physical model for the dependence of carrier lifetime on doping density in nondegenerate silicon

Abstract: A theoretical model that describes the dependence of carrier lifetime on doping density, which is based on the equilibrium solubility of a single defect in nondegenerately doped silicon, is developed. The model predictions are consistent with the longest measured hole and electron lifetimes reported for n -type and p -type silicon, and hence imply a possibly “fundamental” (unavoidable) defect in silicon. The defect is acceptor-type and is more soluble in n -type than in p -type silicon, which suggests a longer fundamental limit for electron lifetime than for hole lifetime at a given nondegenerate doping density. The prevalent, minimum density of the defect, which defines these limits, occurs at the processing temperature below which the defect is virtually immobile in the silicon lattice. The analysis reveals that this temperature is in the range 300–400°C, and thus emphasizes, when related also to common non-fundamental defects, the significance of low-temperature processing in the fabrication of silicon devices requiring long or well-controlled carrier lifetimes.

Carbon in silicon: Properties and impact on devices

Abstract: The properties, origin and analysis of carbon in silicon and its influence on the electrical characteristics of devices are investigated and reviewed. The typical carbon concentrations in electronic-grade silicon are still some 1016 cm−3. The small distribution coefficient (k0 = 0.058) causes an inhomogeneous incorporation of carbon along the crystal axis and across the crystal diameter during crystal growth. Carbon concentrations exceeding about 5 × 1016 cm−3 in float-zoned silicon can lead to the formation of process-induced defects in the fabrication of power rectifiers and thyristors. These defects which are frequently arranged in a swirl-like pattern strongly deteriorate the electrical characteristics of these devices. It is shown that carbon is involved primarily in the generation of the defect nuclei whereas the defects finally observed form via precipitation of oxygen and agglomeration of silicon interstitials. Reasons for the benign behavior of high carbon concentrations in the processing of integrated circuits are discussed. In powder device processing the formation of carbon-induced defects is safely avoided by application of silicon containing carbon less than 5 × 1016 cm−3.

Process for producing dielectrically isolated silicon devices

Abstract: Dielectrically isolated semiconductor devices are producible through a relatively convenient fabrication procedure. In this fabrication procedure, a substrate having regions of single crystal silicon and regions of silicon oxide is employed. Such substrate is expeditiously produced by methods which leave the surface of the single crystal regions below those of the silicon oxide regions. Silicon is deposited by CVD onto the structure with its regions of silicon dioxide and single crystal silicon. Initially, the conditions of the CVD procedure are controlled so that epitaxial silicon grows on the regions of single crystal silicon but essentially no growth is induced on the silicon oxide regions. When the growth of the single crystal regions has proceeded sufficiently to produce a substantially planar structure, advantageously the deposition conditions are adjusted so that silicon is also deposited on the surface of the silicon oxide. The polycrystalline or amorphous silicon layer overlying regions of silicon oxide produced from this growth is then converted into single crystal silicon.

Surface Silicon Crystallinity and Anomalous Composition Profiles of Buried SiO 2 and Si 3 N 4 Layers Fabricated by Oxygen and Nitrogen Implantation in Silicon

Abstract: Buried SiO2 and Si3N4 with residual crystalline surface silicon were fabricated by implantation of O+, O2+, N+ and N2+ into single-crystal silicon with 0.6–3.0×1018 atom/cm2 dose at an energy of 70–150 keV/atom. The implanted silicon wafers were annealed at 1150°C to recover the surface silicon crystallinity and to ensure good Si–O and Si–N bonds. After this, high-quality crystalline silicon layers were grown epitaxially on the implanted surface. The surface silicon damage and the buried layer composition profiles were measured reliably by the Rutherford backscattering method together with the channeling technique. In the buried layers, the O/Si ratio did not exceed the stoichiometric ratio of 2.0 for SiO2 even before annealing. However, the N/Si ratio exceeded the stoichiometric ratio of 4/3 for Si3N4.

A new silicon‐on‐insulator structure using a silicon molecular beam epitaxial growth on porous silicon

Abstract: A new silicon‐on‐insulator (SOI) structure has been achieved by utilizing silicon molecular beam epitaxial (Si‐MBE) growth on porous silicon, silicon island patterning, and the subsequent laterally enhanced oxidation of the porous silicon. The surface of Si‐MBE film grown on porous silicon at 770 °C without high‐temperature preheating has a 7×7 superlattice structure when observed by a reflection high‐energy electron diffraction (RHEED). Patterned Si‐MBE film island, that is 7.0 μm wide and 0.35 μm thick, is successfully isolated by the laterally enhanced oxidation of porous silicon.

An investigation of the properties of an epitaxial si layer on a substrate with a buried sio2 layer formed by oxygen-ion implantation

Abstract: We have investigated the crystallographic properties of a silicon substrate with a buried SiO2 layer formed by oxygen-ion implantation (16O+ dose: 1.2 to 2.4×1018/cm2) and an epitaxial silicon layer on the substrate using the step-by-step sample thinning technique. The surface silicon layer on the buried SiO2 layer was found to have a dislocation-free single-crystalline silicon region, but with small precipitates of oxide. The epitaxial silicon layer grown on the surface silicon layer was found to have a high density of dislocations. The dislocation density was 2×109/cm2 and was almost constant for a substrate oxygen dose above 0.6×1018/cm2. The dislocations are considered to be caused by precipitates in the surface silicon layer. However, the epitaxial layer had fairly high mobility and no stacking faults.

Characterization of Polycrystalline Silicon MOS Transistors and Its Film Properties. I

Abstract: The characterization of polycrystalline silicon MOS transistors and its film properties are studied, with special emphasis on the relationship between crystalline defects and carrier transport phenomena An increase in mobility with gate field in polycrystalline silicon MOS transistors and also with doping concentration in polycrystalline silicon films is observed These phenomena are interpreted as space charge scattering effects caused by a high density of dislocations in the films U-shaped drain current vs gate voltage curves are observed both in p-channel and n-channel polycrystalline silicon MOS transistors The anomalous drain current in the accumulation region is interpreted as junction breakdown at the drain edge caused by crystalline imperfections in the films

Process for fabricating polycrystalline silicon film resistors

Abstract: A method for fabricating polycrystalline silicon resistors is described which includes deposition of a polycrystalline silicon layer of very fine grain size upon an insulator surface, followed by ion implantation of boron equal to or slightly in excess of the solubility limit of the polycrystalline silicon. This ion implantation is normally done using a screen silicon dioxide surface layer. The structure may be annealed at temperatures of between about 800° C. to 1100° C. for 15 to 180 minutes to control the grain size of the polycrystalline silicon layer, homogenize the distribution of the boron ions throughout the entire film thickness and to raise the concentration of the boron in the silicon grains to the solid solubility limit. The suitable electrical contacts are now made to the polycrystalline silicon layer to form the resistor.

Thin-film transistors on a-Si:H

Abstract: A comparison has been made of the characteristics of nitride and oxide MOSFET's fabricated with thin films of amorphous silicon. Published data indicate that Si 3 N 4 -Si:H thin film devices are superior to the oxide devices. Accumulation-mode MOSFET's were fabricated in which the drain current arises from electric-field induced accumulation of electrons (majority carriers) at the a-Si:H-insulator interface. Hydrogenated amorphous silicon layers were deposited at 230°C by glow-discharge plasma decomposition in silane. The deposition conditions were found to be critical, and in the present study the films were grown on an electrically grounded substrate with RF power of 1 W applied to the counter electrode. The a-Si:H was deposited onto silicon nitride and silicon dioxide layers of 100-500-nm thickness, and thin-film transistors were fabricated with the inverted MOS configuration. Devices were tested with on/off drain current ratios greater than 104for a gate voltage swing of 0 to 12 V and drain-current saturation for source-drain voltages of less than 12 V. The properties of MOSFET's on a-Si:H are discussed with a comparison of the silicon-nitride-a-Si: H and silicon-dioxide-a-Si:H interfaces and an evaluation of doped active layers. The transistors on silicon dioxide are as good as any reported to date on silicon nitride.

Method of producing shallow, narrow base bipolar transistor structures via dual implantations of selected polycrystalline layer

Abstract: A method for fabricating high performance NPN bipolar transistors which result in shallow, narrow base devices is described. The method includes depositing a polycrystalline silicon layer over a monocrystalline silicon surface in which the base and emitter regions of the transistor are to be formed. Boron ions are ion implanted into the polycrystalline silicon layer near the interface of the polycrystalline silicon layer with the monocrystalline silicon layer. An annealing of the layer structure partially drives in the boron into the monocrystalline silicon substrate. Arsenic ions are ion implanted into the polycrystalline silicon layer. A second annealing step is utilized to fully drive in the boron to form the base region and simultaneously therewith drive in the arsenic to form the emitter region of the transistor. This process involving a two-step annealing process for the boron implanting ions is necessary to create a base with sufficient width and doping to avoid punch-through. There is also described a method for forming NPN transistors in an integrated circuit.

Method of fabricating submicron silicon structures such as permeable base transistors

Abstract: Submicron silicon structures are fabricated by repeat oxidation and stripping the walls of a U-groove leaving thin silicon fingers. This method may be used to fabricate a silicon transistor having an emitter and a collector separated by a channel. The channel is formed in a silicon finger by a Schottky base, which at zero bias pinches off conduction of the channel. A bias voltage on the Schottky base causes conduction. The channel has a very short length making the transistor capable of high frequency operation.

Solid-Phase Lateral Epitaxial Growth onto Adjacent SiO 2 Film from Amorphous Silicon Deposited on Single-Crystal Silicon Substrate

Abstract: Single-crystal silicon films (200 nm thick) have been grown laterally by thermal annealing from amorphous silicon evaporated on a single-crystal (100) silicon substrate and implanted with ~1016/cm2 Si, onto an adjacent SiO2 film by solid-phase epitaxy The key requirements for this kind of lateral epitaxy appear to be a high-dose Si ion implanatation and low temperature (575°C) annealing for a long period in order to suppress the nucleation of randomly-oriented crystals on the SiO2 film

Method for making a silicon carbide substrate

Abstract: A silicon carbide seed layer is first formed on a (111) major surface of a silicon substrate through the use of the conventional chemical vapor deposition method. The silicon carbide seed layer includes a first surface confronting the silicon substrate. The first surface shows a predetermined grain alignment oriented with the (111) major surface of the silicon substrate even though the deposition is carried out at a temperature below the melting point of the silicon substrate. Then, the silicon substrate is melted so that the first surface of the silicon carbide seed layer is exposed to the molten silicon including a carbon source therein. In this way, a second silicon carbide layer is formed on the first surface of the silicon carbide seed layer through the use of a liquid-phase epitaxial growth method. If required, a third silicon carbide layer is formed on the second silicon carbide layer to thicken the silicon carbide substrate through the use of a conventional chemical vapor deposition method, wherein the substrate is maintained at a temperature above the melting point of silicon to ensure the high-quality crystallization.

Single-crystal silicon transistors in laser-crystallized thin films on bulk glass

Abstract: High-performance thin-film transistors (TFT) have been fabricated in single-crystal silicon thin films on bulk fused silica. Deposited films of polycrystalline silicon were patterned to control nucleation and growth of single-crystal material in pre-selected areas and encapsulated with a dielectric layer (e.g., SiO 2 ) in preparation for laser crystallization. Patterning also minimized microcracking during crystallization. The patterned silicon layer was crystallized with a scanning CO 2 laser, which produced islands with preferred crystal orientation. The single crystallinity of the islands was established with transmission electron microscopy after transistor evaluation. The silicon islands were processed with conventional microelectronic techniques to form metal-oxide-semiconductor-field-effect transistors operating in the n-channel enhancement mode. The devices display exceptional electrical characteristics with "low-field" channel mobilities > 1000 cm2/V sec and leakage currents 2 - laser processing of silicon films a viable and versatile basis for a silicon-on-insulator technology.

Process for producing dielectrically isolated single crystal silicon devices

Abstract: Well-oriented device quality silicon is formed on a dielectric material through a specific melting procedure. In this procedure, a body including polycrystalline or amorphous silicon overlying a dielectric is heated to a temperature close to the melting point of silicon. A narrow region of the amorphous or polycrystalline silicon whose length is substantially longer than its width is then melted using an energy source such as a laser. This long, narrow region is propagated through the amorphous or polycrystalline silicon to produce the desired device quality material.

Method of manufacturing insulating film and electric device utilizing the same

Abstract: An insulating film is prepared by oxidizing an amorphous silicon layer containing boron or boron and germanium. The amorphous silicon layer is partially oxidized inwardly from the surface of the amorphous silicon layer to form the insulating film, while the unoxidized portion of the amorphous silicon layer is used as a conductive layer. The amorphous silicon layer may contain boron or boron and an element of Group IV, for example germanium. The insulating film is utilized to fabricate a bipolar transistor.

Fabrication process for a shallow emitter/base transistor using same polycrystalline layer

Abstract: A method for fabricating a high performance bipolar device having a shallow emitter and a narrow intrinsic base region is described. The method uses a minimum number of process steps. The method involves providing a silicon semiconductor body having regions of monocrystalline silicon isolated from one another by isolation regions and a buried subcollector therein. A layer of polycrystalline silicon is deposited on the silicon substrate. The surface of the polycrystalline silicon is oxidized and the polycrystalline silicon is implanted with a base impurity. Silicon nitride and oxide layers are deposited on the polysilicon layer. An opening is made in the surface oxide layers and the silicon nitride layer to define the emitter area. The polycrystalline silicon is thermally oxidized to drive the base impurity into the substrate. The thermal oxide is removed in an isotropic etch to form a sidewall. The emitter impurity is ion implanted into the polycrystalline silicon in the emitter area and then driven into the substrate. The collector, base and emitter contact openings are made and the conductive metallurgy is formed.

Method of fabricating zener diodes

Abstract: A process for forming zener diodes from an IC structure having coextensive layers of gate silicon dioxide and polycrystalline silicon on a substrate and self-aligned with a diffused region in the substrate. A differential oxidation of the polycrystalline silicon and substrate silicon is followed in turn by a silicon dioxide etch to expose only the polycrystalline silicon layer. Thereafter, the exposed polycrystalline silicon is etched with an etchant that does not materially etch silicon dioxide. The exposed substrate is then subjected to an ion implantation, performed with an energy sufficient to locate the peak impurity concentration below the substrate surface, and a dose sufficient to moderately dope the area originally under the polycrystalline silicon electrode while reducing the effective concentration of the opposite impurity type dopant in the diffused region of the substrate. Residual silicon dioxide is now removed with an etchant that does not materially etch silicon; exposing the active area of the substrate. Annealing follows to heal implant and etching damage. The junction of the zener diode formed thereby is located below the substrate surface and displaced laterally from any area of etchant damage to provide stable and reproducible zener break-down characteristics.

Compensated amorphous silicon solar cell incorporating an insulating layer

Abstract: A P-I-N type compensated amorphous silicon solar cell which incorporates an insulating layer adjacent to the compensated intrinsic amorphous silicon layer.

Hydrogen annealing of silicon gate‐nitride‐oxide‐silicon nonvolatile memory devices

Abstract: A hydrogen annealing study of silicon gate‐nitride‐oxide‐silicon (SNOS) nonvolatile memory devices showed that the important parameter in determining the optimum hydrogen annealing temperature for maximum charge retention is the previous thermal history of the memory devices. If a memory device’s charge retention is not degraded by high‐temperature processing, then the hydrogen anneal should be at the silicon nitride deposition temperature. If a device is degraded by high‐temperature processing, then the hydrogen anneal should be at the degradation temperature.

Optical recording in amorphous silicon films

Abstract: The amorphous to polycrystalline transition in thin silicon layers is accompanied by a large change in optical transmission in the visible. By inducing this transition by laser annealing, high‐resolution optical recording and visible‐light readout have been demonstrated. As an optical recording material, amorphous silicon layers offer characteristics of high information‐storage density, long‐term stability, and negligible degradation upon repeated readout. Such an optical image in a thin silicon layer can be converted to a relief pattern by taking advantage of the difference in etch rate between amorphous and polycrystalline silicon, thus providing a method of producing patterns in silicon layers without use of intermediate photo‐resist steps.

Silicon molecular beam epitaxy on arsenic‐implanted and laser‐processed silicon

Abstract: We report on the production of doped silicon layers buried under epitaxial undoped silicon layers, giving particular attention to the abruptness of the doped‐undoped silicon interface. Arsenic‐implanted silicon is both annealed and atomically cleaned using pulsed laser irradiation. Surface cleanliness and surface order are checked with Auger electron spectroscopy and low energy electron diffraction respectively. Molecular beam epitaxy is done with a substrate temperature between 300 and 600 °C, resulting in an epitaxial silicon layer of typically 100 nm. Rutherford backscattering plus channeling show that the arsenic concentration drops abruptly at the substrate‐epitaxy interface and that the epitaxial layer is of good crystal quality.

Integrated circuit bipolar memory cell

Abstract: A static bipolar random access memory cell includes first and second transistors formed in epitaxial silicon pockets 41 and 42 in a substrate. The collectors 19 and 19' and bases 15 and 15' of the transistors are interconnected with polycrystalline silicon 21 doped to match the conductivity types of the regions contacted. Undesired PN junctions 40 and 40' created thereby are shorted using an overlying layer of a metal silicide 25. In a region overlying the N conductivity type polycrystalline silicon 23 or 23', the metal silicide is removed and a PH junction 37 or 37' created by depositing P conductivity type polycrystalline silicon 35c or 35c'. If desired additional P type polycrystalline silicon 35a and 35b may be deposited across the surface of the epitaxial layer where the base regions of the two transistors are formed to reduce the base series resistance.

Amorphous silicon solar cells incorporating an insulating layer in the body of amorphous silicon and a method of suppressing the back diffusion of holes into an N-type region

Abstract: Hydrogenated amorphous silicon solar cells which incorporate a thin insulating layer between a photoactive layer of intrinsic hydrogenated amorphous silicon and a heavily doped radiation incident N or N + -type layer of hydrogenated amorphous silicon.

Method of applying a carbon-rich surface layer to a silicon carbide filament

Abstract: The invention relates to a surface treatment for stoichiometric silicon carbide. A carbon-rich silicon carbide layer is applied over the silicon carbide. In the case of the silicon carbide surface, the ratio of silicon to carbon in the carbon-rich layer varies from one at the silicon carbide interface to near zero in the interior of the carbon-rich layer to greater than zero and preferably 0.3 to 0.5 on the surface of the carbon-rich layer remote from the interface. A preferred method of making the silicon carbide layer is also presented.

Logic structure utilizing polycrystalline silicon Schottky diode

Abstract: An integrated circuit structure and process for fabricating it are described which allow fabrication of a very compact high-speed logic gate. The structure utilizes a bipolar transistor formed in an epitaxial silicon pocket surrounded by silicon dioxide. A pair of Schottky diodes and a resistor are formed outside the epitaxial pocket on the silicon dioxide and connected to the pocket by doped polycrystalline silicon.

Extended cyclability in electrically-alterable read-only-memories

Abstract: An electrically-alterable read-only-memory using silicon dioxide and silicon-rich silicon dioxide layers capable of being cycled ≳ 107times by minimizing electron charge trapping in the SiO 2 layers of the device by incorporation of small amounts of silicon is reported for the first time. Charge transfer to and from a floating polycrystalline silicon layer from a control gate electrode is accomplished by means of a modified dual-electron-injector-structure stack. This modified stack has the intervening silicon dioxide layer, which is sandwiched between silicon-rich silicon dioxide injectors, replaced by a slightly off-stoichiometric oxide containing between 1% and 6% excess atomic silicon above the normal 33% found in silicon dioxide. A brief discussion of a physical model which is believed to account for the observed phenomenon is given.

Method for manufacturing schottky barrier diode

Abstract: Disclosed is a method for manufacturing a Schottky barrier diode. An insulating film is formed on a silicon substrate of one conductivity type. The insulating film has a hole therein partially exposing the surface of the silicon substrate. Then, a polycrystalline silicon layer is formed to cover that portion of the insulating film which surrounds the contact hole, the inner wall of the contact hole, and the exposed surface portion of the silicon substrate. Thereafter, a metal layer is deposited to cover at least the polycrystalline silicon layer. The polycrystalline silicon is then alloyed with the metal to form a metal silicide layer.

A Backscattering-Channeling Study of Thermally Grown Nitride Films on Silicon

Abstract: The backscattering-channeling method using 330 keV He+ ions has been applied to a study of plasma-enhanced, thermally grown nitride films on (100) Si. The nitride films are stoichiometric Si3N4, and the interface is reconstructed with 10.5×1015 atoms/cm2 of silicon atoms, which corresponds to 3.9 atoms/string.