Showing papers on "Stuck-at fault published in 1984"

Random Pattern Testability

Abstract: A major problem in self testing with random inputs is verification of the test quality, i.e., the computation of the fault coverage. The brute-force approach of using full-fault simulation does not seem attractive because of the logic structure volume, and the CPU time encountered. A new approach is therefore necessary. This paper describes a new analytical method of computing the fault coverage that is fast compared with simulation. If the fault coverage falls below a certain threshold, it is possible to identify the ``random-pattern-resistant'' faults, modify the logic to make them easy to detect, and thus, increase the fault coverage of the random test.

Critical Path Tracing: An Alternative to Fault Simulation

Abstract: Critical path tracing determines fault detection without explicit. fault simulation. It appears to be a more efficient alternative to conventional methods.

On Random Pattern Test Length

Abstract: The testing of large logic networks with random patterns is examined. Work by previous workers for single faults is extended to a class of multiple fault situations. Not only is the problem of fault detection in the presence of nonmasking multiple faults treated, but the question of distinguishing between them is also examined. It is shown that a test that merely exposes each fault has a high probability of distinguishing between the faults. The relationships between quality, diagnostic resolution, and random pattern test length are developed. The results have application to self-test schemes that use random patterns as stimuli.

Systematic characterization of physical defects for fault analysis of MOS IC cells

Abstract: A methodology relating physical features of point defects inherent in the fabrication process to the circuit-level faulty behaviors caused by these defects is proposed. A simulation approach to support this methodology is introduced and illustrated using an example n-MOS circuit. Using this methodology, technology and layout dependent faults can be generated and ranked according to their likelihood. Using a ranked fault list, a new and more effective testing approach for MOS VLSI circuits can be developed.

STAFAN: An Alternative to Fault Simulation

Abstract: STAtistical Fault ANalysis (STAFAN) is proposed as an alternative to fault simulation of digital circuits. In this analysis, controllabilities and observabilities of circuit nodes are defined as probabilities which are estimated from signal statistics obtained from fault-free simulation. Special procedures are developed for dealing with these quantities at fanout nodes and at feedback nodes. The computed probabilities are used to derive unbiased estimates of fault detection probabilities and overall fault coverage for the given set of input vectors. Fault coverage and the undetected fault data obtained from STAFAN for actual circuits are shown to agree favorably with the fault simulator results. The computational complexity added to a fault-free simulator by STAFAN grows only linearly with the number of circuit nodes.

A unified decomposition approach for fault location in large analog circuits

Abstract: This paper deals with the problem of fault location in analog circuits The circuit under test is decomposed into subnetworks using nodes at which voltages have been measured We localize the faults to within the smallest possible subnetworks according to the final decomposition Then, further identification of the faulty elements inside the subnetworks is carried out The method is applicable to large-networks, linear or nonlinear It requires a limited-number of measurement nodes and its on-line computation requirements are minimal The method is based on checking the consistency of KCL in the decomposed circuit A measure of the effect of tolerances on the elements is introduced, and a number of examples are considered to illustrate the application of the method in both the linear and the nonlinear cases

Fault-Tolerance of Dynamic-Full-Access Interconnection Networks

Abstract: A β-network is an interconnection network composed of 2 ×2 crossbar switches called β-elements. This paper presents an analysis of the fault-tolerance of β-networks. A fault model is specified which allows β-elements to be stuck in either of their two normal states. A new connectivity property called dynamic full access (DFA) is introduced which serves as the criterion for fault tolerance. A fault is called critical if it destroys the DFA property; otherwise, it is noncritical. A minimal critical fault (MCF) is a critical fault none of whose proper subsets constitutes a critical fault. Two graph-theoretical characterizations of the minimal critical faults and the noncritical faults of a β-network are presented. Some applications of the theory developed here are discussed.

A Testable PLA Design with Low Overhead and High Fault Coverage

Abstract: A new design of testable PLA's is presented. This design has the following characteristics: it requires little extra hardware; it has very little, if any, impact on the speed of the PLA in normal operation; it has very high fault coverage (all single and multiple stuck-at faults, crosspoint faults, and all combinations thereof are detected); and it can be used for designing testable folded PLA's. This design, however, is not appropriate for built-in test.

Yield model for fault clusters within integrated circuits

Abstract: Generalized negative binomial statistics turns out to be a model of the fault distribution in very large chips or wafers with internal defect clusters. This is expected to influence large chip and full wafer redundancy requirements. Furthermore, the yield appears to be affected by an experimental dependence of the average number of faults on chip area.

Fault diagnostic distributed processing method and system

Abstract: In a distributed processing system having a plurality of interconnected subsystems of equal level, each subsystem operates to diagnose faults in other subsystems and protects its own subsystem based on the diagnosis of the faults of the other subsystems. The subsystems may be network control processors connected to common signal transmission lines, each of which carries major and minor loop check messages used to detect the faults in the other network control processors and constitutes a bypass route to protect its own unit when the fault occurs. If a transient fault occurs in the systems, an indication of the degree of the transient fault is stored and a possibility that the transient fault will change to a permanent fault is determined based on a time variation of the degree of the fault. If it is determined that the transient fault will change to a permanent fault, it is indicated to a man-machine system. In this manner, a loop transmission system which can be readily prediction-diagnosed for a fault is provided. In a second embodiment, means for calculating a feedback rate of a signal sent out to the transmission line and means for calculating the degree of fault on the transmission line based on the feedback rate calculated by the calculation means are provided.

Spectral Fault Signatures for Single Stuck-At Faults in Combinational Networks

Abstract: A method is described for the derivation of fault signatures for the detection of stuck-at faults in single-output combinational networks. These signatures consist of a set of values derived from the network. Any single stuck-at fault causes at least one value to change. The fault signatures developed are a generalization of syndrome testing. The technique is developed in the Rademacher-Walsh spectral domain but is easily implemented using conters and basic gates.

An Experimental MOS Fault Simulation Program CSASIM

Abstract: A prototype version of a new switch-level fault simulator for digital MOS IC's is described. The simulation program, which is called CSASIM, analyzes CSA (connector-switch-attenuator) circuit models using multiple logic values. A novel method of signal evaluation is employed, based on the super-position of bidirectional static and dynamic signals. CSASIM also allows efficient simulation of many different fault types, including stuck-at-constant, open-circuit, short-circuit, and delay faults. The internal structure and fault-simulation mechanisms of the simulator are discussed in this paper.

Fault Modeling for Digital MOS Integrated Circuits

Abstract: A new fault modeling technique aimed at efficient simulation and test generation for complex digital MOS IC's is described. It is based on connector-switch-attenuator (CSA) analysis, which employs purely digital models of switching transistors, resistive/capacitive elements, and their associated signals. The use of CSA networks to model the digital behavior, both static and dynamic, of MOS circuits is reviewed. It is shown that most physical failure modes in such circuits, including short-circuit, open-circuit, and delay faults, can be modeled more efficiently by CSA models than by conventional approaches. A generalized single stuck-line (GSSL) fault model is suggested as a uniform and practical method for fault representation.

Fault tolerant controller

Abstract: A controller operable in a normal mode of operation to control an output device in response to a sensed condition includes means for detecting a fault in the controller or output device. Means are responsive to the fault detecting means for controlling the output device in a failsafe mode of operation wherein the output device is safely operated without regard to the sensed condition when a fault is detected. Means responsive to the fault detecting means causes a return to the normal mode of operation only if the existence of the fault can be detected while in the failsafe mode and the fault ceases to exist during such time.

On CMOS totally self-checking circuits

Abstract: To model faults in CMOS VLSI digital circuits, an augmented fault model comprising FET stuck-open and stuck-on faults, in addition to line stuck-at faults, is being used. Recently, it was discovered that delays in CMOS circuits under test. could invalidate tests derived by neglecting such delays. Thus, it is necessary to reinvestigate most of the existing design and test methods which are based on stuck-at fault models while considering CMOS digital circuits. One of the areas that requires such a revisit is that of self-checking circuits, due to the fact that the self-testing property of these circuits is dependent upon fault model adopted. In this paper, the problem of the design of CMOS totally self-checking checkers is considered when arbitrary delays in the circuit under test are allowed. Designs using both full CMOS and domino gates are considered. Several design procedures given earlier for totally self-checking checkers are analyzed under the augmented fault model. Adequate design rules are derived for some of the checkers, such that the self-testing property is retained for the augmented fault model.

On a theory of t-fault diagnosable analog systems

Abstract: The theory of t -fault diagnosable systems initiated by Preparata et al. has been studied for applications to automatic self-testing of large scale digital systems. Recently, Amin introduced another variation of their model. In this paper, we show that this model has an application to analog fault diagnosis. We further specialize Amin's model to obtain characterization theorems which are much more transparent and also are more suitable for this particular application.

Integrated circuit input-output diagnostic system

Abstract: Input and output fault monitoring circuits for determining the presence of integrated circuit chip open connections at the input and output pads of each circuit on a chip. The input fault monitoring circuit operates on the principle that if there is no input signal from the input pad throughout the known duty cycle or frequency of the input circuit, a defect, such as an open circuit interconnect, has occurred. The output fault monitoring circuit generates a signal through a dummy circuit connected to the output circuit which has a time delay intermediate that of the output circuit operating into a connected output pad and that of the output circuit when operating into a disconnected pad. Thus, the time of arrival of the dummy circuit signal in relation to that of the actual output signal is used to indicate the presence or absence of a disconnected output pad.

An analysis of the multiple fault detection capabilities of single stuck-at fault test sets

Abstract: Multiple fault detection using single stuck-at fault test sets is considered. The 74LS181 4-bit ALU is analyzed using 10 test sets varying widely in length and method of generation. The simulation results demonstrate significantly higher multiple fault coverage than anticipated by previous studies. It is shown that single stuck-at fault test sets can provide suitably high fault coverage for practical circuits with multiple outputs and reconvergent internal fanout.

System for detecting a program execution fault

Abstract: A system for detecting a fault in the program execution of a programmed digital signal processing system is disclosed. The fault detection system may include a plurality of monitoring devices for monitoring the execution of a plurality of program portions of the programmed processor and for generating a fault signal in response to a detected faulty program execution condition. Logic circuitry is included for restarting of suspending any fault signal generation rendered by the plurality of monitoring devices. Further included is circuitry for limiting the number of automatic restarts to a predetermined number which avoids continuous cycling between fault signal generation and reset. Still further, the predetermined number of fault generations must occur within a given time interval which may be set and from time to time changed by the program instructions, for example. A fault indication or alarm is not provided until the predetermined number of fault signal generations has occurred within the predetermined time interval. While in the alarm state, the monitoring devices are inhibited, rendering the fault detection system inoperative, and the program execution of the programmed processor is sustained in an initial state. The fault detection system further includes a power supply monitor which disables the logic circuitry when the power supply of the program processor is below a predetermined level to render the fault detection system inoperative and to sustain the program execution at its initial state.

The inadequacy of the stuck-at fault model for testing mos lsi circuits: a review of mos failure mechanisms and some implications for computer-aided design and test of mos lsi circuits

Abstract: The stuck-at fault model is widely used as the basis for automatic test pattern generation in digital circuit testing, for example the D-algorithm. However, there have been growing doubts over the ability of the model to cover faults that occur in MOS LSI circuits. The paper consists of a review of the failure mechanisms that produce faults in MOS LSI circuits, a discussion of the problems that arise when using the stuck-at fault model to test MOS LSI circuits and a set of guidelines for the future development of computer-aided design and test of such circuits.

Fault Tolerance in Continuous Process Control

Abstract: Increasing the reliability of continuous process control systems means choosing a fault tolerance technique that matches computer hardware capabilities, as well as applications.

Fault simulation at the architectural level

Abstract: We have developed a method for fault simulation at the architectural level. This requires first an architectural level fault model. We have developed one based partially on the fault model proposed by Thatte and Abraham. An experiment with this fault model was done with a shift register described at both the architectural and gate levels. The resulting architectural level fault coverage tracked the gate level fault coverage obtained using the traditional stuck-at fault model. The next step was the development of an architectural level fault simulator, and an associated simulation model of the eight bit WE® 8000 microprocessor. The model was written in C, and 2512 faults were inserted in the model. A previously written test for the microprocessor was applied, and a fault coverage of 95% was obtained.

Process and device for determining a parameter associated with a faulty electric conductor, using a composite monitoring signal

Abstract: Method and apparatus for determining, at a measurement point in a faulty conductor of electrical energy, a fault parameter such as the distance between the point of measurement and such fault or the direction of such fault. As a signal of a fault current, the device utilizes a signal I pa formed by a linear combination of a signal representative of homopolar current and a signal representative of an inverse current associated with a fault. The invention is particularly applicable in the case of networks having at the point of measurement an insensitivity to homopolar current or to inverse current.

A Diagnosis Algorithm for the BGM System Level Fault Model

Abstract: A ?diagnosable system is a system in which all faults may be identified from the test results, provided that the number of faults does not exceed ?. In this correspondence we present an algorithm that may be used for the diagnosis of the system level BGM fault model proposed by Barsi, Grandoni, and Maestrini, whenever the system is ?-diagnosable and the number of faults is at most ?.

Sequential Fault Diagnosis of Modular Systems

Abstract: In this correspondence, we present an algorithm based on information theoretic concepts for the design of efficient sequential fault diagnosis experiments for permanent faults in modular systems.

ATWIG, an automatic test pattern generator with inherent guidance

Abstract: ATWIG is a heuristic automatic test pattern generator (ATG) which employs various types of guidance based on controllability and observability (C/O) measures and various heuristics fault' path and fault selection. Guided inconsistent path sensitization, a new method for low cost ATG, is discussed. A concurrent fault simulator is used to verify the generated test patterns. Experimental results show that ATWIG is very efficient in generating test patterns for combinational and low sequential circuits. Further improvements and heuristics are necessary for automatic test generation of highly sequential circuits. The relationship between C/O cost measures and A TWIG cost is discussed.

Functional testing of EPROMs

Abstract: The aim of this paper is to develop a testing scheme for EPROM memories. The starting point is the assumed general model of EPROM memory logic structure. For this model, an adequate fault model is developed. The class of faults taken into consideration includes faults in input-output buffers, faults in address decoding circuitry, and faults in memory cell arrays. The proposed testing scheme makes possible the detection of all faults included in the assumed fault model. This scheme takes into account technological and economic aspects. The method proposed is illustrated by detailed solutions for the 2716 EPROM memory.

Stuck-At Fault Tests in the Presence of Undetectable Bridging Faults

Abstract: Undetectable bridging faults between two arbitrary leads, which may produce feedback loops, in a unate two-level irredundant AND-OR network are anlyzed and their effect on stuck-at fault detection tests is explored. As a result, any complete test set for single stuck-at faults proves to still remain valid in the presence of undetectable bridging faults.