Showing papers on "Stuck-at fault published in 1994"

Alarm correlation and fault identification in communication networks

Abstract: Presents an approach for modeling and solving the problem of fault identification and alarm correlation in large communication networks. A single fault in a large network may result in a large number of alarms, and it is often very difficult to isolate the true cause of the fault. This appears to be one of the most important difficulties in managing faults in today's networks. The problem may become worse in the case of multiple faults. The authors present a general methodology for solving the alarm correlation and fault identification problem. They propose a new alarm structure, propose a general model for representing the network, and give two algorithms which can solve the alarm correlation and fault identification problem in the presence of multiple faults. These algorithms differ in the degree of accuracy achieved in identifying the fault, and in the degree of complexity required for implementation. >

Using heavy-ion radiation to validate fault-handling mechanisms

Abstract: Fault injection is an effective method for studying the effects of faults in computer systems and for validating fault-handling mechanisms. The approach presented involves injecting transient faults into integrated circuits by using heavy-ion radiation from a Californium-252 source. The proliferation of safety-critical and fault-tolerant systems using VLSI technology makes such attempts to inject faults at internal locations in VLSI circuits increasingly important. >

ATPG for heat dissipation minimization during test application

Abstract: A new ATPG algorithm has been proposed that reduces average heat dissipation (between successive test vectors) during test application. The objective is to permit safe and inexpensive testing of low power circuits and bare dies that would otherwise require expensive heat removal equipment for testing at high speeds. Three new functions, namely transition controllability, observability and test generation costs, have been defined. It has been shown that the transition test generation cost is the minimum number of transitions required to test the corresponding stuck-at fault in fanout free circuits. This cost function is used for target fault selection while the other two functions are used to guide the backtrace and objective selection procedures of PODEM. The tests generated by the proposed ATPG decrease heat dissipation during test application by a factor of 2-23 for benchmark circuits.

Development of a new fault location system for multi-terminal single transmission lines

Abstract: Conventional fault location systems which use one-terminal AC voltages and currents are difficult to apply to multi-terminal power systems. This paper discusses a new fault location system for multi-terminal single transmission lines. Asynchronous sampling at each terminal is preferred in order to simplify the transmission equipment and an algorithm for synchronizing the asynchronous sampling data is presented. Another algorithm is presented which converts the original multi-terminal power system by progressive conversion to a system with one fewer terminals to arrive at a 2-terminal system containing the fault. An effective fault locating system can be constructed by combining these algorithms with existing reactive power locating operations. EMTP simulation results are presented. >

Transient fault tolerance in digital systems

Abstract: It is hard to shield systems effectively from transient faults (fault avoidance techniques). So some other means must be employed to assure appropriate levels of transient fault tolerance (insensitivity to transient faults). They are based on fault-masking and fault recovery ideas. Having analyzed this problem, the author identifies critical design points and outlines some practical solutions that refer to efficient on-line detectors (detecting errors during the system operation) and error handling procedures. This framework provides a basis for understanding transient fault problems in digital systems. It can be helpful in selecting optimum techniques to mask or eliminate transient fault effects in developed systems. >

An approach to the analysis and detection of crosstalk faults in digital VLSI circuits

Abstract: The continuous reduction of the device size in integrated circuits and the increase in the switching rate cause parasitic capacitances between conducting layers to become dominant and cause logic errors in the circuits. Therefore, capacitive couplings can be considered as potential logic faults. Classical fault models do not cover this class of faults. This paper presents a logic level characterization and fault model for crosstalk faults. The authors also show how a fault list of such faults can be generated from the layout data, and give an automatic test pattern generation procedure for them. >

Analytical fault modeling and static test generation for analog ICs

Abstract: Static tests are key in reducing the current high cost of testing analog and mixed-signal ICs. A new DC test generation technique for detecting catastrophic failures in this class of circuits is presented. To include the effect of tolerance of parameters during testing, the test generation problem is formulated as a minimax optimization problem, and solved iteratively as successive linear programming problems. An analytical fault modeling technique, based on manufacturing defect statistics is used to derive the fault list for the test generation. Using the technique presented here an efficient static test set for analog and mixed-signal ICs can be constructed, reducing both the test time and the packaging cost.

Method and apparatus for detecting faults in a computer network

Abstract: The present invention is for a fault detecting system for a computer network comprising a plurality of computer systems which are placed apart and interconnected by a communication network, and a central computer system monitors faults in the network. The central computer system stores fault information which is transmitted from a plurality of computer systems and judges whether the information indicates a fault occurring for a slight fault or for a serious fault based on the length of the duration of the fault, and display means performs the alarm display for a case of a serious fault and does not display for a case of a slight fault. As a result, the central computer system effectively detects faults in a computer network in which a plurality of computer systems are interconnected with the central computer system by means of a monitoring system that automatically distinguishes serious faults from slight faults.

Automated fault diagnosis using a discrete event systems framework

Abstract: Automated fault diagnosis for a complex system is often a very difficult task. Before proceeding with fault diagnosis, we need to make sure that the given sensor configuration has the capability of assisting the diagnostician perform the fault diagnosis in an efficient manner. In this paper, we present some results on the testability of a system whose fault behavior is modeled by a nondeterministic automaton. We discuss the issues pertaining to testability such as optimal sensor configuration and the infimal partition of the fault space. We also present a manufacturing process example to illustrate the application of the results presented in the paper. >

Design of an efficient weighted random pattern generation system

Abstract: This paper describes the design of an efficient weighted random pattern system. The performance of the system is measured by the number of weight sets and the number of weighted random patterns required for high fault coverage. Various heuristics that affect the performance of the system are discussed and an experimental evaluation is provided.

Expert system framework for fault detection and fault tolerance in robotics

Abstract: Fault tolerance is of increasing importance for modern robots. The ability to detect and tolerate failures enables robots to effectively cope with internal failures and continue performing assigned tasks without the need for immediate human intervention. To monitor fault tolerance actions performed by lower level routines and to provide higher level information about a robot;s recovery capabilities, we present an expert system and critic which together form a novel and intelligent fault tolerance framework integrating fault detection and tolerance routines with dynamic fault tree analysis. A higher level, operating system inspired critic layer provides a buffer between robot fault tolerant operations and the user. The expert system gives the framework the modularity and flexibility to quickly convert between a variety of robot structures and tasks. It also provides a standard interface to the fault detection and tolerance software and a more intelligent means of monitoring the progress of failure and recovery throughout the robot system. The expert system further allows for prioritization of tasks so that recovery can take precedence over less pressing goals. Fault trees are used as a standard database to reveal the components essential to fault detection and tolerance within a system and detail the interconnection between failures in the system. The trees are also used quantitatively to provide a dynamic estimate of the probability of failure of the entire system or various subsystems.

Apparatus and method for automatic test generation and fault simulation of electronic circuits, based on programmable logic circuits

Abstract: An electronic circuit test vector generation and fault simulation apparatus is constructed with programmable logic devices (PLD) or field programmable gate array (FPGA) devices and messaging buses carrying data and function calls. A test generation and fault simulation (TGFS) comparator is implemented in the PLD or FPGA consisting of a partitioned sub-circuit configuration, and a multiplicity of copies of the same configuration each with a single and different fault introduced in it. The method for test vector generation involves determining test vectors that flag each of the fault as determined by a comparison of the outputs of the good and single fault configurations. Further the method handles both combinational as well as sequential type circuits which require generating a multiplicity of test vectors for each fault. The successful test vectors are now propagated to the inputs and outputs of the electronic circuit, through driver and receiver sub-circuits, modeled via their corresponding TGFS comparators, by means of an input/output/function messaging buses. A method of fault simulation utilizing the TGFS comparators working under a fault specific approach determines the fault coverage of the test vectors.

Fault impedance estimation algorithm for digital distance relaying

Abstract: Fault impedance is one of the major parameters that must be estimated accurately in digital distance relaying application. In this paper, a new algorithm is proposed based on symmetrical components theory. The proposed algorithm has computational advantage over previously suggested symmetrical components based algorithms. A procedure for applying shunt fault conditions to the sequence equations to estimate fault impedance of the protected transmission line is discussed. The Alternative Transient Program (ATP) that is available on personal computers was used in evaluating the proposed algorithm. ATP models a power system and simulates many fault conditions on a selected transmission line. Fault data obtained were used in calculating fault impedance using the proposed algorithm. Fault impedance estimates were inserted in relay characteristics to determine suitability of the proposed algorithm for first zone distance protection. Sample results of these studies which show stable fault distance estimates are presented and discussed in the paper. >

Fault detection and input stimulus determination for the testing of analog integrated circuits based on power-supply current monitoring

Abstract: A new method for the testing and fault detection of analog integrated circuits is presented. Time-domain testing followed by spectral analysis of the power-supply current is used to detect both DC and AC faults. Spectral analysis is applied since the tolerances on the circuit parameters make a direct comparison of waveforms impossible. For the fault detection a probabilistic decision rule is proposed based on a multivariate statistical analysis. Since no extra testing pin is needed and the on-line calculation effort is small, the method can be used for wafer-probe testing as well as final production testing. In addition, a methodology for the selection of the input stimulus is presented that improves the test-ability. Examples demonstrate the efficiency and the effectiveness of the algorithms.

DEFINE: a distributed fault injection and monitoring environment

Abstract: This paper presents a distributed fault injection and monitoring environment (DEFINE) as a tool to evaluate system dependability, to investigate fault propagation, and to validate fault-tolerant mechanisms. DEFINE can inject both hardware faults (hardware-induced software errors) and software faults into any process running in a distributed system, either in user mode or in supervisor mode, and monitor the fault impact and propagation in software systems and among machines. It employs two fault injection techniques: (i) using hardware clock interrupts to control the time of fault injection and activation, and (ii) using software traps to inject all the faults except communication faults and memory faults in the data/stack segment. Experiments on six Sun SPARCstations to study the system behavior under faults are conducted to demonstrate the application of DEFINE.

Analogue fault simulation based on layout dependent fault models

Abstract: A testability analysis procedure for complex analogue circuits is presented based on layout dependent fault models extracted from process defect statistics. The technique has been applied to a mixed-signal phase locked loop circuit and a number of test methodologies have been evaluated including the existing production test. It is concluded that the fault coverage achieved by this test can be improved by the use of a supplementary test based on power supply variations.

Multifrequency testability analysis for analog circuits

Abstract: Testability analysis in analog circuits is an important task and a desirable approach for producing testable complex systems. In past years, most of the testability evaluation methods presented were based on measures of the degree of solvability of the fault diagnosis equations. In this paper, we study the testability of analog circuits in the frequency domain by introducing the analog fault observability concept. The proposed algorithm indicates the set of adequate test frequencies and test nodes to increase fault observability. We analyze the case of single fault and of double and multiple faults. Concepts such as fault masking, fault dominance, fault equivalence and non observable fault in analog circuits are defined and then used to evaluate testability. Finally, some experimental results are provided. >

CMOS bridging fault modeling

Abstract: This paper analyses the general problem of the determination of the intermediate potentials created by a bridging fault. The analyses is made taking into account the bridge resistance value. It is shown that the fault is detectable as a logic error for a given range of bridge resistance values. But, in this range, the logic faulty value is independent of the bridge resistance value. A general electrical model which can be used to determine if a particular structure of transistors gives an intermediate voltage which is higher or lower than a given threshold voltage is proposed. A global procedure to simulate bridging fault is given. By using the proposed equations and model no SPICE simulation is required. >

Fast timing simulation of transient faults in digital circuits

Abstract: Transient fault simulation is an important verification activity for circuits used in critical applications since such faults account for over 80% of all system failures. This paper presents a timing level transient fault simulator that bridges the gap between electrical and gate-level transient fault simulators. A generic MOS circuit primitive and analytical solutions of node differential equations are used to perform transistor level simulation with accurate MOS-FET models. The transient fault is modeled by a piecewise quadratic injected current waveform; this retains the electrical nature of the transient fault and provides SPICE-like accuracy. Detailed comparisons with SPICE3 show the accuracy of this technique and speedups of two orders of magnitude are observed for circuits containing up to 2000 transistors. Latched error distributions of the benchmark circuits are also provided.

Fault diagnosis in systems using fuzzy logic

Abstract: Two tasks of fault detection in linear dynamical systems are addressed in this paper. On one hand, to estimate residuals, a system described by a model with some deviations in parameters or unknown input disturbances is considered. In such a situation, sensor fault detection using classical methods is not very efficient. In order to solve this problem, an adaptive thresholding approach using fuzzy logic is proposed. On the other hand, to locate faults, a fuzzy logic technique is put in place of usual classical logic used with dedicated observer scheme. >

Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0

Abstract: Simulation-based test vector generators require much less computer time than deterministic ATPG but they generate longer test sequences and sometimes achieve lower fault coverage. This is due to the divergence in the search process. In this paper, we propose a correction technique for simulation-based ATPG. This technique is based on identifying the diverging state and on computing a fault cluster (faults close to each other). A set of candidate faults from the cluster is targeted with a deterministic ATPG and the resulting test sequence is used to restart the search process of the simulation-based technique. This above process is repeated until all faults are detected or proven to be redundant/untestable. The program implementing this approach has been used to generate tests with very high fault coverage, and runs about 10 times faster than traditional deterministic techniques with very good test quality in terms of test length and fault coverage.

On microprocessor error behavior modeling

Abstract: A microprocessor error behavior function (EBF) is introduced, mapping faults into errors on the functional level. The errors are obtained using a functional model of the processor. By applying the EBF to a fault and instruction distribution, it is possible to obtain the corresponding error distribution. A case study is described, in which (i) the EBFs for simulated bit-flip and pin-level faults are designed and used to compare the bit-flip and pin-level fault models, and (ii) the obtained error distribution for the bit-flip faults is used in an error injection experiment on the functional level to emulate these faults. For the processor used in the case study, it was found that only 9-12% of the bit-flip faults could be emulated using pin-level faults, while a tentative evaluation of the possibility to emulate bit-flip faults with software-implemented fault injection showed that 98-99% could be emulated. Finally, the results of the emulated bit-flip errors corresponded well to the real results obtained using bit-flip faults, thus indicating that the injected errors are good approximations of the faults. >

Low-cost redundancy identification for combinational circuits

Abstract: This paper presents a novel fault independent algorithm for redundancy identification (FIRE) in combinational circuits. The algorithm is based on a simple concept that a fault which requires an illegal combination of values as a necessary condition for its detection is undetectable and hence redundant. It uses implications to find a subset of such faults whose detection requires conflicts on certain lines in the circuit. Our results on benchmark circuits indicate that we find a large number of redundancies, much faster when compared to a test-generation-based approach for redundancy identification. >

Hierarchical pattern faults for describing logic circuit failure mechanisms

Abstract: A method and system (12) for defining and using a pattern fault file (15) having a static pattern fault and/or a dynamic pattern fault A static pattern fault is represented as a list of required excitation nodes and their values, as well as a fault propagation point The fault propagation point is defined to be a net or node in a circuit to be tested where the defect's effect first appears once it has been excited A dynamic pattern fault adds to this structure an initial value list of nodes and their required initial values The dynamic-pattern fault is employed to advantage when a two pattern sequence is required to excite a specific defect Logical combinations (AND/OR) of specified pin excitations and fault propagation points may be employed The excitation value list, the initial value list and the propagation point can include any of the following: input pins of an entity; output pins of the entity; nets inside of the entity; pins on usage blocks inside the entity; nets inside a usage of a lower entity; and pins inside a usage of a lower level entity The method and system also provide a capability to define pattern faults for each entity in a hierarchial circuit definition, and thus provides a mechanism to define pattern faults for specific cells in a cell technical library (13)

Logic synthesis techniques for reduced area implementation of multilevel circuits with concurrent error detection

Abstract: This paper presents new logic synthesis techniques for generating multilevel circuits with concurrent error detection based on a parity-check code scheme that can detect all errors caused by single stuck-at faults. These synthesis techniques fully automate the design process and allow for a better quality result than previous methods thereby reducing the cost of concurrent error detection. An algorithm is described for selecting a good parity-check code for encoding the outputs of a circuit. Once the code has been chosen, a new procedure called structure-constrained logic optimization is used to minimize the area of the circuit as much as possible while still using a circuit structure that ensures that single stuck-at faults cannot produce undetected errors. The implementation that is generated is path fault secure and when augmented by a checker forms a self-checking circuit. Results indicate that self-checking multilevel circuits can be generated which require significantly less area than using duplication.

Design-for-Testability for Path Delay Faults in Large Combinational Circuits Using Test-Points

Abstract: We present a method for test-point insertion in large combinational circuits, to increase their path delay fault testability. Using an appropriate test application scheme with multiple clock periods, a test-point on a line g divides the set of paths through g for testing purposes into a subset of paths from the primary inputs up to g, and a subset of paths from g to the primary outputs. Each one of these subsets can be tested separately. The number of paths that need to be tested directly is thus reduced. Test-point insertion is done to reduce the number of paths, using a time-efficient procedure. Indirectly, it also reduces the number of tests and renders untestable paths testable. Experimental results are presented to demonstrate the effectiveness of the method proposed in increasing the testability of large benchmark circuits, and to demonstrate the overheads involved.

Three-pattern tests for delay faults

Abstract: To improve the quality of CMOS digital circuits, more complex fault models than single stuck-at have been proposed. This paper focuses on the effect of inaccurate delay modeling on delay fault testing. It is shown that accurate delay models are needed for effective delay fault testing. This is particularly important for large timing optimized circuits with many paths. Limitations of the path delay fault model are shown, and even the assumption that 2-pattern tests are sufficient for delay testing is shown to have limitations. >

System and method for improving fault coverage of an electric circuit

Abstract: The present invention is a method and system which determine signal probability and transfer probability for each node in a netlist describing an electrical circuit; determine, using the signal probability and transfer probability, a fault detection probability for each node; and, using the fault detection probabilities, determine overall fault coverage of the electrical circuit described in the netlist. The method and system of the present invention then, using the fault coverage data, heuristically determine a set of testpoints to be inserted into the netlist which increase the overall fault coverage of the electrical circuit above a predetermined value.