Showing papers on "Stuck-at fault published in 2011"

Wavelet-based protection strategy for DC faults in multi-terminal VSC HVDC systems

Abstract: A new protection algorithm for DC line faults in multi-terminal high voltage DC (MTDC) systems is proposed in this study A four-terminal MTDC model is used to investigate fault behaviour and detection using the simulation program PSCAD/EMTDC The simulation results are post-processed using Matlab The fault clearing must be done very rapidly, to limit the effect of the fault on neighbouring DC lines because of the rapid increase in DC current However, before clearing the line, the fault location must be detected as soon as possible A rapid fault location detection algorithm is therefore needed, preferably without communication The protection algorithm proposed in this study uses wavelet analysis to detect the fault location based on local measurements The protection algorithm consists of three independent fault criteria, of which two use wavelet analysis The third criterion is based on a detection method in the time domain The latter is an additional detection method independent of wavelet analysis Using a two out of three selection criteria results in an increased reliability of the whole protection algorithm The final objective is to implement a protection algorithm which allows to detect a DC fault within 1 ms without using communication between the participating converter stations

Differential fault analysis of the advanced encryption standard using a single fault

Abstract: In this paper we present a differential fault attack that can be applied to the AES using a single fault. We demonstrate that when a single random byte fault is induced at the input of the eighth round, the AES key can be deduced using a two stage algorithm. The first step has a statistical expectation of reducing the possible key hypotheses to 232, and the second step to a mere 28.

A Probabilistic Fault Detection Approach: Application to Bearing Fault Detection

Abstract: This paper introduces a method to detect a fault associated with critical components/subsystems of an engineered system. It is required, in this case, to detect the fault condition as early as possible, with specified degree of confidence and a prescribed false alarm rate. Innovative features of the enabling technologies include a Bayesian estimation algorithm called particle filtering, which employs features or condition indicators derived from sensor data in combination with simple models of the system's degrading state to detect a deviation or discrepancy between a baseline (no-fault) distribution and its current counterpart. The scheme requires a fault progression model describing the degrading state of the system in the operation. A generic model based on fatigue analysis is provided and its parameters adaptation is discussed in detail. The scheme provides the probability of abnormal condition and the presence of a fault is confirmed for a given confidence level. The efficacy of the proposed approach is illustrated with data acquired from bearings typically found on aircraft and monitored via a properly instrumented test rig.

Building management system with fault analysis

Abstract: A controller for a building management system is configured to analyze faults in the building management system. The controller detects a fault in the building management system by evaluating data of building management system using a system of rules. The controller determines a conditional probability for each of a plurality of possible fault causes given the detected fault. The controller determines the most likely fault cause by comparing the determined probabilities and electronically reports the most likely fault cause.

An In-depth and Black-box Characterization of the Effects of Clock Glitches on 8-bit MCUs

Abstract: The literature about fault analysis typically describes fault injection mechanisms, e.g. glitches and lasers, and cryptanalytic techniques to exploit faults based on some assumed fault model. Our work narrows the gap between both topics. We thoroughly analyse how clock glitches affect a commercial low-cost processor by performing a large number of experiments on five devices. We observe that the effects of fault injection on two-stage pipeline devices are more complex than commonly reported in the literature. While injecting a fault is relatively easy, injecting an exploitable fault is hard. We further observe that the easiest to inject and reliable fault is to replace instructions, and that random faults do not occur. Finally we explain how typical fault attacks can be mounted on this device, and describe a new attack for which the fault injection is easy and the cryptanalysis trivial.

Further improvements on impedance-based fault location for power distribution systems

Abstract: In this study, further improvements regarding the fault location problem for power distribution systems are presented. The proposed improvements relate to the capacitive effect consideration on impedance-based fault location methods, by considering an exact line segment model for the distribution line. The proposed developments, which consist of a new formulation for the fault location problem and a new algorithm that considers the line shunt admittance matrix, are presented. The proposed equations are developed for any fault type and result in one single equation for all ground fault types, and another equation for line-to-line faults. Results obtained with the proposed improvements are presented. Also, in order to compare the improvements performance and demonstrate how the line shunt admittance affects the state-of-the-art impedance-based fault location methodologies for distribution systems, the results obtained with two other existing methods are presented. Comparative results show that, in overhead distribution systems with laterals and intermediate loads, the line shunt admittance can significantly affect the state-of-the-art methodologies response, whereas in this case the proposed developments present great improvements by considering this effect.

A Hybrid Framework for Fault Detection, Classification, and Location—Part I: Concept, Structure, and Methodology

Abstract: Bridging the gap between the theoretical modeling and the practical implementation is always essential for fault detection, classification, and location methods in a power transmission-line network. In this paper, a novel hybrid framework that is able to rapidly detect and locate a fault on power transmission lines is presented. The proposed algorithm presents a fault discrimination method based on the three-phase current and voltage waveforms measured when fault events occur in the power transmission-line network. Negative-sequence components of the three-phase current and voltage quantities are applied to achieve fast online fault detection. Subsequently, the fault detection method triggers the fault classification and fault-location methods to become active. A variety of methods-including multilevel wavelet transform, principal component analysis, support vector machines, and adaptive structure neural networks-are incorporated into the framework to identify fault type and location at the same time. This paper lays out the fundamental concept of the proposed framework and introduces the methodology of the analytical techniques, a pattern-recognition approach via neural networks and a joint decision-making mechanism. Using a well-trained framework, the tasks of fault detection, classification, and location are accomplished in 1.28 cycles, significantly shorter than the critical fault clearing time.

Wide-Area Backup Protection Algorithm Based on Fault Component Voltage Distribution

Abstract: A new wide-area backup protection algorithm based on the fault component voltage distribution is proposed in this paper. It is helpful to overcome the problems of complex setting and maloperation under flow transfer of conventional backup protection. The measured values of fault component voltage and current at one terminal of the transmission line are applied to estimate the fault component voltage at the other terminal. Then, the fault element can be identified by the ratio between the measured values and the estimated values. In addition, the speed of fault element identification can be accelerated by a faulted area detection scheme. The proposed method has the advantage of easy setting and low requirement for synchronized wide-area data. The studies performed on the IEEE 39-bus system validate the proposed algorithm under various faults and flow transfer.

A Simple Real-Time Fault Signature Monitoring Tool for Motor-Drive-Embedded Fault Diagnosis Systems

Abstract: The reference frame theory constitutes an essential aspect of electric machine analysis and control. In this study, apart from the conventional applications, it is reported that the reference frame theory approach can successfully be applied to real-time fault diagnosis of electric machinery systems as a powerful toolbox to find the magnitude and phase quantities of fault signatures with good precision as well. The basic idea is to convert the associated fault signature to a dc quantity, followed by the computation of the signal's average in the fault reference frame to filter out the rest of the signal harmonics, i.e., its ac components. As a natural consequence of this, neither a notch filter nor a low-pass filter is required to eliminate fundamental component or noise content. Since the incipient fault mechanisms have been studied for a long time, the motor fault signature frequencies and fault models are very well-known. Therefore, ignoring all other components, the proposed method focuses only on certain fault signatures in the current spectrum depending on the examined motor fault. Broken rotor bar and eccentricity faults are experimentally tested online using a TMS320F2812 digital signal processor (DSP) to prove the effectiveness of the proposed method. In this application, only the readily available drive hardware is used without employing additional components such as analog filters, signal conditioning board, external sensors, etc. As the motor drive processing unit, the DSP is utilized both for motor control and fault detection purposes, providing instantaneous fault information. The proposed algorithm processes the measured data in real time to avoid buffering and large-size memory needed in order to enhance the practicability of this method. Due to the short-time convergence capability of the algorithm, the fault status is updated in each second. The immunity of the algorithm against non-ideal cases such as measurement offset errors and phase unbalance is theoretically and experimentally verified. Being a model-independent fault analyzer, this method can be applied to all multiphase and single-phase motors.

Simple Fault Diagnosis Based on Operating Characteristic of Brushless Direct-Current Motor Drives

Abstract: In this paper, a simple fault diagnosis scheme for brushless direct-current motor drives is proposed to maintain control performance under an open-circuit fault. The proposed scheme consists of a simple algorithm using the measured phase current information and detects open-circuit faults based on the operating characteristic of motors. It requires no additional sensors or electrical devices to detect open-circuit faults and can be embedded into the existing drive software as a subroutine without excessive computation effort. The feasibility of the proposed fault diagnosis algorithm is proven by simulation and experimental results.

Hilbert-Transform-Based Transient/Intermittent Earth Fault Detection in Noneffectively Grounded Distribution Systems

Abstract: Conventional relaying algorithms are mostly based on phasor computation. Since it is difficult to obtain accurate phasor results in fast transient situations, most of the feeder relays fail to correctly respond to transient/intermittent earth faults, which are, however, frequent fault cases in distribution systems. This paper presents a novel approach for fault detection and direction determination for these transient/intermittent faults. The basic idea is to extract the fault direction using the instantaneous power's direction. The instantaneous power is obtained by using Hilbert transform. The proposed direction element inherently utilizes the high-frequency components of the transient fault signals at a conventional sampling rate. Together with an intermittence detection algorithm, a scheme for transient/intermittent earth fault detection has been proposed. It has been implemented as a prototype relay. Electromagnetic Transients Program tests as well as physical model tests have proved the effectiveness of the proposed scheme.

Robust Fault Detection for Networked Systems with Distributed Sensors

Abstract: This paper is concerned with the robust fault detection problem for a class of discrete-time networked systems with distributed sensors. Since the bandwidth of the communication channel is limited, packets from different sensors may be dropped with different missing rates during the transmission. Therefore, a diagonal matrix is introduced to describe the multiple packet dropout phenomenon and the parameter uncertainties are supposed to reside in a polytope. The aim is to design a robust fault detection filter such that, for all probabilistic packet dropouts, all unknown inputs and admissible uncertain parameters, the error between the residual (generated by the fault detection filter) and the fault signal is made as small as possible. Two parameter-dependent approaches are proposed to obtain less conservative results. The existence of the desired fault detection filter can be determined from the feasibility of a set of linear matrix inequalities that can be easily solved by the efficient convex optimization method. A simulation example on a networked three-tank system is provided to illustrate the effectiveness and applicability of the proposed techniques.

Distributed Fault Accommodation for a Class of Interconnected Nonlinear Systems With Partial Communication

Abstract: Motivated by applications related to large-scale and complex systems, there has recently been an increased interest in the design and analysis of distributed control and fault accommodation schemes. This note presents a distributed fault detection and accommodation design method for a class of nonlinear interconnected subsystems. A fault may occur in the subsystems local dynamics as well as in the interconnections between the subsystems. The subsystems exchange state information according to a tracking error based communication protocol, where each subsystem transmits its state information only when its tracking error exceeds a certain threshold. The robustness of the distributed fault detection scheme and the closed-loop stability properties of the fault accommodation design are established through a rigorous analysis.

A Novel UHV/EHV Transmission-Line Pilot Protection Based on Fault Component Integrated Impedance

Abstract: Based on the ratio of the sum of the fault component voltage phasors across the two terminals in the transmission line to the sum of the current phasors through the same line, which is defined as fault component integrated impedance in this paper, a new transmission-line pilot protection principle is proposed. When an external fault occurs, the amplitude of the fault component integrated impedance that reflects the capacitance impedance of the line becomes large; When an internal fault occurs, the amplitude of the fault component integrated impedance which reflects the impedance of the system source and the line, becomes relatively small. Therefore, the fault in the line can be detected according to this characteristic. The criterion is not affected by the current through the capacitance and is not affected by the fault resistance. It can be applied to the line with or without shunt reactor. Also, it can be easily set. Both the simulation results with Electromagnetic Transients Program and dynamic model data verify the validity of the proposed principle.

A Fault Steady State Component-Based Wide Area Backup Protection Algorithm

Abstract: A novel wide area backup protection algorithm to identify fault branch based on the fault steady state component is proposed. Under normal conditions of the power system, subsets of buses called protection correlation regions (PCRs) are formed on the basis of the network topology and phasor measurement unit (PMU) placement. After the fault occurs, by analyzing the fault steady state component of differential current in each PCR, the fault correlation region is confirmed and then a fault correlation factor (FCF), is calculated in real time to locate the fault branch. The simulation results for the 10-generator 39-bus system verify that this method is able to easily identify fault branch with limited measurement points.

Fault models of inverter-interfaced distributed generators: Experimental verification and application to fault analysis

Abstract: This paper investigates the fault behaviour of inverter-interfaced distributed generators in stand-alone networks. It is shown that the rapid transient response of the inverter control system allows its fault behaviour to be characterised by quasi steady-state equivalent fault models. The choice of inverter control strategy, control reference frame and the method of active current limiting dominate the fault response, especially in case of unbalanced faults. The proposed fault models can be directly incorporated in conventional fault analysis methods of which an example is given for a faulty islanded microgrid. Model validation is carried out by comparing experimental measurements with results of analytical fault analysis using the developed fault models and PSCAD time domain simulations.

Methods of Handling the Tolerance and Test-Point Selection Problem for Analog-Circuit Fault Diagnosis

Abstract: Soft-fault diagnosis and tolerance are two challenging problems in analog-circuit fault diagnosis. Although many analog faults can be diagnosed theoretically, they cannot be accurately diagnosed due to the influence of component tolerance. This paper proposes approaches to the tolerance-handling method in soft-fault diagnosis. First, the slope fault model and its theoretical proof are presented. In linear analog circuits, the voltage equation between two nodes is linear and can be expressed by a point-slope-form equation in which the point is determined by the nominal voltage values on the two selected nodes, and the slope, which is invariant, can be used as the fault model, which is applicable to both hard (open or short) and soft (parametric) faults. Then, the parameter tolerance is taken into consideration. The point-slope-form equation is governed by a point and a slope value. The tolerance influences the fault diagnosis by shifting both the point and the nominal slope value. These influences can be mitigated in two ways: 1) The point is measured when an actual circuit is under steady state and free of fault, and 2) the maximum slope deviation is readily obtained by using optimization theory if the equation governing the voltage between two nodes is available; otherwise, a threshold proportion coefficient is used to calculate the maximum deviation. Based on these methods, a novel test-point selection approach for the fault dictionary technique is proposed. The effectiveness of the proposed approaches is verified by both simulated and experimental results.

A Novel Fault-Location Algorithm for Double-Circuit Transmission Lines Without Utilizing Line Parameters

Abstract: This paper puts forward a novel algorithm for locating faults on double-circuit transmission lines using two-end unsynchronized current measurements. The algorithm does not require line parameters, which is a radical step forward compared to existing approaches, which require this information, so it can be considered as a settings-free algorithm. Only the positive-sequence current phasors during the fault are processed for determining the sought distance to fault and the synchronization angle, limiting thus the amount of data needed to be transferred from each line terminal. The proposed algorithm is derived by applying the Kirchhoff's voltage law around the parallel circuits loops during the fault. The algorithm is applicable for both transposed and untransposed double-circuit lines and is independent of the fault type. Evaluation studies using reliable Alternative Transients Program-Electromagnetic Transients Program simulation data verify that the accuracy of the proposed algorithm is very high under various fault resistances, fault locations, and source impedances.

Sampling + DMR: practical and low-overhead permanent fault detection

Abstract: With technology scaling, manufacture-time and in-field permanent faults are becoming a fundamental problem. Multi-core architectures with spares can tolerate them by detecting and isolating faulty cores, but the required fault detection coverage becomes effectively 100% as the number of permanent faults increases. Dual-modular redundancy(DMR) can provide 100% coverage without assuming device-level fault models, but its overhead is excessive. In this paper, we explore a simple and low-overhead mechanism we call Sampling-DMR: run in DMR mode for a small percentage (1% of the time for example) of each periodic execution window (5 million cycles for example). Although Sampling-DMR can leave some errors undetected, we argue the permanent fault coverage is 100% because it can detect all faults eventually. Sampling-DMR thus introduces a system paradigm of restricting all permanent faults' effects to small finite windows of error occurrence. We prove an ultimate upper bound exists on total missed errors and develop a probabilistic model to analyze the distribution of the number of undetected errors and detection latency. The model is validated using full gate-level fault injection experiments for an actual processor running full application software. Sampling-DMR outperforms conventional techniques in terms of fault coverage, sustains similar detection latency guarantees, and limits energy and performance overheads to less than 2%.

Transmission line faults detection, classification and location using artificial neural network

Abstract: Transmission lines, among the other electrical power system components, suffer from unexpected failures due to various random causes. These failures interrupt the reliability of the operation of the power system. When unpredicted faults occur protective systems are required to prevent the propagation of these faults and safeguard the system against the abnormal operation resulting from them. The functions of these protective systems are to detect and classify faults as well as to determine the location of the faulty line as in the voltage and/or current line magnitudes. Then after the protective relay sends a trip signal to a circuit breaker(s) in order to disconnect (isolate) the faulty line.The features of neural networks, such as their ability to learn, generalize and parallel processing, among others, have made their applications for many systems ideal. The use of neural networks as pattern classifiers is among their most common and powerful applications. This paper presents the use of back-propagation (BP) neural network architecture as an alternative method for fault detection, classification and isolation in a transmission line system. The main goal is the implementation of complete scheme for distance protection of a transmission line system. In order to perform this, the distance protection task is subdivided into different neural networks for fault detection, fault identification (classification) as well as fault location in different zones. Three common faults were discussed; single phase to ground faults, double phase faults and double phase to ground faults. The result provides a reliable and an attractive alternative approach for the development of a protection relaying system for the power transmission systems.

Automatic Synthesis of Static Fault Trees from System Models

Abstract: Fault tree analysis (FTA) is a traditional reliability analysis technique. In practice, the manual development of fault trees could be costly and error-prone, especially in the case of fault tolerant systems due to the inherent complexities such as various dependencies and interactions among components. Some dynamic fault tree gates, such as Functional Dependency (FDEP) and Priority AND (PAND), are proposed to model the functional and sequential dependencies, respectively. Unfortunately, the potential semantic troubles and limitations of these gates have not been well studied before. In this paper, we describe a framework to automatically generate static fault trees from system models specified with SysML. A reliability configuration model (RCM) and a static fault tree model (SFTM) are proposed to embed system configuration information needed for reliability analysis and error mechanism for fault tree generation, respectively. In the SFTM, the static representations of functional and sequential dependencies with standard Boolean AND and OR gates are proposed, which can avoid the problems of the dynamic FDEP and PAND gates and can reduce the cost of analysis based on a combinatorial model. A fault-tolerant parallel processor (FTTP) example is used to demonstrate our approach.

High-speed superimposed-based protection of series-compensated transmission lines

Abstract: This study presents a sub-cycle power frequency-based fault direction discrimination and fault classification algorithm for the series-compensated transmission lines. Also, it provides an accurate estimation for the fault occurrence instant which is helpful in synchronised waveforms-based pilot protective schemes. The proposed algorithm is based on capturing the initial change in the voltage and current waveforms caused by occurrence of a fault. The high-frequency components of the fault signals are first filtered out, and then the signals are sampled at a relatively low sampling rate. Unlike the conventional relative-phase-angle-based directional relays, the proposed algorithm is not affected by the current and voltage inversion phenomena due to the presence of series capacitor in the fault loop. Extensive simulation studies are performed to evaluate the proposed algorithm performance. The obtained results show that the proposed algorithm provides a simple and a very fast and reliable protection technique for power transmission lines. This algorithm also covers non-compensated transmission lines and is able to well discriminate the fault direction even if the post-fault voltage amplitude becomes too small. It is also tested using some real data recorded from a high-voltage transmission system.

Determinant-based feature extraction for fault detection and classification for power transmission lines

Abstract: This study proposes a novel fault feature extraction that could be used in fault detection and classification schemes for power system transmission lines, based on single-end measurements using time shift invariant property of a sinusoidal waveform. Various types of faults at different locations, fault resistance and fault inception angles on a 400 kV 361.65 km power system transmission line are investigated. The determinant function is used to extract distinctive fault features over various data window sizes namely, 1/4, 1/2 and a cycle of post-fault data. In addition, various delays were introduced before taking the post-fault measurements. The performance of the feature extraction scheme was tested on a machine intelligent platform WEKA by using three types of feature selection techniques: information gain, gain ratio and SVM. The result shows that, the determinant function defined over the phase current and neutral current is sufficient to classify ten types of short-circuit faults on doubly fed transmission lines; however, the scheme did not differentiate between 3 phase line faults (LLL) and 3 phase lines to ground faults (LLLG), the two types of faults are treated as the same type of fault, balanced fault. An accuracy between 95.95 and 100 is achieved.

Online fault-detecting scheme of an inverter-fed permanent magnet synchronous motor under stator winding shorted turn and inverter switch open

Abstract: To detect faults in an inverter-fed permanent magnet synchronous motor drive under the circumstance having faults in a stator winding and inverter switch, an online basis fault-detecting scheme during motor operation is presented. The proposed scheme is achieved by monitoring the second-order harmonic component in q-axis current and the fault is detected by comparing these components with those in normal conditions. The non-fault harmonic data in an arbitrary operating condition are determined using the linear interpolation method with several sample harmonic data pre-measured in the stage of the initial drive setup. Once the fault is detected, the operating mode is changed to identify a fault source using the phase current waveform. To verify the effectiveness of the proposed fault detecting scheme, a test motor to allow inter-turn short in the stator winding has been built. The entire control system including harmonic analysis and fault detecting algorithm is implemented using digital signal processor TMS320F28335. Without requiring an additional hardware, the fault can be effectively detected by the proposed scheme during operation so long as the steady-state condition is satisfied.

An efficient test data reduction technique through dynamic pattern mixing across multiple fault models

Abstract: ATPG tool generated patterns are a major component of test data for large SOCs. With increasing sizes of chips, higher integration involving IP cores and the need for patterns targeting multiple fault models for better defect coverage in newer technologies, the issues of adequate coverage and reasonable test data volume and application time dominate the economics of test. We address the problem of generating compact set of test patterns across multiple fault models. Traditional approaches use separate ATPG for each fault models and minimize patterns either during pattern generation through static or dynamic compaction, or after pattern generation by simulating all patterns over all fault models for static compaction. We propose a novel ATPG technique where all fault models of interest are concurrently targeted in a single ATPG run. Patterns are generated in small intervals, each consisting of 16, 32 or 64 patterns. In each interval fault model specific ATPG setups generate separate pattern sets for their respective fault model. An effectiveness criterion then selects exactly one of those pattern sets. The selected set covers untargeted faults that would have required the most additional patterns. Pattern generation intervals are repeated until required coverage for faults of all models of interest is achieved. The sum total of all selected interval pattern sets is the overall test set for the DUT. Experiments on industrial circuits show pattern count reductions of 21% to 68%. The technique is independent of any special ATPG tool or scan compression technique and requires no change or additional support in an existing ATPG system.