Showing papers on "System bus published in 2007"

Systems and methods for multiple mode voice and data communications using intelligently bridged TDM and packet buses and methods for implementing language capabilities using the same

Abstract: Systems and methods by which voice/data communications may occur in multiple modes/protocols are disclosed. In particular, systems and methods are provided for multiple native mode/protocol voice and data transmissions and receptions with a computing system having a multi-bus structure, including, for example, a TDM bus and a packet bus, and multi-protocol framing engines. Such systems preferably include subsystem functions such as PBX, voice mail and other telephony functions, LAN hub and data router. In preferred embodiments, a TDM bus and a packet bus are intelligently bridged and managed, thereby enabling such multiple mode/protocol voice and data transmissions to be intelligently managed and controlled with a single, integrated system. A computer or other processor includes a local area network controller, which provides routing and hub(s) for one or more packet networks. The computer also is coupled to a buffer/framer, which serves to frame/deframe data to/from the computer from TDM bus. The buffer/framer includes a plurality of framer/deframer engines, supporting, for example, ATM and HDLC framing/deframing. The buffer/framer is coupled to the TDM bus by way of a switch/multiplexer, which includes the capability to intelligently map data traffic between the buffer/framer and the TDM bus to various slots of the TDM frames. Preferably, a DSP pool is coupled to buffer/framer in a manner to provide various signal processing and telecommunications support, such as dial tone generation, DTMF detection and the like. The TDM bus is coupled to a various line/station cards, serving to interface the TDM bus with telephone, facsimiles and other telecommunication devices, and also with a various digital and/or analog WAN network services. Language support for such systems is accomplished by way of a program/data structure so that additional language support may be readily implemented, for example, by a non-software programmer using grammar and voice prompt files, which are preferably located in a predetermined directory in the system.

Method and system for controlling and monitoring an array of point-of-load regulators

Abstract: A power control system comprises a plurality of POL regulators, at least one serial data bus operatively connecting the plurality of POL regulators, and a system controller connected to the serial data bus and adapted to send and receive digital data to and from the plurality of POL regulators. The serial data bus further comprises a first data bus carrying programming and control information between the system controller and the plurality of POL regulators. The serial data bus may also include a second data bus carrying fault management information between the system controller and the plurality of POL regulators. The power control may also include a front-end regulator providing an intermediate voltage to the plurality of POL regulators on an intermediate voltage bus.

Multiplexing a parallel bus interface and a flash memory interface

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for multiplexing a parallel bus interface with a flash memory interface. In some embodiments, an integrated circuit includes a parallel bus interface to communicate parallel bus interface signals. The integrated circuit may also include logic to multiplex flash memory device interface signals and parallel bus interface signals on the parallel bus interface.

RF bus controller

Abstract: A radio frequency (RF) bus controller includes an interface and a processing module. The interface is coupled for communicating intra-device RF bus access requests and allocations. The processing module is coupled to receive an access request to an RF bus via the interface; determine RF bus resource availability; and when sufficient RF bus resources are available to fulfill the access request, allocate, via the interface, at least one RF bus resource in response to the access request.

mPlatform: a reconfigurable architecture and efficient data sharing mechanism for modular sensor nodes

Abstract: We present mPlatform, a new reconfigurable modular sensornet platform that enables real-time processing on multiple heterogeneous processors. At the heart of the mPlatform is a scalable high-performance communication bus connecting the different modules of a node, allowing time-critical data to be shared without delay and supporting reconfigurability at the hardware level. Furthermore, the bus allows components of an application to span across different processors/modules without incurring much overhead, thus easing the program development and supporting software reconfigurability. We describe the communication architecture, protocol, and hardware configuration, and the implementation in a low power, high speed complex programmable logic device (CPLD). An asynchronous interface decouples the local processor of each module from the bus, allowing the bus to operate at the maximum desired speed while letting the processors focus on their real time tasks such as data collection and processing. Extensive experiments on the mPlatform prototype have validated the scalability of the communication architecture, and the high speed, reconfigurable inter-module communication that is achieved at the expense of a small increase in the power consumption. Finally, we demonstrate a real-time sound source localization application on the mPlatform, with four channels of acoustic data acquisition, FFT, and sound classification, that otherwise would be infeasible using traditional buses such as I2C.

An intelligent aircraft secondary power distribution system that facilitates condition based maintenance

Abstract: An electrical power distribution system comprises a solid state power controller (102) in communication with an aircraft system main data bus (126) via a gateway module (128) and a condition based maintenance module (134) in communication with the solid state power controller (102) via a communication network (118) distinct from the main data bus (126). A method of load/feeder health assessment for an electrical power distribution system includes applying a controlled excitation to a load; sampling information from the load/feeder system for the load; characterizing a normal behavior of the load/feeder system for the load; determining if the load characteristics are within the normal behavior profile for the load; and shutting down power to the load if load characteristics are not within the profile when immediate action is indicated or generating a health message for the load when immediate action is not required.

System and method for facilitating skill gap analysis and remediation based on tag analytics

Abstract: This invention includes a workforce management system having a system bus, at least one database in communication with the system bus that includes data representative of workforce employees, and social networking data associated with the employees. A matching functional unit includes a text mining function for mining contextual information from the at least one database to generate context labels for an employee, a clustering function for generating concept labels for an employee, and a matching function that sorts and matches employees by the labels in accordance with a matching criteria. A user interface provides user input to the support operation of the workforce management system.

Apparatus, system, and method for a device shared between multiple independent hosts

Abstract: An apparatus, system and method that permits for sharing a device between multiple hosts where data can be transferred between a host and the shared device over a system bus independent from other hosts connected to the system bus. A command proxy host establishes a data path between the shared device and requesting host, and then acts as proxy for selected commands used to set up a data transfer.

Liquid crystal display device and method for fabricating the same

Abstract: A liquid crystal display device and a method for fabricating the same are provided to improve brightness by overcoming a limitation on an increase of an aperture ratio by mixing an IPS(In Plane Switching) mode and an FFS(Fringe Field Switching) mode, and improve a viewing angle by realizing micro multi-domains Gate bus lines(111) are arranged on a lower substrate in a first direction Data bus lines(121) are arranged in a second direction crossing the first direction Common electrode lines(117) are arranged at areas formed by crossing the gate bus lines and the data bus lines, consisting of a plurality of common electrodes(117a) and plate common electrodes(117b) Thin film transistors are formed at areas where the gate bus lines and the data bus lines cross each other Pixel electrode lines(131) are arranged on the lower substrate including the common electrode lines, insulated from the common electrode lines, consisting of a plurality of pixel electrodes(131a) placed between the plurality of common electrodes and a plurality of pixel electrodes(131a) overlapped with the plate common electrodes An upper substrate is opposite to the lower substrate at a certain gap, having a color filter layer A liquid crystal layer is arranged between the upper substrate and the lower substrate

Speed exceeded notification device for vehicle having a data bus and associated methods

Abstract: A speed exceeded notification device is for a vehicle of a type including a vehicle data communications bus extending throughout the vehicle, and at least one vehicle device generating data related to vehicle speed on the vehicle data communications bus. The speed exceeded notification device may include a wireless communications device, and a controller to be coupled to the vehicle data communications bus. The controller may be for reading the data related to vehicle speed from the vehicle data communications bus, and determining when a vehicle speed exceeds a speed threshold for a first time period. The controller may also be for determining when the vehicle speed exceeds the speed threshold for a second time period less than the first time period and, in response thereto, generating a local vehicle speed exceeded notification. Based thereon, the controller may cooperate with the wireless communications device to send a remote vehicle speed exceeded notification.

SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips

Abstract: A high performance communication architecture, SAMBA-bus, is proposed in this paper. In SAMBA-bus architecture, multiple compatible bus transactions can be performed simultaneously with only a single bus access grant from the bus arbiter. Experimental results show that, compared with a traditional bus architecture, the SAMBA-bus architecture can have up to 3.5 times improvement in the effective bandwidth, and up to 15 times reduction in the average communication latency. In addition, the performance of SAMBA-bus architecture is affected only slightly by arbitration latency, because bus transactions can be performed without waiting for the bus access grant from the arbiter. This feature is desirable in SoC designs with large numbers of modules and long communication delay between modules and the bus arbiter

Apparatus and method for reconfiguring a programmable logic device

Abstract: A method and apparatus is provided to implement rapid reconfiguration during either a full, or partial, reconfiguration of a programmable logic device (PLD). Rapid reconfiguration is facilitated by a massively parallel configuration data bus that is created to simultaneously reconfigure the entire height of a reconfiguration memory space. A direct link may be provided to the configuration memory space of the PLD by utilizing interconnect and input/output resources to form the massively parallel configuration data bus. An indirect link may also be provided to the entire configuration memory space by utilizing existing random access memory (RAM) resources within the PLD as configuration bitstream buffers.

Power management systems for automotive video event recorders

Abstract: Video event recorders are coupled to a vehicle power source via an on-board diagnostic system including its power bus, data bus, and scanner port connector. Video event recorders are provided with a power input arranged in conjunction with a standard ODBII type “D” connector. Systems further include an extension cable between the connector and the vehicle event record to accommodate mounting needs associated with each. In advanced versions, both OBD power and data networks are coupled to the vehicle event recorded such that data relating to vehicle diagnostic systems can be captured in a triggered event along with video data. In addition, some versions are provided with special detection mechanism to determine the use state of a vehicle and adjust application of power accordingly. Thus an “in-use” detector is coupled to the vehicle and/or OBD systems to provide feedback which helps to conserve power and regulate the power connections.

Design and control of a second-generation hyper-redundant mechanism

Abstract: We present a refined, second-generation design, construction and integration, of a compact hyper-redundant snakelike robot, called "Woodstock." This robot has substantial advantages over our previous design iteration, "Snoopy," in terms of cost and performance. The robot is composed of six actuated universal joints which are serially chained to construct a twelve degrees of freedom snake-like robot optimized for strength and compactness. Any joint in the robot is strong enough to produce a torque that is capable of cantilevering the entire robot. This paper also presents the low-level system- control architecture, which is based on a high-speed RS-485 data bus; this allows the entire system to be operated with only two power and two data wires. The system is controlled from a remote computer on a wireless network and can also run over the Internet.

Vehicle tracking unit with downloadable codes and associated methods

Abstract: A multi-vehicle compatible tracking unit is for a vehicle including a vehicle data bus extending throughout the vehicle. The vehicle tracking unit may include a vehicle position determining device, a wireless communications device, and a multi-vehicle compatible controller for cooperating with the vehicle position determining device and the wireless communications device to send vehicle position information. The multi-vehicle compatible controller may be coupled to the vehicle data bus for communication thereover with at least one vehicle device using at least one corresponding vehicle device code from among a plurality thereof for different vehicles. A downloading interface may be included for permitting downloading of enabling data related to the at least one corresponding vehicle device code for use by the multi-vehicle compatible controller.

Data bus bandwidth scheduling in an fbdimm memory system operating in variable latency mode

Abstract: A method and system for scheduling the servicing of data requests, using the variable latency mode, in an FBDIMM memory sub-system. A scheduling algorithm pre-computes return time data for data connected to all DRAM buffer chips and stores the return time data in a table. The return time data is expressed as a set of data return time binary vectors with one bit equal to “1” in each vector. For each received data request, the memory controller retrieves the appropriate return time vector. Additionally, the scheduling algorithm utilizes an updated history vector representing a compilation of data return time vectors of all executing requests to determine whether the received request presents a conflict to the executing requests. By computing and utilizing a score for each request, the scheduling algorithm re-orders and schedules the execution of selected requests to preserve as much data bus bandwidth as possible, while avoiding conflict.

Processing system with millimeter wave host interface and method for use therewith

Abstract: A processing system includes a plurality of first circuit modules and a wired data bus, connected to the plurality of first circuit modules. A plurality of second circuit modules are coupled to an RF data bus via a millimeter wave communication path. A millimeter wave modem receives first data from at least one of the plurality of first circuit modules via the wired data bus, and transmits the first data over the RF data bus to at least one of the plurality of second circuit modules.

Methods and apparatus for decreasing power consumption and bus activity

Abstract: Methods and apparatus for enhancing efficiency (e.g., reducing power consumption and bus activity) in a data bus. In an exemplary embodiment, a client-driven host device state machine switches among various states, each comprising a different polling frequency. A client device on the data bus (e.g., serial bus) checks for non-productive periods of polling activity, and upon discovering such a period, informs the host. The state machine then alters its polling scheme; e.g., switches to a lower state comprising a reduced polling frequency, and polling continues at this reduced frequency. In one variant, the client device continuously monitors itself to determine whether it has any data to transmit to a host device and if so, the host is informed, and the state machine restarts (e.g., to its highest polling state). By eliminating extraneous polling, power consumption and serial bus activity is optimized, potentially on both the host and the client.

Distributed engine control system

Abstract: A distributed engine control system is provided. The engine control system includes first and second engine data concentrators. Each of the first and second engine data concentrators include a processor module, a signal conditioning module coupled to the processor module, a data transfer module coupled to the processor module, and a data bus coupled between the first and second engine data concentrators and a hydro-mechanical unit (HMU).

Event signaling between peripheral modules and a processing unit

Abstract: There is described a method, a bus protocol, a peripheral module, a processing unit, a hub and also to a system consisting of said components, for event signaling between at least one peripheral module and a processing unit by means of a system bus. In this case the data to be transmitted data is encoded into a larger symbol space, from which a standard idle symbol is used in telegram pauses for synchronizing a connection between transmitter and receiver. A message present at the peripheral modules is enabled to be signaled to the processing unit independently of the telegram traffic initiated by the processing unit. This is achieved by a peripheral module wishing to signal an event to the processing unit sending to the processing unit in a telegram pause, instead of the standard idle character, a signaling sequence consisting of an alarm idle symbol and an alarm identifier which contain information about the relevant event as well as the module address of the peripheral module at which the event is present, with the information about the event also being transcoded into the larger symbol space.

Reduced pin count interface

Abstract: An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface are some operations performed by the controller. The controller determines a width for a Data bus while assigning a target device address to each of the memory devices.

BMSYN: Bus Matrix Communication Architecture Synthesis for MPSoC

Abstract: Modern multiprocessor system-on-chip designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Traditional hierarchical shared bus communication architectures can only support limited bandwidths and are not scalable for very high-performance designs. Bus matrix-based communication architectures consist of several parallel busses which provide a suitable backbone to support high-bandwidth systems but suffer from high-cost overhead due to extensive bus wiring inside the matrix. Manual traversal of the vast exploration space to synthesize a minimal cost bus matrix that also satisfies performance constraints is practically infeasible. In this paper, we address this problem by proposing an automated approach for synthesizing a bus matrix communication architecture, which satisfies all performance constraints in the design and minimizes wire congestion in the matrix. To validate our approach, we consider several industrial strength applications from the networking domain and show that our approach results in up to 9times component savings when compared to a full bus matrix, and up to 3.2times savings when compared to a maximally connected reduced bus matrix, while satisfying all performance constraints in the design.

Receiver and distribution unit for vehicle entertainment system

Abstract: A receiver and distribution unit in a vehicle that includes a wireless receiver and signal processing/conversion facilities. The receiver and distribution unit may include a data bus and a selection multiplexer connected to the wireless receiver and an additional media source. The wireless receiver receives asignal comprising media content from a wireless network, such as the FLOTM network. The processing/conversion facilities decode the signal for output to a display and speaker in the vehicle. The selection multiplexer multiplexes media content from the wireless receiver or media content from the additional media source to the data bus. A function control, controllable by a wired controller and a wireless controller, controls the functions of the receiver and distribution unit.

Non-blocking bus controller for a pipelined, variable latency, hierarchical bus with point-to-point first-in first-out ordering

Abstract: A method and apparatus is disclosed herein for a bus controller that supports a flexible bus protocol that handles pipelined, variable latency bus transactions while maintaining point-to-point (P2P) FIFO ordering of transactions in a non-blocking manner. In one embodiment, the apparatus includes a bus controller to receive a plurality of bus transactions at a first incoming port from a bus. The bus controller is configured to process the plurality of bus transactions in a pipelined manner, maintaining P2P FIFO ordering of the plurality of bus transactions even when the plurality of bus transactions take a variable number of cycles to complete.

System and architecture for controlling lighting through a low-voltage bus

Abstract: A system and architecture for managing lighting through a seamless low-voltage bus network is disclosed. The system comprises a plurality of control units that serve as nodes for integrating devices, such as light fixtures, control switches and sensors into the bus. Each of the control units preferably includes a printed circuit board and node interconnects for assembling the low-voltage bus and for integrating the devices. Alternatively, the system comprises a central hub with a master printed circuit control board and a plurality of interconnects for assembling the bus and for integrating the devices.

Control protocol encapsulation

Abstract: Some bus protocols are useful for management of peripheral devices that exist on a computer's system bus. Such bus protocols include the industry standard architecture bus (ISA), peripheral component interconnect (PCI), PCI express (PCIe), etc. The usefulness of such protocols for control messages, interrupt management and more is limited to the short distances over which the protocols operate, usually measured in inches. The use of longer distance transport protocols, such as Ethernet to encapsulate and transport bus protocol messages allows the advantages of the short distant protocols to be used to control remote devices. A master device, with a controller or processor, may be used to manage the operation of a slave device using the bus or control protocol. Such management may include button presses, indicator lights, slave device configuration, etc. The slave device may have a low cost controller or ASIC to provide real-time operational functions, such as routing.

An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion

Abstract: A 4Gb/s/pin 32b parallel 512Mb GDDR4 SDRAM is implemented in an 80nm DRAM process. It employs a data-bus inversion coding scheme with an analog majority voter insensitive to mismatch, which reduces peak-to-peak jitter by 21 ps and voltage fluctuation by 68mV. A dual duty-cycle corrector is proposed to average duty error, and tuning is added to the auto-calibration of driver and termination impedance.

Remote power management and monitoring system for solid state circuit breaker control with manual bypass

Abstract: A power management and monitoring system for controlling an electrical device powered by a power supply is disclosed. The system may include a circuit breaker enclosure box structured to monitor and manage power to the electrical device via a centralized data bus and centralized power bus. The circuit breaker enclosure box may include at least a remotely actuated solid state electronic circuit breaker (ECB) that monitors and manages power to the electrical device and a switch connected to the ECB and capable or remotely bypassing the ECB. The system may also include a display and controller that can remotely monitor and control the electrical device by remotely actuating the ECB.

Method and apparatus for synchronization of actions in a parallel ups system using a serial communications bus

Abstract: A serial communications bus is utilized to send key action data between parallel UPS units. The communications bus is used to transmit data at the zero crossing of the critical bus voltage. Each UPS unit then takes action based upon the event data received at the next zero crossing of the critical bus voltage.

Data bus bridge and its working method

Abstract: The related data bus bridge comprises: a physical interface connected with external standard device to transmit data according to different logic channel, a data link unit to execute HDLC protocol for data on different logic channel, a FIFO unit for data buffer, an arbitrating mechanism unit to ensure physical interfaces exclusive visit the share data in memory and make the data read and write accord with protocol specification, and a DMA control unit to build high-speed data transmission between physical interface and physical memory. This invention is real-time and reliable, and fit to negotiate control device and monitor device.