Showing papers on "Thin-film transistor published in 1980"

A New Field-Effect Transistor with Selectively Doped GaAs/n-AlxGa1-xAs Heterojunctions

Abstract: Studies of field-effect control of the high mobility electrons in MBE-grown selectively doped GaAs/n-AlxGa1-x As heterojunctions are described. Successful fabrication of a new field-effect transistor, called a high electron mobility transistor (HEMT), with extremely high-speed microwave capabilities is reported.

Hydrogenation of transistors fabricated in polycrystalline-silicon films

Abstract: Transistors have been fabricated with their active channels in thin films of polycrystalline silicon. A subsequent hydrogen plasma treatment has been used to improve the transistor properties significantly by reducing the number of electrically active grain-boundary defects. Plasma conditions to maximize the hydrogenation effect have been briefly investigated.

Self-aligned process for providing an improved high performance bipolar transistor

Abstract: A bipolar transistor structure formed in a monolithic silicon semiconductor substrate of p type having a planar surface comprising: a subcollector of n type formed in the substrate; an epitaxial layer of n type formed on said planar surface of said substrate and also having a planar surface, the epitaxial layer having a thickness in the order of 1.0 to 1.5 micrometers; an enclosed deep recessed oxide isolation trench enclosing a transistor structure area of the substrate and the epitaxial layer, the enclosed deep recessed oxide isolation trench having a depth extending from said planar surface of said epitaxial layer through the subcollector region; a shallow recessed oxide isolation trench, the relatively shallow recessed oxide isolation trench being wholly enclosed by the deep recessed oxide isolation trench and intersecting the deep recessed oxide isolation trench at two spaced apart points to divide said transistor structure area enclosed by the deep recessed oxide isolation trench into first and second areas, the first and second areas being electrically connected one to the other by the subcollector region; a shallow depth emitter region formed in a limited portion of the first area of said epitaxial layer, the emitter region having a depth in the order of 0.1 micrometers; an active base region formed beneath said emitter region in the limited portion the first area of said epitaxial layer, the active base region having a width in the order of 0.1 micrometers; an inactive base region surrounding the emitter region and active base region, the inactive base region being wholly contained within the first area of said epitaxial layer; an emitter-base junction contained within said first area of the epitaxial layer and extending to the surface of the epitaxial layer; a composite layer of silicon dioxide and silicon nitride having a width of approximately 0.2 to 0.3 micrometers, the composite layer being positioned on the planar surface of the epitaxial layer over the surface juncture of said emitter-base junction, the silicon dioxide having a thickness of approximately 500Å and the silicon nitride layer having a thickness of approximately 500Å; the second area of the epitaxial layer containing a collector reach through, the shallow recessed oxide isolation trench isolating the collector reach through from the inactive base region; a layer of polysilicon p type on said planar surface of the epitaxial layer and in physical and electrical contact with the inactive base region, the polysilicon layer extending over a portion of said enclosed relatively deep recessed oxide isolation trench; and, a base contact physically and electrically contacting the portion of the polysilicon layer which extends over the enclosed deep recessed oxide isolation trench.

Amorphous silicon thin film transistor and manufacture thereof

Abstract: PURPOSE:To eliminate the distortion of VD-ID curve by a method wherein a gate electrode is formed on a semiconductor layer through an insulation layer, and N layers are formed in parallel isolated from each other on a clean surface of the semiconductor layer. CONSTITUTION:An a-Si-TFT is formed on a substrate 106 made of glass, ceramics or the like by laminating in sequence a gate electrode 101, an electrical insulation layer 104 designed to cover the gate electrode 101 and a semiconductor layer 105 composed of hydrided and/or fluorided amorphous silicon, and constructed to have a structure in which the first N layer 107-1, the second N layer 107-2 are mounted isolated from each other in a parallel relation on the surface 108 of the semiconductor layer 105, and in addition, a source electrode 102 is mounted on the first N layer 107-1 and a drain electrode 103 on the second N layer 107-2, respectively. The N layers are formed during the surface 108 of the semiconductor 105 being in the clean state just after the formation of the layer, thereby a satisfactory ohmic contact is formed on the interface of the semiconductor layer 105 and the N layers 107.

Thin film transistors, thin film transistor arrays, and a process for preparing the same

Abstract: A process for the preparation of thin film transistors and thin film transistor arrays as described wherein, in a single pump-down, the semiconductive pad, the source electrode, the drain electrode and an insulating layer over the source electrode, drain electrode, and the exposed portion of the semiconductive layer is applied in a single vacuum pump-down by the deposition of the various materials through a shadow mask having openings therein of a size equal to the size of the semiconductive pad to be deposited. The mask is first utilized to deposit the semiconductive pad then moved in a direction and the first conductive electrode is deposited then moved in a direction 180° with respect to the first direction a distance of approximately twice that of the original motion and the second conductor applied by deposition through the openings in the mask. Finally, the remaining portion of the thin film transistors are completed by conventional technology.

Method for forming an insulating film on a semiconductor substrate surface

Abstract: METHOD FOR FORMING AN INSULATING FILM ON A SEMICONDUCTOR SUBSTRATE SURFACE ABSTRACT In a method for forming an insulating film on a semiconductor substrate surface, the silicon nitride of the insulating film has been formed by a plasma CVD or a direct nitridation In the present invention, a gas plasma of a nitrogen-containing gas is generated in a direct nitridation reaction chamber, and the semiconductor silicon body is heated to a temperature of from approximately 800 to approximately 1300°C within the gas plasma atmosphere, thereby forming the silicon nitride film The resulting silicon nitride film has a dense structure and a low oxygen concentration and a thick silicon nitride film is formed in a short period of direct nitridation of silicon

Complementary transistor structure

Abstract: Complementary, vertical bipolar NPN and PNP transistors are fabricated on the same monolithic semiconductor substrate which have matched high performance characteristics. A method for fabricating such complementary devices is also provided. In the method, a barrier region of a first conductivity type is formed on the surface of the monocrystalline semiconductor substrate doped with a second conductivity type. After an annealing heat treatment to drive in the doping ions of the barrier region, a collector region for one of the complementary transistors of a second conductivity type is formed within the barrier region. It is convenient to simultaneously form isolation regions of a second conductivity type in the substrate while forming the collector region. A collector region of a first conductivity type is then formed in the substrate for the other of the complementary transistors. The collector region for the other complementary transistor is formed within at least one other isolation region. An epitaxial layer of semiconductor material doped with ions of the first conductivity type is then formed on the surface of the substrate. To provide improved PNP transistor performance, the P-type emitter for the PNP transistor is formed prior to a last drive-in treatment by forming a polycrystalline silicon layer on the exposed surface of the base. The polycrystalline silicon is doped with a P-type dopant. Thereafter the transistor structure is subjected to conditions whereby the doping ions contained in the polycrystalline silicon layer are driven into the epitaxial layer to provide a shallow emitter region without effecting dislocations in the silicon lattice of the epitaxial layer.

Segmented type liquid crystal display and driving method thereof

Abstract: A system is disclosed for driving a segmented type liquid crystal display comprising a thin film transistor (TFT) array including a plurality of TFTs each having a gate line, a source line, and a drain line, a pair of substrates with one carrying the thin film transistor array coupled to a plurality of segmented display electrodes and the other carrying a common electrode opposite to the segmented display electrodes, a liquid crystal material interposed between the pair of substrates. The system is characterized by a source line and drain line driving circuit for driving the source line and the drain line with a first voltage waveform and a second voltage waveform in such a manner that the ratio of the first voltage amplitude to the second voltage is so selected that both charging and discharging voltages in the forward and backward directions are zero when the TFTs are off. In another aspect of the segmented type display of the present invention, there is additionally provided a separating element for separating the thin film transistor array from the liquid crystal material. In a further aspect, the plurality of pairs of the segmented display electrodes and the common electrodes are allotted equally to each of the pair of substrates.

Polycrystalline‐silicon thin‐film transistors on glass

Abstract: Thin‐film transistors are fabricated on polycrystalline silicon on transparent glass using molecular beam deposition at low temperatures. It is found that the transistor characteristics and stability of this device, together with the low‐temperature processes utilized, afford potential application to flat display panels.

Structure of thin film transistors

Abstract: A thin film transistor comprises a substrate, a gate electrode, a drain electrode, a source electrode, an insulative layer, and a semiconductor layer for the purpose of switching display signals to be applied to at least one display element of a display device. Preferably, the thin film transistor is mounted on the same substrate on which the display element is mounted. The selected material for the display element electrode is identical to at least one selected from the gate electrode, the source electrode, and the drain electrode. In another aspect of the present invention neither the gate electrode nor the insulating layer overlap either of the drain electrode or the source electrode. A resistance value of the semiconductor layer between the source and the drain electrodes is considerably less than the resistance value of the semiconductor channel layer controlled by the gate electrode. For this purpose, at least one of the width, thickness, and impurity concentration is varied therebetween. In a further aspect, the semiconductor channel has a substantial length more than the distance between the source electrode and the drain electrode with the help of a labyrinth passage.

Polysilicon FET devices for large area input/output applications

Abstract: The properties of FETs made in a polysilicon semiconductor are discussed both theoretically and experimentally. A two-dimensional solution for the potential in a polysilicon grain under the influence of a transverse field produced by the gate shows that the channel mobility can be described by an activation energy which depends on the gate voltage. Calculated drain currents based on parameters derived from Hall measurements are in good agreement with actual devices. In addition, circuits such as a latch with a liquid crystal driver are described.

Method of making planar thin film transistors, transistor arrays

Abstract: A planar thin film transistor is described wherein each element of the transistor structure is disposed in a planar relationship with respect to the next adjacent layer. The method of manufacture generally includes the steps of depositing one of the elemental members of a thin film transistor structure and filling in the valleys between the elemental structure with an insulating material to form a planar surface which, in turn, forms the surface upon which the next planar layer is formed.

Design and fabrication of large-area thin-film transistor matrix circuits for flat-display panels

Abstract: This paper reports the design principles and fabrication process for large-area thin-film transistor matrix circuits for flat-panel displays developed in our laboratory. It is demonstrated that thin-film transistors can be made reproducibly with desirable characteristics. Opens in bus bars and shorts through insulators are the major causes of defects in the matrix circuit and can be reduced by careful process control. Many near-perfect matrix circuits have been fabricated.

Process for producing a field-effect transistor

Abstract: The process of the invention allows, by placing a silicon nitride layer between a first silicon oxide layer developed on a silicon wafer and a second silicon oxide layer developed from polycrystalline silicon grid electrodes, a double self-alignment of the grid electrodes to be obtained which are used as a mask with respect to the channel-forming zones of the transistor and of these same grid electrodes used as a mask with respect to the connections for the source regions of this same transistor, the source regions being obtained by diffusion in the silicon wafer of the dopant of a doped polycrystalline silicon layer forming the connections of the source regions.

Electrical and structural properties of cadmium selenide thin film transistors

Abstract: Stable thin film transistors based on cadmium senenide and silicon dioxide have been prepared. The degree of stability implies a decay of only 10% in drain current in 100 years of continuous d.c. operation. The decay is solely due to tunnelling of electrons into insulator traps and has a logarithmic time dependence. The devices have field effect mobilities up to 140 cm 2 . Volt −1 sec −1 , switching ratios in the range 10 5 –10 6 , and good reproducibility. The CdSe films contain the hexagonal structure and grain growth occurs during anneal. Grain size and distribution are reproducible from run to run.

Laser Induced Crystal Growth of Silicon Islands on Amorphous Substrates

Abstract: The importance of controlled lateral heat flow in the growth of single crystal silicon islands on amorphous substrates is demonstrated. In one approach the thermal profile on and around the islands is determined by varying the optical absorption with a variety of thin film structures. In another, beam spot shaping is used. Competitive nucleation is suppressed and continued in-plane epitaxial zone growth is enhanced. In this way we are able to produce single crystal islands 20µm wide and >20µm long. Routine production of such islands would enable new thin film transistor technologies.

Polysilicon interconnects with pin poly diodes

Abstract: A semiconductor device comprising a semiconductor substrate, a plurality of IIL gates formed in the substrate, each consisting of an inverter transistor and an injector transistor, and polysilicon films of P and N conductivity types connected to each other and formed as electrode layers connected with diffusion layers of P and N conductivity types which are formed on the substrate, respectively.

Process for the preparation of large area TFT arrays

Abstract: Thin film transistor arrays are prepared by a vacuum deposition technique wherein only a single deposition of discrete areas of an insulating material are deposited through a mask. No registration is required to form the various elements of the transistors. A unique structure is described wherein the contact of the semiconductor material with the source electrode, the source bus conductors, and the drain electrode is coterminous with conductive material forming the source electrode and bus conductors and the drain electrode.

Nonvolatile MNOS semiconductor memory

Abstract: A semiconductor nonvolatile memory wherein a unit cell is constructed of a series connection consisting of an MNOS (metal--silicon nitride--silicon dioxide--semiconductor) transistor whose gate electrode is made of polycrystalline silicon and an MOS (metal--silicon dioxide--semiconductor) transistor whose gate electrode is also made of polycrystalline silicon, such unit cells being arrayed in the form of a matrix, and wherein the gate electrode of the MOS transistor is used as a reading word line, the gate electrode of the MNOS transistor is used as a writing word line, and a terminal of either of the MNOS transistor and the MOS transistor connected in series and constituting the unit cell is used as a data line.

State of the art in thin film transistor: a review of the used insulator-semiconductor combinations

Abstract: This paper deals with the technology of the thin film transistor (TFT). It deals with the different semiconductors used successfully in a TFT, as well as the different gate insulators employed. A variety of structures have been realized in the past. The most important difficulty with the use of these TFT structures consisted of low frequency instabilities, caused by mobile ions in the insulator and slow states at the semiconductor-insulator interface. Various proposed solutions to these problems will be discussed.

Effect of thermal annealing on thin film transistors processed by photoengraving

Abstract: Thin film transistors (TFTs) are of current interest for addressing large‐area flat panel displays. In most cases, in‐vacuum mechanical masking and successive evaporations in a single pumpdown have been used to define the necessary patterns. While this has the advantage of minimizing contamination of the film interfaces, complex and expensive equipment is needed to fabricate high resolution patterns over large areas. We have, therefore, investigated the use of conventional vacuum deposition and photoengraving processes, similar to those used in silicon integrated circuit technology, and have successfully fabricated CdSe TFTs in which the gate and source‐drain levels have been defined by photoengraving. Al and Cr metallizations and Al2O3 dielectric layers have been used. Well‐saturated transistors with switching ratios of ∠104 and electron mobilities of ∠50 cm2 V−1 s−1 are achieved only after the fabricated structure is thermally annealed. Since some thermal annealing appears to be essential in all of the ...

Method of making a vertical dmos type field effect transistor

Abstract: The invention relates to the DMOS type of field effect power transistors. The process of the invention allows, through the interposition of a layer of silicon nitride (3) between a first silicon oxide layer (2) grown on a silicon wafer and a second silicon oxide layer (5) developed from the gate electrodes (41) of polycrystalline silicon, a double self-alignment of the gate electrodes used as masks with respect to the channel forming regions (6) of the transistor and these gate electrodes used as a mask with respect to the connections of the source regions (8) of the same transistor, the source regions being obtained by diffusion into the silicon wafer the dopant of a polysilicon layer (7) constituting the connections doped source regions . Application to the fabrication of transistors in DMOS power Field Effect discrete or integrated vertical operation.

Method for the formation of polycrystalline silicon layers, and its application in the manufacture of a self-aligned, non planar, MOS transistor

Abstract: A method for forming a self-aligned MOS power transistor. A layer of silicon nitride is deposited uniformly over a plate with limited oxide zones. The plate is then placed in an acid bath and subjected to a potential difference. Only the zones of the polycrystalline silicon layer which are over the silica zones remain.

Semiconductor structure with improved isolation between two layers of polycrystalline silicon

Abstract: In a field effect device such as a charge coupled device or field effect transistor in which at least two levels of polycrystalline silicon conductors are used; these two levels of polycrystalline silicon are isolated from one another with a dielectric layer. Disclosed is a composite dielectric layer formed either by in situ oxidation of the first polycrystalline silicon layer plus chemical vapor deposited silicon dioxide or, in the alternative, the composite dielectric layer is formed by a phosphosilicate glass layer with thermal reoxidation of the first polycrystalline silicon layer.

A thin-film transistor with polytetrafluoroethylene as insulator

Abstract: The fabrication and performance characteristics of a new kind of thin-film transistor is presented. The novelty consists of the use of a thin polymer film as an insulator between gate and semiconductor film. The insulator used is polytetrafluoroethylene film, evaporated by an electron gun. The semiconductor used is a tellurium film, evaporated by resistive heating. The transistor shows useful current/voltage characteristics, but the isulator and the insulator ? semiconductor interface show slow-drift phenomena, analogous to the drift seen in most conventional thin-film transistors with an inorganic insulator film.

MOS integrated circuit mfr. - using local oxidn. of silicon to separate active transistor zone in silicon semiconductor substrate

Abstract: In the circuits, the active transistor zones in a p- or n- doped semiconductor substrate(1) are sepd. by silica layers obtd. by LOCOS (local oxidn. of silicon); and the usable voltage is increased by field ion implantation in the field oxide. The substrate is first coated with thermal oxide (2), which is implanted with nitrogen ions to form an implanted oxide (4). The N-ion concn. (C-N) in the substrate must remain below its dopant concn. A photolacquer mask(5) is used to define the active transistor zones; and layer(4) is etched off where field oxide is to be formed. Field ions are then implanted, followed by removing mask(5) and creating the field oxide zones. Layer (4) is next removed and gate oxidn. employed. Alternatively, layer (4) may be used as the gate oxide. Used in very large scale integration technology, to achieve min. dimensions without "birds' beaks".