Showing papers on "Thin-film transistor published in 1989"

The physics of amorphous-silicon thin-film transistors

Abstract: The basic physics underlying the operation and key performance issues of amorphous-silicon thin-film transistors (TFTs) are discussed. The static transistor characteristics are determined by the localized electronic states that occur in the bandgap of the amorphous silicon. The deep states, mostly consisting of Si dangling bonds, determine the threshold voltage, and the conduction band-tail states determine the field-effect mobility. The finite capture and emission times of the deep localized states lead to a dynamic transistor characteristic that can be described by a time-dependent threshold voltage. The transistors also show longer time threshold voltage shifts due to two other distinct mechanisms: charge trapping in the silicon nitride gate insulator and metastable dangling bond state creation in the amorphous silicon. These two mechanisms show characteristically different bias, temperature, and time dependencies of the threshold voltage shift. Illumination of a TFT causes the generation of electron-hole pairs in the space-charge region leading to a steady-state equal flux of electrons and holes and a reduction in the band-bending. In most applications, the photosensitivity should be minimized. The uniformity of large arrays of transistors for display applications is excellent, with variations in the threshold voltage of 0.5-1.0 V. >

High-performance TFTs fabricated by XeCl excimer laser annealing of hydrogenated amorphous-silicon film

Abstract: High-performance staggered a-Si:H and poly-Si thin-film transistors (TFTs) fabricated by XeCl excimer laser annealing of a-Si:H films are discussed. The field-effect mobility of poly-Si TFT is 102 cm/sup 2//V-s, and that of a-Si:H TFT is 0.23 cm/sup 2//V-s. Their drain current on/off ratios are over 10/sup 6/. Except for the crystallization, the fabrication process was the same for both of them. This process appears extremely promising for the integration of matrix elements and peripheral drivers in a single substrate. >

Development and electrical properties of undoped polycrystalline silicon thin-film transistors

Abstract: The conduction mechanism and the origins of the leakage current in undoped channel polycrystalline silicon thin-film transistors fabricated under a variety of processing conditions were investigated. Leakage currents below 1 nA at drain-source voltages of 40 V were achieved in both n-type and p-type devices. The effective channel electron and hole mobilities were 75 and 42 cm/sup 2//V-s, respectively. Measured stage delay times for CMOS ring oscillators as a function of supply voltage agreed well with theoretical calculations. The effective carrier mobility was shown to have a minimum at a gate voltage corresponding to the point at which all traps are filled. Both dark and photoinduced leakage currents were determined to be controlled by generation from the grain boundary traps. The voltage drop across individual gates in multigated structures was investigated as a function of gate voltage. The use of multiple gates at high drain-source potentials was found to decrease both dark and photoinduced leakage currents. >

XeCl Excimer Laser Annealing Used to Fabricate Poly-Si TFT's

Abstract: Polycrystalline silicon thin-film transistors (poly-Si TFT's) with a high carrier mobility were fabricated at low processing temperatures of 150 and 250°C. A hydrogenated amorphous silicon (a-Si:H) film was successfully crystallized at room temperature by multistep irradiation of XeCl-308 nm excimer laser pulses without explosive evaporation of hydrogen. The poly-Si TFT's fabricated by the 250°C process had a carrier mobility of 54 cm2/Vs and a low potential barrier height at a grain boundary of 0.01 eV.

A new analytic model for amorphous silicon thin‐film transistors

Abstract: We present a new theory describing current‐voltage characteristics of amorphous silicon thin‐film transistors. We calculate the output conductance in saturation by considering channel shortening effects caused by the space‐charge‐limited current in the pinch‐off region. In this model the drain current is expressed through the free‐carrier concentration at the source side of the channel. This allows us to obtain an accurate description of the different operating regimes of a thin‐film transistor using one equation that accounts for the dependence of the free‐carrier concentration in the channel for different regimes. Our model is in good agreement both with experimental data and the results of our two‐dimensional computer simulation. This approach allows one to account for different distributions of localized states in the energy gap. The model has also been developed to be incorporated into a circuit simulator and used for computer‐aided design of amorphous silicon integrated circuits.

Low-temperature fabrication of high-mobility poly-Si TFTs for large-area LCDs

Abstract: A low-temperature process developed for fabrication of high-mobility polycrystalline silicon thin-film transistors (poly-Si TFTs) is discussed. Its main feature is the use of a sputter-deposited Si film followed by laser irradiation and a sputter-deposited gate SiO/sub 2/ film. The poly-Si TFTs have a mobility of 350-cm/sup 2//V-s. They have been successfully applied to peripheral circuits for large-area liquid-crystal displays (LCDs). >

Active matrix panel having display and driver TFT's on the same substrate

Abstract: An active matrix panel including a matrix of driving electrodes couples through thin film transistor switches to a corresponding source line and gate line and at least one of a driver circuit including complementary thin film transistors for driving the source and/or gate lines of the picture elements on the substrate. The thin film transistors of the active matrix have the same cross-sectional structure as the P-type or the N-type thin film transistors forming the driver circuit and are formed during the same patterning process.

High performance low-temperature poly-Si n-channel TFTs for LCD

Abstract: High-performance poly-Si TFTs were fabricated by a low-temperature 600 degrees C process utilizing hard glass substrates. To achieve low threshold voltage (V/sub TH/) and high field-effect mobility ( mu /sub FE/), the conditions for low-pressure chemical vapor deposition of the active layer poly-Si were optimized. Effective hydrogenation was studied using a multigate (maximum ten divisions) and thin-poly-Si-gate TFTs. The crystallinity of poly-Si after thermal annealing at 600 degrees C depended strongly on the poly-Si deposition temperature and was maximum at 550-560 degrees C. The V/sub TH/ and mu /sub FE/ showed a minimum and a maximum, respectively, at that poly-Si deposition temperature. The TFTs with poly-Si deposited at 500 degrees C and a 1000-AA gate had a V/sub TH/ of 6.2 V and mu /sub FE/ of 37 cm/sup 2//V-s. The high-speed operation of an enhancement-enhancement type ring oscillator showed its applicability to logic circuits. The TFTs were successfully applied to 3.3-in.-diagonal LCDs with integration of scan and data drive circuits. >

Thin film semiconductor and process for producing the same

Abstract: A thin film semiconductor which comprises a substrate, a single crystalline silicone thin film layer and an intermediate layer disposed between the substrate and the single-crystalline silicon thin film layer. Coefficient of the thermal expansion of the intermediate layer is between those of the substrate and the single-crystalline silicon. The intermediate layer absorbs thermal stress and relaxes strain remaining in the silicon layer, which strain is generated due to difference of thermal expansion coefficient between the substrate and the silicon layer. Due to the arrangement of the intermediate layer, it becomes possible to use various material as the substrate without generating micro-cracks and produce a semiconductor device using a large sized substrate.

Gate dielectric and contact effects in hydrogenated amorphous silicon‐silicon nitride thin‐film transistors

Abstract: The characteristics of glow‐discharge hydrogenated amorphous silicon‐silicon nitride (a‐Si:H/a‐SiNx:H) thin‐film transistors (TFTs) are reported for various deposition conditions. TFTs incorporating a N‐rich nitride gate dielectric, a‐SiN1.6:H, are superior to a‐Si:H TFTs with a Si‐rich gate nitride, a‐SiN1.2:H. In particular, the N‐rich gate nitride TFTs show considerably less interface or near‐interface charging during operation, improved stability, and a higher field‐effect mobility. The average field‐effect mobility μFE is found to be 0.27 and 0.41 cm2/V s for the Si‐ and N‐rich gate nitride TFTs, respectively. A further improvement in mobility, μFE =0.61 cm2/V s, is achieved by increasing the N‐rich gate nitride deposition temperature from 250 to 450 °C. These results suggest that N‐rich a‐SiNx:H, deposited at elevated temperatures, yields a more abrupt or ‘‘cleaner’’ a‐SiNx:H/a‐Si:H interface. We also show, for the first time, that using n+ μc‐Si:H source‐drain contacts in place of n+ a‐Si:H improve...

Characterization of front and back Si-SiO/sub 2/ interfaces in thick- and thin-film silicon-on-insulator MOS structures by the charge-pumping technique

Abstract: It is shown that the charge-pumping technique can be successfully applied to SOI structures, directly providing important and reliable information about the quality of both front- and back-gate interfaces. The possibility of performing measurements on a transistor level makes direct correlation with other MOS characteristics and material parameters possible. In particular, the ability of this technique to perform measurements on thin-film transistors and to separate the information from front and back gates makes it indispensable for characterization of advanced SOI CMOS structures. Although the technique was demonstrated only on 5- mu m channel length devices, it has sufficient sensitivity to be applicable to transistors of micrometer and submicrometer dimensions. Charge-pumping measurements on laser-recrystallized SOI MOSFETs showed that the front interface is only slightly deteriorated compared to that of bulk MOSFET devices, while the back interface is of a substantially lower quality, with about 10 times higher interface trap densities. >

Active matrix panel

Abstract: An active matrix panel comprises a picture element matrix (22), which is mounted on a transparent substrate (71, 86) and which includes a plurality of gate lines (24, 25), a plurality of source lines (26, 27, 28) and a plurality of picture elements (32, 33). Each of the picture elements includes a thin film transistor (29, 101). The active matrix panel further includes a gate line drive circuit (21) and a source line drive circuit (12) and being characterised in that at least one of the gate line drive circuit and the source line drive circuit comprises a plurality of complementary thin film transistors (47 to 56; 58, 59; 99, 100) provided on the transparent substrate. The complementary thin film transistors comprise a P type thin film transistor including acceptor impurities in the source region and the drain region thereof and an N type thin film transistor including acceptor impurities and donor impurities in the source region and the drain region thereof, the donor impurities in the N type thin film transistor having a higher concentration than the acceptor impurities in the n type thin film transistor.

Thin film transistor panel and manufacturing method thereof

Abstract: A thin film transistor panel has a substrate on which a plurality of electrode lines are aligned in a matrix form, thin film transistors (T3) which are formed on crossing portions of the plurality of the electrode lines, a diffusible insulating film (38) for covering said thin film transistors (T3), and metal-diffused layers (38a) connected to source electrodes. The metal-diffused layers are formed by diffusing a metal into predetermined areas of said insulating film (38). If the metal-diffused layers (38a) are used as the pixel electrodes, high density display can be obtained due to the fine pixel electrodes. In addition, a manufacturing method of thin film transistor panel having the steps of forming gate electrodes (32) on a substrate (31), forming gate insulating films (33) on the gate electrodes (32), forming semiconductor layers (34) on said gate insulating films (33), forming source and drain electrodes (36, 37) on said semiconductor layers (34) except for channel portions, forming a diffusible insulating film (38) which covers the whole surface of the substrate (31), providing contact holes (39) in said diffusible insulating film (38) corresponding to said source electrodes (36), and forming metal-diffused layers (38a) by diffusing a metal into the diffusible insulating film (38) and inner surfaces of said contact holes (39). The metal-diffused layers (38a) can be formed in high pattern accuracy, and the fine pixel electrodes can be easily obtained if the metal-diffused layers (38a) are used as the pixel electrodes.

Thin-film transistor

Abstract: PURPOSE: To suppress an increase in a current by the irradiation with light by forming a noncrystalline semiconductor film of a polycrystallized region and the residual region of an amorphous semiconductor film, and providing the residual amorphous region corresponding to the position of a gate electrode film. CONSTITUTION: An insulating board 1, a gate electrode 2, a gate insulating film 3, an amorphous semiconductor film 4, a polycrystalline semiconductor film 6, an impurity implanted amorphous semiconductor layer 7, drain and source electrodes 8, 8, a passivation film 9 and a shielding film 10 are provided. In this case, the film 4 is formed of a polycrystallized region irradiated with a high energy beam to amorphous semiconductor and the residual region of the amorphous semiconductor film, and the residual region is provided corresponding to the position of the film 2. Accordingly, the amorphous region sensitive to light for forming a semiconductor operation channel can shield light projected from the side of the electrode 2 by the electrode 2, and even if the light is directed to the polycrystallized region having low sensitivity to the light which is not shielded, characteristic change can be suppressed. Thus, stable switching characteristic which is not affected by the influence of the light is obtained. COPYRIGHT: (C)1991,JPO&Japio

Active matrix type liquid crystal display

Abstract: An active matrix type liquid crystal display device includes a substrate on which a matrix picture element electrodes reside, TFTs which are disposed in the vicinity of each picture element electrodes, and capacitor electrodes are provided, each of which is opposed to one portion of each of the picture element electrodes. A dielectric lamination structure consisting of three insulating layers is formed between the picture element electrode and the capacitor electrode. The dielectric lamination structure includes an anodic oxidation film, a gate insulating layer and a protective insulating layer. The protective insulating layer further extending over the associated TFT.

Method for producing amorphous silicon thin film transistor array substrate

Abstract: A method for producing an amorphous silicon thin film transistor array substrate comprising successively coating a gate insulating layer, an amorphous silicon layer and a protective insulating layer on a glass substrate provided with a gate electrode and a gate wiring having a predetermined shape, in such a manner as to not cover the connecting terminal region of the gate wiring. A protective insulating layer is patterned into a predetermined shape. After passing through a predetermined production process to produce an amorphous silicon thin film transistor array, at least a gate wiring and a source wiring are provided. The step of patterning the protective insulating layer comprises covering the connecting terminals of the gate wiring and the exposed region of the glass substrate with a photoresist.

Thin-film transistor

Abstract: A thin-film transistor comprising a substrate (1), a gate electrode (2) formed on said substrate (1), gate insulation film (3, 4, 5) formed on said gate electrode (2), semiconductor film (6) formed on said gate insulation film (3, 4, 5) and source and a drain electrode (9₁, 9₂), both formed on said semicnductor film (6) This thin-film transistor is characterized in that said gate electrode (2) is made of Mo-Ta alloy containing 60 to 85 atomic % of Ta, and said gate insulation film is made of a laminated layer including silicon nitride film (5) and oxide film (3) formed by oxidizing the surface of said gate electrode (2)

Liquid crystal display element

Abstract: PURPOSE:To improve problems of a color sepn. characteristic and medium contrast and to obtain an active matrix type color liquid crystal display element having the good color sepn. characteristic by interposing a dielectric material between 1st and 2nd transparent electrodes of each picture element of a liquid crystal display element and providing the same in the form of a thin film as a capacity or resistor on a counter substrate. CONSTITUTION:The 1st transparent electrode film 21 and the dielectric material 22 consisting of a film insulator are formed on the glass substrate 20. This transparent electrode film 21 is formed by a sputtering, plasma CVD method, etc., and the size of the additive capacity is so changed as to change the film area by selecting the material from materials having different dielectric constants and changing the dielectric constant. The 2nd transparent electrode film 23 is formed thereon. Plural color filters 24, 25, 26 and black stripe layer 27 are further formed thereon to constitute the counter substrate of a thin film transistor Tr substrate. The signal of a data line Y is distributed to the additive capacity 18 by turning on the Tr 17 for one picture element of the cell 16 and the liquid crystal 19 is driven by the voltage suitable for each color picture element.

Electrical Characteristics of High-Mobility Fine-Grain Poly-Si TFTs from Laser Irradiated Sputter-Deposited Si Film

Abstract: Electrical characteristics of n-channel fine-grain polycrystalline silicon thin-film transistors (poly-Si TFTs) fabricated from a sputter-deposited Si film irradiated with laser light have been measured. The fine-grain poly-Si TFTs have attained a high mobility of 383 cm2/Vs despite a small grain size from 40 nm to several hundred nanometers. The high-mobility fine-grain poly-Si TFTs feature decreases in mobility with gate voltage and decreases in drain current with temperature in a manner similar to single-crystal MOSFETs. They also show a low carrier trap state density Nst at grain boundaries of 5.6×1011 cm-2. High mobility in the poly-Si TFTs is due to a low Nst.

Shared gate CMOS transistor

Abstract: A stacked shared-gate CMOS transistor and method of fabrication are disclosed. An improved CMOS transistor is fabricated by the formation of a bulk transistor and an overlying isolated (SOI) transistor wherein each transistor is adjoined to a portion of a shared gate having the same conductivity type as the related transistor. The differential conductivity of the shared gate is obtained by the fabrication of a conductive diffusion-barrier layer intermediate to conductive layers. Improved switching performance is obtained as a result of higher current levels produced by the isolated transistor.

Vertical gate thin film transistors in liquid crystal array

Abstract: Vertical gate thin film transistors are integrated into an actively addressable liquid crystal array to provide the switching function for charging each pixel element and any desired peripheral transistor circuitry. One of the conductive plates of each pixel of the array includes an extended portion. The address lines for the switching/charging transistors form a grid between the rows and columns of pixels and each intersection of the grid lies on an extended portion of a pixel element with the drain of the associated transistor formed directly on the extended portion. The source of the transistor is that portion of one set of address lines lying superjacent but insulated from the transistor drain. The gate of the transistor is that portion of the second set of address lines which is adjacent but insulated from the edges of the source and drain, lying essentially perpendicular to the substrate. Additional transistors for the peripheral circuitry are formed by the same process steps which form the pixel elements and the switching transistor.

Method of making a thin film transistor

Abstract: The present invention relates to a semiconductor device in which a semiconductor element is formed on a semiconductor layer (3) supported on a substrate (1) via at least insulating layers (2) and (4) as shown in FIGS. 1 and 2 and a method of fabricating the same. The semiconductor layer (3) has wiring layers (5) and (6) on both surfaces thereof, thus leading itself well for increasing the density of wiring and for increasing the operation speed in a large-scale integrated circuit device.

Liquid crystal display device and method of manufacturing the same

Abstract: A liquid crystal display device comprises a plurality of display electrodes which are selectively energized through on-off control of thin film transistors. In order to reduce the channel length of the thin film transistors to increase operation speed and obtain uniform characteristics, each display electrode and an associated transistor source electrode is formed on one of a pair of transparent substrates of the liquid crystal display device, a semiconductor layer is formed between the display layer and source electrode, a gate insulating film is formed on the semiconductor electrode, and a gate electrode is formed on a portion of the gate insulating film between the display electrode and source electrode. Then, ions are implanted into the semiconductor layer with the gate electrode used as a mask, thus rendering portions of the semiconductor layer contiguous to the display electrode and source electrode into ohmic layers. A channel is thus obtained between the ohmic layers with its length determined by the length of the gate electrode.

UV pulsed laser annealing of Si+ implanted silicon film and low-temperature super-thin film transistors

Abstract: A UV pulsed excimer laser was irradiated onto Si+-implantated thin silicon films. The resultant crystallized state was investigated by UV reflectance measurement and TEM observation. As a result, we found that the grain size depended on the irradiated pulse energy, and that the grain growth was more effective for a smaller Si+ dose, in the low-pulse-energy region of less than 200 mJ/cm2. Moreover, for efficient annealing, the back-side irradiation through the quartz substrate was preferable to the front-side irradiation upon the silicon surface. Using this method, TFT's were fabricated in a low-temperature process, and excellent device characteristics were obtained. The leakage current was below 1×10-13 (A/µm).

Active matrix array

Abstract: PURPOSE:To obtain a high picture quality display being free from a luminance difference by setting the parasitic capacity generated between a picture element electrode and two pieces of signal lines being adjacent thereto and a resistance to almost the same, and also, reversing the polarity of the potential of each adjacent signal line and driving it. CONSTITUTION:The matrix array is provided with the source - drain capacity of a thin film transistor Tnm, and a capacitor Cnm corresponding to a transistor OFF resistance, and a resistance Rnm. That is, that which consists of the same structure as the thin film transistor Tnm and has no gate electrode is formed between a picture element Pnm and a signal line Ym + 1. In this state, the potential polarity of a signal line Ym is inverted against the opposed common potential at every one screen scan, and also, the potential of each adjacent signal line Ym is set to the opposite polarity. Accordingly, the influence of the source - drain parasitic capacity of the transistor Tnm is offset by inversion driving of the signal line, and also, a leak of the picture element potential to the signal line potential due to an OFF resistance of the transistor Tnm becomes the same in the upper and the lower parts on the screen. In such a way, a high picture quality display being free from a luminance difference can be obtained.

Drastically improved performance in poly-Si TFTs with channel dimensions comparable to grain size

Abstract: Poly-Si thin-film transistors (TFTs) with channel dimensions (width, W, and length, L) comparable to the grain size of the film were fabricated and characterized. The grain size of the film was enhanced by Si ion implantation followed by a low-temperature anneal. A remarkable improvement was observed in the device performance as the channel dimensions decreased to W=L=2 mu m. The TFTs with submicron channel dimensions were characterized by an extremely abrupt switching in their transfer characteristic. The improvement was attributed to the floating-body effect as well as the minimization of the grain boundary effect. It is believed that the results obtained will have impact in the development of large-area devices such as active-matrix liquid-crystal displays and image sensors with on-glass circuits. >

Manufacture of thin-film transistor

Abstract: PURPOSE:To facilitate manufacturing process and increase in area and to obtain a TFT without any step achieving a large-area and large-capacity display by burying a metal material for achieving electrode contact for the TFT into the surface of an insulation substrate and then making smooth the surface of the insulation substrate. CONSTITUTION:A gel film 11 is applied on a glass substrate 1 and a mold material 13 is pressed against the surface of the gel film 11. The glass substrate 1 is subjected to heat treatment and a recessed part 12 is formed on the surface of the gel film 11. The glass substrate 1 with the gel film 11 on the surface is subjected to heat treatment and a glass body 14 is formed. Then, a metal film 15 which becomes the gate wiring of an TFT array is formed on the glass body 14. The surface of the glass body 14 is polished and the material film 15 is allowed to remain only at the recessed part 12. Then, the surface of the glass body 14 is smoothed along with the surface of the metal film 15, thus reducing the resistance of the metal wiring and solving the problem of gate wire propagation delay generated at the internal parasitic resistance of the metal film. Also, the TFT formation and combination efficiency to the insulation substrate can be improved.

Method for forming a thin layer on a semiconductor substrate

Abstract: A method and apparatus for manufacturing a semiconductor device having a thin layer of material formed on a semiconductor substrate with a much improved interface between them are disclosed. A silicon substrate is heated up to a temperature around 300° C. in the presence of ozone gas under exposure to UV light. Through this process, organic contaminants that might be present on the surface of the silicon substrate are dissipated by oxidation, and a thin oxide film is formed on the substrate surface on the other. The silicon substrate with the thin oxide film coated thereon is then heated up to temperature of 200°-700° C. in the presence of HCl gas under illumination to UV light to strip the oxide film off the substrate surface, thereby exposing the cleaned substrate surface. Finally, HCl cleaned surface of the silicon substrate is coated with a thin layer of material such as monocrystalline silicon without exposing the cleaned substrate surface. The method provides a semiconductor device with the thin layer of material formed thereon having a well-controlled, well-organized interface between them.

Vapor deposition method for simultaneously growing an epitaxial silicon layer and a polycrystalline silicone layer over a selectively oxidized silicon substrate

Abstract: A method for simultaneously forming an epitaxial silicon layer on a surface of a silicon substrate, and a polysilicon layer on a silicon dioxide (SiO 2 ) layer which is formed on the silicon substrate using a low pressure silicon vapor deposition method, employing silicon hydride gas, particularly disilane (Si 2 O 6 ), as a silicon source gas. A crystal growing temperature ranging from 780° C. to 950° C. and a reaction gas pressure ranging from 20 Torr to 300 Torr are desirable. An extended silicon epitaxial region is achieved under a higher temperature and a higher gas pressure, and with a substrate of a (100) orientation. A polysilicon layer having an even surface and joining smoothly to an epitaxial silicon layer which is simultaneously formed, is obtained under a lower temperature and a lower gas pressure, and with a substrate of a (111) orientation.