Showing papers on "VHDL published in 2020"

FPGA Stream-Monitoring of Real-time Properties

Abstract: An essential part of cyber-physical systems is the online evaluation of real-time data streams. Especially in systems that are intrinsically safety-critical, a dedicated monitoring component inspecting data streams to detect problems at runtime greatly increases the confidence in a safe execution. Such a monitor needs to be based on a specification language capable of expressing complex, high-level properties using only the accessible low-level signals. Moreover, tight constraints on computational resources exacerbate the requirements on the monitor. Thus, several existing approaches to monitoring are not applicable due to their dependence on an operating system. We present an FPGA-based monitoring approach by compiling an RTLola specification into synthesizable VHDL code. RTLola is a stream-based specification language capable of expressing complex real-time properties while providing an upper bound on the execution time and memory requirements. The statically determined memory bound allows for a compilation to an FPGA with a fixed size. An advantage of FPGAs is a simple integration process in existing systems and superb executing time. The compilation results in a highly parallel implementation thanks to the modular nature of RTLola specifications. This further increases the maximal event rate the monitor can handle.

Design, FPGA implementation and statistical analysis of chaos-ring based dual entropy core true random number generator

Abstract: In this paper, a novel chaos-ring based dual entropy core TRNG architecture on FPGA with high operating frequency and high throughput has been performed and presented. The design of dual entropy core TRNG has been generated by uniting the chaotic system-based RNG and the RO-based RNG structures on FPGA. The chaotic oscillator structure as the basic entropy source has been implemented in VHDL using Euler numerical algorithm in 32-bit IQ-Math fixed point number standart on FPGA. The designed chaotic oscillator has been synthesized for the FPGA chip and the statistics related to chip resource consumption and clock frequencies of the units have been presented. The RO-based RNG structure has been designed as the second entropy source. Chaos-ring based dual entropy core novel TRNG unit have been created by combining of these two FPGA-based structures in the XOR function used at the post processing unit. The throughput of the designed dual entropy core TRNG unit ranges 464 Mbps. The output bit streams obtained from FPGA-based novel TRNG have been subjected to NIST 800-22 test suites.

VLSI Implementation of Image Compression using TSA Optimized Discrete Wavelet Transform Techniques

Abstract: The Discrete Wavelet transform is one of the best tools for signal and data analysis, It requires efficient hardware implementation in the real-time applications. The submissions established in the field of imaging necessitates compacted architecture. In DWT discrete sampling is accomplished for the wavelets. In this paper, the VLSI implementation of HAAR wavelet-based image compression is proposed and designed. HAAR wavelet transform is one of the easiest methods for image compression because it has coefficients as either 1 or −1. In this work software alone is used for the compression together with optimizing it with a continuous optimization algorithm and provides a hardware-free architecture with low cost. The VHDL work is carried out in Xilinx Platform and provides a truncated power architecture for a concrete application. The same VHDL architecture can also be instigated in FPGA which will harvest hardware effectual compromising outcomes.

Multiplierless chaotic Pseudo random number generators

Abstract: This paper presents a multiplierless based FPGA implementation for six different chaotic Pseudo Random Number Generators (PRNGs) that are based on: Chua, modified Lorenz, modified Rossler, Frequency Dependent Negative Resistor (FDNR) oscillator, and other two systems that are modelled using the simple jerk equation. These chosen systems can be employed in high speed applications because they don’t utilize any hardware multiplier. The proposed PRNGs have been implemented using VHDL, synthesized on Xilinx, using the FPGA: XC5VLX50T, and tested using the NIST statistical suite. Furthermore, a comparison has been established between the performance of all the PRNGs, regarding the implementation area, speed, and the statistical randomness quality. It has been found that the modified Lorenz PRNG has the best randomness quality and the best hardware performance as it can pass all the NIST tests while operating at 298.597 MHz and utilizing only 0.23% and 0.62% from the FPGA’s slice registers and Look-Up-Tables (LUTs) respectively.

Real-Time Hardware in the Loop Simulation Methodology for Power Converters Using LabVIEW FPGA

Abstract: Nowadays, the use of the hardware in the loop (HIL) simulation has gained popularity among researchers all over the world. One of its main applications is the simulation of power electronics converters. However, the equipment designed for this purpose is difficult to acquire for some universities or research centers, so ad-hoc solutions for the implementation of HIL simulation in low-cost hardware for power electronics converters is a novel research topic. However, the information regarding implementation is written at a high technical level and in a specific language that is not easy for non-expert users to understand. In this paper, a systematic methodology using LabVIEW software (LabVIEW 2018) for HIL simulation is shown. A fast and easy implementation of power converter topologies is obtained by means of the differential equations that define each state of the power converter. Five simple steps are considered: designing the converter, modeling the converter, solving the model using a numerical method, programming an off-line simulation of the model using fixed-point representation, and implementing the solution of the model in a Field-Programmable Gate Array (FPGA). This methodology is intended for people with no experience in the use of languages as Very High-Speed Integrated Circuit Hardware Description Language (VHDL) for Real-Time Simulation (RTS) and HIL simulation. In order to prove the methodology’s effectiveness and easiness, two converters were simulated—a buck converter and a three-phase Voltage Source Inverter (VSI)—and compared with the simulation of commercial software (PSIM® v9.0) and a real power converter.

An efficient and adaptable multimedia system for converting PAL to VGA in real-time video processing

Abstract: Real-time video processing has found its range of applications from defense to consumer electronics for surveillance, video conferencing, etc. With the advent of Field Programmable Gate Arrays (FPGAs), flexible real-time video processing systems which can meet hard real-time constraints are easily realized with short development time. Most of the existing solutions have high utilization of system resources and are not quite flexible with many applications. Here we propose a hardware–software co-design for an FPGA-based real-time video processing system to convert video in standard Phase Alternating Line (PAL) 576i format to standard video of Video Graphics Array (VGA)/Super Video Graphics Array (SVGA) format with little utilization of resources. Switching between multiple video streams, character/text overlaying, and skin color detection are also incorporated with the system. The system is also adaptable for rugged applications. VHSIC Hardware Description Language (VHDL) codes for the architecture were synthesized using Altera Quartus II and targeted for Altera Stratix I FPGA. Results achieved confirm that the proposed system performs efficient conversion with very less resource utilization compared to the existing solutions. Since the proposed system is also flexible, many other applications can be incorporated in the future.

LLHD: A Multi-level Intermediate Representation for Hardware Description Languages

Abstract: Modern Hardware Description Languages (HDLs) such as SystemVerilog or VHDL are, due to their sheer complexity, insufficient to transport designs through modern circuit design flows. Instead, each design automation tool lowers HDLs to its own Intermediate Representation (IR). These tools are monolithic and mostly proprietary, disagree in their implementation of HDLs, and while many redundant IRs exists, no IR today can be used through the entire circuit design flow. To solve this problem, we propose the LLHD multi-level IR. LLHD is designed as simple, unambiguous reference description of a digital circuit, yet fully captures existing HDLs. We show this with our reference compiler on designs as complex as full CPU cores. LLHD comes with lowering passes to a hardware-near structural IR, which readily integrates with existing tools. LLHD establishes the basis for innovation in HDLs and tools without redundant compilers or disjoint IRs. For instance, we implement an LLHD simulator that runs up to 2.4x faster than commercial simulators but produces equivalent, cycle-accurate results. An initial vertically-integrated research prototype is capable of representing all levels of the IR, implements lowering from the behavioural to the structural IR, and covers a sufficient subset of SystemVerilog to support a full CPU design.

Intelligent Fault-Prediction Assisted Self-Healing for Embryonic Hardware

Abstract: This paper proposes novel methods for making embryonic bio-inspired hardware efficient against faults through self-healing, fault prediction, and fault-prediction assisted self-healing. The proposed self-healing recovers a faulty embryonic cell through innovative usage of healthy cells. Through experimentations, it is observed that self-healing is effective, but it takes a considerable amount of time for the hardware to recover from a fault that occurs suddenly without forewarning. To get over this problem of delay, novel deep learning-based formulations are proposed for fault predictions. The proposed self-healing technique is then deployed along with the proposed fault prediction methods to gauge the accuracy and delay of embryonic hardware. The proposed fault prediction and self-healing methods have been implemented in VHDL over FPGA. The proposed fault predictions achieve high accuracy with low training time. The accuracy is up to 99.36% with the training time of 2.16 min. The area overhead of the proposed self-healing method is 34%, and the fault recovery percentage is 75%. To the best of our knowledge, this is the first such work in embryonic hardware, and it is expected to open a new frontier in fault-prediction assisted self-healing for embryonic systems.

Customized Posit Adders and Multipliers using the FloPoCo Core Generator

Abstract: The posit number system, which is proposed as a replacement of IEEE floating-point numbers, is in the spotlight of Arithmetic research due to the recent breakthroughs. This format claims to provide more accurate results with the same bitwidth than standard floating point, but the run-time variability during the detection of the posit fields involves a hardware design challenge. In this work, we propose parameterized designs for multiple posit functional units, including addition and multiplication, and integrate them as templates of the FloPoCo framework. The integration of the proposed algorithms within FloPoCo can provide synthesizable VHDL code for posit arithmetic of any possible configuration 〈n, es〉. Experiments show an improvement in terms of area and energy with respect to state-of-the-art works up to 35.9% and 30.8%, respectively.

High throughput and area-efficient FPGA implementation of AES for high-traffic applications

Abstract: This study presents a high throughput field-programmable gate array (FPGA) implementation of advanced encryption standard-128 (AES-128). AES is a well-known symmetric key encryption algorithm with high security against different attacks that are widely used in different applications. The main goal of this study is to design a high throughput and FPGA efficiency (FPGA-Eff) cryptosystem for high-traffic applications. To achieve high throughput, loop-unrolling, inner and outer pipelining techniques are employed. In AES, substitution bytes (Sub-Bytes) is one of the costly functions that occupy a large number of resources and has a large delay. To reduce the area of Sub-Bytes, new-affine-transformation, which is the combination of inverse isomorphic and affine transformation, is proposed and employed. Besides that, AES has been modified according to the proposed architecture. For the first nine rounds, Shift-Rows and Sub-Bytes have been exchanged, and Shift-Rows is merged with Add-Round-Key. To make an equal latency between stages, Mix-Columns is divided into two different stages. AES is implemented in counter mode on Xilinx Virtex-5 using VHDL. The proposed implementation achieves a throughput of 79.7 Gbps, FPGA-Eff of 13.3 Mbps/slice, and frequency of 622.4 MHz. Compared to the state-of-the-art work, the proposed design has improved data throughput by 8.02% and FPGA-Eff by 22.63%.

An FPGA-Based Architecture for the Versatile Video Coding Multiple Transform Selection Core

Abstract: Versatile video coding (VVC) will be released by 2020, and it is expected to be the nextgeneration video coding standard. One of its enhancements is multiple transform selection (MTS) for core transform. MTS uses three different types of 2D discrete sine/cosine transforms (DCT-II, DCT-VIII and DST-VII) and up to 64 × 64 transform unit sizes. With this schema, significant enhancements of the compression ratio are obtained at the expense of more computational complexity on both encoders and decoders. In this paper, a deeply pipelined high-performance architecture is proposed that implements the three transforms for sizes from 4 × 4 to 64 × 64 according to working draft 4 of the standard. The design has been described in very high-speed integrated circuit hardware description language (VHDL), and it has been prototyped in a system on a programmable chip (SoPC). It is able to process up to 64 fps@3840 × 2.160 for 4 × 4 transform sizes. To the best of our knowledge, this is the first implementation of an architecture for VVC MTS supporting the 64 × 64 size.

LLHD: a multi-level intermediate representation for hardware description languages

Abstract: Modern Hardware Description Languages (HDLs) such as SystemVerilog or VHDL are, due to their sheer complexity, insufficient to transport designs through modern circuit design flows. Instead, each design automation tool lowers HDLs to its own Intermediate Representation (IR). These tools are monolithic and mostly proprietary, disagree in their implementation of HDLs, and while many redundant IRs exists, no IR today can be used through the entire circuit design flow. To solve this problem, we propose the LLHD multi-level IR. LLHD is designed as simple, unambiguous reference description of a digital circuit, yet fully captures existing HDLs. We show this with our reference compiler on designs as complex as full CPU cores. LLHD comes with lowering passes to a hardware-near structural IR, which readily integrates with existing tools. LLHD establishes the basis for innovation in HDLs and tools without redundant compilers or disjoint IRs. For instance, we implement an LLHD simulator that runs up to 2.4× faster than commercial simulators but produces equivalent, cycle-accurate results. An initial vertically-integrated research prototype is capable of representing all levels of the IR, implements lowering from the behavioural to the structural IR, and covers a sufficient subset of SystemVerilog to support a full CPU design.

Real-Time FPGA-based HIL Emulator of Power Electronics Controllers using NI PXI for DFIG Studies

Abstract: This paper presents a high-performance hardware-in-the-loop (HIL) system aimed to assist experts in developing and testing power electronics control board and their logic with Real-Time (RT) models of both electrical and mechanical components. For demonstrating the effectiveness of this system for HIL testing, a new industrial doubly-fed induction generator (DFIG) control board is tested based on a comprehensive wind energy conversion model developed in MATLAB/Simulink hardware description language (HDL) coder and LabVIEW environment. The interaction between MATLAB/Simulink and LabVIEW is accomplished by National Instrument (NI) intellectual property (IP) integration node, which loads very high-speed integrated circuit hardware description language (VHSIC-HDL or VHDL) codes (that enable those two software exchange real-time data). LabVIEW implements a VHDL code of electrical model with fixed-point variables on an R-Series reconfigurable input/output (I/O) field-programmable gate array (FPGA) module on NI-PXIe 7858R installed on NI PXIe 1062Q chassis and the mechanical models deployed in its PXIe 8133 central processing unit (CPU). Finally, through a uniquely developed interface-board, the HIL emulator connects to an external DFIG control board. In FPGA, the model and other communicational and logging components’ step-time in each iteration is 5.0 μs. For verifying the results, a comparison is made between the proposed emulator system and Typhoon HIL602+ as a commercially-available HIL system. It is proved that there is little or no significant deviation between the two systems outputs. The proposed HIL emulator does not have the limitation of commercial HIL systems in adding custom-made new components.

An Automatic Design Framework for Real-Time Power System Simulators Supporting Smart Grid Applications

Abstract: Smart grid technology is the next step to the evolution of classical power grids, providing robustness, reliability, and security throughout the network, enabling real-time management and control. To achieve these goals, distributed computing (microgrid concept) and intelligent control algorithms, tailored to the nature and needs of the network under study, are necessary. To deal with the vast diversity of power grids, being able to capture the dynamics of any given network, and create tools for network analysis, apparatus testing, and power grid management, an automatic design framework for real-time power system simulators is needed. In this article, a prototype of this approach is presented, employing Field Programmable Gate Array (FPGA) platforms due to their reconfigurability that enables low-power, low-latency, and high-performance designs, as a first attempt towards an open source platform, compatible with the majority of hardware design suites. It comprises two major parts: (i) a user-oriented section, built in Matlab/Simulink; and (ii) a hardware-oriented section, written in Matlab and Very High Speed Integrated Circuit (VHSIC)-Hardware Description Language (VHDL) code. To verify its functionality, two test power networks were given in a schematic format, analyzed through Matlab code and turned into dedicated hardware simulators with the aid of the VHDL template. Then, simulation results from Simulink and the prototype were compared for error estimation. The results show the prototype’s successful implementation with minimal resources utilization, high performance and low latency in the order of nanoseconds in Xilinx 6- and 7-series FPGAs, therefore proving its modularity and efficient use in many different scenarios, meeting low-latency/real-time requirements while enabling further smart grid research.

Fiber-Fed Distributed Antenna System in an FPGA Software Defined Radio for 5G Demonstration

Abstract: The implementation of high-speed wireless networks, such as currently used fourth generation (4G) systems and future 5G systems, feature challenging processing. Field programmable gate arrays (FPGAs) can straddle research and development for these current and future networks since they provide scaling through reconfigurable logic, high parallelism, and low power consumption. This brief demonstrates an FPGA circuit implementation, with measurements, of a minimal system (a 5G element or “unit cell”): a single-user mobile with antenna diversity and a distributed antenna system (DAS) at the base station. The demonstration system has a bandwidth of 20 MHz, runs at 2.4 GHz, and has two antennas at both the transmitting base station and at the receiving mobile. The modulation is orthogonal frequency division multiplexing (OFDM) with space-time block coding (STBC). The FPGA is a Virtex-6, used for software defined radio (SDR), and this can readily be scaled to handle larger-dimensioned, higher-capacity systems. The receiver has time-offset synchronization, frequency-offset, and channel estimation. The high-level algorithm design (Xilinx System Generator) for these functions and the OFDM-STBC, and the resources consumed on the FPGA during real-time implementation, are included. We also compare the use of coax and fiber for linking the distributed antennas, using off-the-shelf components. The approach used here of combining simulations with physical measurement of a minimal system is a practical way forward for assessing candidate systems for 5G.

Power-Efficient Approximate Newton–Raphson Integer Divider Applied to NLMS Adaptive Filter for High-Quality Interference Cancelling

Abstract: The division datapath is undoubtedly the most complex operation in a wide range of digital signal processing applications, such as in adaptive filtering algorithms. This paper proposes an optimized and approximate integer divider hardware architecture, based on the Newton–Raphson algorithm combining both fixed-point dynamic range and truncation techniques, to speed up that operation. Adaptive filters have been much studied over time, as they comprise one of the most challenging fields in signal processing. This work presents dedicated hardware architectures based on normalized least mean square adaptive filtering algorithms for the power line harmonics interference cancelling. The hardware architectures are based on 2’s complement representation and were described in VHDL and synthesized into a 65 nm CMOS dedicated ASIC. Our results show that the increased approximation level of Newton–Raphson divider approximation presents up to 223 times less power dissipation than the baseline version without our optimization and approximations, providing up to 93 times of power dissipation savings in the complete interference canceller system.

Comparative study of FFA architectures using different multiplier and adder topologies

Abstract: Parallel FIR filter is the prime block of many modern communication application such as MIMO, multi-point transceivers etc. But hardware replication problem of parallel techniques make the system more bulky and costly. Fast FIR algorithm (FFA) gives the best alternative to traditional parallel techniques. In this paper, FFA based FIR structures with different topologies of multiplier and adder are implemented. To optimize design different multiplication technique like add and shift method, Vedic multiplier and booth multiplier are used for computation. Various adders such as carry select adder, carry save adder and Han-Carlson adder are analyzed for improved performance of the FFA structure. The basic objective is to investigate the performance of these designs for the tradeoffs between area, delay and power dissipation. Comparative study is carried out among conventional and different proposed designs. The advantage of presented work is that; based on the constraints, one can select the suitable design for specific application. It also fulfils the literature gap of critical analysis of FPGA implementation of FFA architecture using different multiplier and adder topologies. Xilinx Vivado HLS tool is used to implement the proposed designs in VHDL.

P4 to FPGA-A Fast Approach for Generating Efficient Network Processors

Abstract: This paper presents a framework for converting P4 programs to VHDL and then implementing them on Field-Programmable Gate Array (FPGA) platforms. In this framework, a match-action-based hardware architecture is introduced with clearly designed components, which correspond to the described functionalities in the P4 programs. A pre-built template library is used for the compilation that includes optimized VHDL templates corresponding to specific clearly designed components. From the output of a standard frontend P4 compiler, the proposed compiler extracts parameters and relationships within the functions being employed, maps them to corresponding templates by calling, configuring, optimizing and instantiating them, and finally generates the appropriate FPGA code. A pre-built evaluation library is also proposed that helps the compiler to optimize the implementation during the mapping phase. A prototype of this framework is also implemented and evaluated; in this process, it is found that the generated processors use few resources and have high throughput and low latency. Compared with a state-of-the-art solution, the packet processing time is halved. In addition, the generated processors are able to operate at a line rate of nearly 100 Gigabits per second for a basic layer-3 forwarding application.

High Throughput Implementation of the Keccak Hash Function Using the Nios-II Processor

Abstract: Presently, cryptographic hash functions play a critical role in many applications, such as digital signature systems, security communications, protocols, and network security infrastructures. The new standard cryptographic hash function is Secure Hash Algorithm 3 (SHA-3), which is not vulnerable to attacks. The Keccak algorithm is the winner of the NIST competition for the adoption of the new standard SHA-3 hash algorithm. In this work, we present hardware throughput optimization techniques for the SHA-3 algorithm using the Very High Speed Integrated Circuit Hardware Description Language (VHDL) programming language for all output lengths in the Keccak hash function (224, 256, 384 and 512). Our experiments were performed with the Nios II processor on the FPGA Arria 10 GX (10AX115N2P45E1SG). We applied two architectures, one without custom instruction and one with floating point hardware 2. Finally, we compare the results with other existing similar designs and found that the proposed design with floating point 2 optimizes throughput (Gbps) compared to existing FPGA implementations.

LFSR-Fractal ANN Model applied in R-IEDs for Smart Energy

Abstract: In this research, a novel VHDL model was developed for implementation of self-similar circuits, in reconfigurable hardware. A Reed Solomon coding system (255,k) was selected as a case study. Fractal design techniques and concurrent modeling ware applied. A theoretical contribution was achieved, with the logic model of a Fractal ANN. Likewise; practical advances are obtained with the optimization in terms of hardware resources and energy efficiency. The correspondence of these circuits has been interpreted through LFSR schemes, which constitutes a significant contribution for Reconfigurable IEDs applications in Reconfigurable Systems of Renewable Energy, under criteria of hardware re-usability.

AnyHLS: High-Level Synthesis With Partial Evaluation

Abstract: Field programmable gate arrays (FPGAs) excel in low power and high throughput computations, but they are challenging to program. Traditionally, developers rely on hardware description languages, such as Verilog or VHDL to specify the hardware behavior at the register-transfer level. High-level synthesis (HLS) raises the level of abstraction but still requires FPGA design knowledge. Programmers usually write pragma-annotated C/C++ programs to define the hardware architecture of an application. However, each hardware vendor extends its own C dialect using its own vendor-specific set of pragmas. This prevents portability across different vendors. Furthermore, pragmas are not first-class citizens in the language. This makes it hard to use them in a modular way or design proper abstractions. In this article, we present AnyHLS, an approach to synthesize FPGA designs in a modular and abstract way. AnyHLS is able to raise the abstraction level of the existing HLS tools by resorting to programming language features such as types and higher order functions as follows. It relies on partial evaluation to specialize and to optimize the user application based on a library of abstractions. Then, vendor-specific HLS code is generated for Intel and Xilinx FPGAs. Portability is obtained by avoiding any vendor-specific pragmas at the source code. In order to validate achievable gains in productivity, a library for the domain of image processing is introduced as a case study, and its synthesis results are compared with several state-of-the-art domain-specific language (DSL) approaches for this domain.

A Model-Based Design Floating-Point Accumulator. Case of Study: FPGA Implementation of a Support Vector Machine Kernel Function

Abstract: Recent research in wearable sensors have led to the development of an advanced platform capable of embedding complex algorithms such as machine learning algorithms, which are known to usually be resource-demanding. To address the need for high computational power, one solution is to design custom hardware platforms dedicated to the specific application by exploiting, for example, Field Programmable Gate Array (FPGA). Recently, model-based techniques and automatic code generation have been introduced in FPGA design. In this paper, a new model-based floating-point accumulation circuit is presented. The architecture is based on the state-of-the-art delayed buffering algorithm. This circuit was conceived to be exploited in order to compute the kernel function of a support vector machine. The implementation of the proposed model was carried out in Simulink, and simulation results showed that it had better performance in terms of speed and occupied area when compared to other solutions. To better evaluate its figure, a practical case of a polynomial kernel function was considered. Simulink and VHDL post-implementation timing simulations and measurements on FPGA confirmed the good results of the stand-alone accumulator.

Formal Verification of Control Modules in Cyber-Physical Systems

Abstract: The paper proposes a novel formal verification method for a state-based control module of a cyber-physical system. The initial specification in the form of user-friendly UML state machine diagrams is written as an abstract rule-based logical model. The logical model is then used both for formal verification using the model checking technique and for prototype implementation in FPGA devices. The model is automatically transformed into a verifiable model in nuXmv format and into synthesizable code in VHDL language, which ensures that the resulting models are consistent with each other. It also allows the early detection of any errors related to the specification. A case study of a manufacturing automation system is presented to illustrate the approach.

Lightweight Hardware Architectures for the Piccolo Block Cipher in FPGA

Abstract: The Piccolo block cipher is a lightweight block encryption for hardware use. Hardware devices are equipped with limited computation resources and small memory. In this paper, we propose an implementation to carry out through several trade-offs between area and speed. We implemented the Piccolo block cipher algorithm with 128-bit key in two different architectures on FPGA: the iterative and the 4-bit serial architectures. The proposed implementation was performed on Xilinx Spartan-3. The iterative implementation achieves 76% of resource utilization. This implementation takes 31 clock cycles to perform the encryption or decryption. So, it results in a throughput of 151.1 Mbps. The serial implementation was optimized in terms of area to reduce the cost. It achieves 54% of resource utilization and takes 496 clock cycles resulting in a throughput of 6.39 Mbps.