Showing papers on "Voltage droop published in 2004"

A wireless controller to enhance dynamic performance of parallel inverters in distributed generation systems

Abstract: This paper presents a novel control strategy for parallel inverters of distributed generation units in an AC distribution system. The proposed control technique, based on the droop control method, uses only locally measurable feedback signals. This method is usually applied to achieve good active and reactive power sharing when communication between the inverters is difficult due to its physical location. However, the conventional voltage and frequency droop methods of achieving load sharing have a slow and oscillating transient response. Moreover, there is no possibility to modify the transient response without the loss of power sharing precision or output-voltage and frequency accuracy. In this work, a great improvement in transient response is achieved by introducing power derivative-integral terms into a conventional droop scheme. Hence, better controllability of the system is obtained and, consequently, correct transient performance can be achieved. In addition, an instantaneous current control loop is also included in the novel controller to ensure correct sharing of harmonic components when supplying nonlinear loads. Simulation and experimental results are presented to prove the validity of this approach, which shows excellent performance as opposed to the conventional one.

Control of distributed generation systems - Part II: Load sharing control

Abstract: This work is concerned with the control strategy for the parallel operation of distributed generation systems (DGS) in a standalone ac power supply. The proposed control method uses only low-bandwidth data communication signals between each generation system in addition to the locally measurable feedback signals. This is achieved by combining two control methods: droop control method and average power control method. The average power method with slow update rate is used in order to overcome the sensitivity about voltage and current measurement errors. In addition, a harmonic droop scheme for sharing harmonic content of the load currents is proposed based on the voltages and currents control algorithm. Experimental and simulation studies using two parallel three-phase pulsewidth modulation (PWM) inverters are presented to show the effectiveness of the proposed control.

A voltage and frequency droop control method for parallel inverters

Abstract: In this paper, a new control method for the parallel operation of one or several inverters in an island grid or the mains is described. Frequency and voltage control, including mitigation of voltage harmonics, are achieved without the need for any common control circuitry or communication between the inverters. Each inverter supplies a current that is the result of the voltage difference between a reference AC voltage source and the grid voltage across a virtual impedance with real and/or imaginary parts. The reference AC voltage source is synchronised with the grid, with a phase shift, depending on the difference between nominal and real grid frequency. A detailed analysis show that this approach has superior behaviour in comparison with the existing droop control methods, considering the mitigation of voltage harmonics, short-circuit behaviour and, in the case of a non-negligible line resistance, the 'efficient' control of frequency and voltage. Experiments show the behaviour of the method for an inverter feeding a highly distorted load and during the connection of two parallel inverters in operation.

Design of a capacitor-supported dynamic voltage restorer (DVR) for unbalanced and distorted loads

Abstract: The paper discusses the operating principles and control characteristics of a dynamic voltage restorer (DVR) that protects sensitive but unbalanced and/or distorted loads. The main aim of the DVR is to regulate the voltage at the load terminal irrespective of sag/swell, distortion, or unbalance in the supply voltage. In this paper, the DVR is operated in such a fashion that it does not supply or absorb any active power during the steady-state operation. Hence, a DC capacitor rather than a DC source can supply the voltage source inverter realizing the DVR. The proposed DVR operation is verified through extensive digital computer simulation studies.

High voltage generation and regulation system for digital multilevel nonvolatile memory

Abstract: A high voltage generator provides high voltage signals with different regulated voltage levels. A charge pump generates the high voltage, and includes a quadrature phase forward and backward Vt-canceling high-voltage self-biasing charge pump with a powerup-assist diode. A high voltage series regulator generates the high voltage supply levels, and includes slew rate enhancement and trimmable diode regulation. A nested loop regulator eliminates shunt regulation.

On-die droop detector for analog sensing of power supply noise

Abstract: Understanding the supply fluctuations of various frequency harmonics is essential to maximizing microprocessor performance. Conventional methods used for analog validation of the power delivery system fall short in one or more of the following areas. 1) Measurement accuracy in both frequency and time domains, especially for very high-frequency noise caused by large di/dt events. The multigigahertz power supply noise attenuates very quickly away from the die. Conventional approaches of measuring the noise at the pins of the package or at the die using capacitive probes are not accurate for multigigahertz clocks. For this reason, the observability of high-frequency on-die noise has been very tricky. 2) Implementation (e.g., delivery) of analog references to multiple areas across a "noisy" die, compactness/modularity of the measurement units, restraining assumptions inherent in the measurement circuit such as periodicity of the supply noise event. 3) Automation to enable a timely volume of measurements. The efficiency of the measurements is key to correlating a particular speed path to poser supply noise. To address these issues, this paper presents an on-die droop detector (ODDD), a scalable IC solution implemented and validated on a 90-nm process, for analog sensing of differential high-bandwidth supply noise.

Analysis of series compensation and DC-link voltage controls of a transformerless self-charging dynamic voltage restorer

Abstract: This paper describes a transformerless self-charging dynamic voltage restorer (DVR) series compensation device used to mitigate voltage sags. A detailed analysis on the control of the restorer for voltage sag mitigation and dc-link voltage regulation are presented. A nonlinear element is shown to exist in the regulator, the activation of which can adversely affect its stability. Active cancellation for this element is recommended. Simulation and experimental results are presented for a 1-kVA prototype to validate the analysis as well as demonstrate the DVR's performance under both voltage restoration and self-charging operating conditions.

A 480-MHz, multi-phase interleaved buck DC-DC converter with hysteretic control

Abstract: We propose an on-chip 1.8 V-to-0.9 V DC-DC converter aimed to reduce the input current and decoupling requirements of future microprocessors. By utilizing a 90-nm CMOS process, employing a four-phase hysteretic control, and operating at ultra-high frequency of 480-MHz, we achieved a 10% output droop with only 2.5 nF of on-chip decoupling, for 0.5 A of load current. No off-chip decoupling was connected to the output. At 480 MHz the measured efficiency was 72%. At 250 MHz, the efficiency improved to 76% at the cost of a 17% droop or larger decoupling of 11.5 nF. A converter with 100 A rating would require a capacitor of 0.5 /spl mu/F, which is comparable to the size of an on-chip capacitor of a typical microprocessor.

Decentralized generator scheduling in a nanogrid using DC bus signaling

Abstract: A nanogrid is a small isolated DC power system that uses distributed renewable energy sources in conjunction with storage to supply continuous power to small local loads. Power electronic converters interface the sources and loads to the nanogrid. Power balance in a nanogrid is achieved by scheduling the sources in a decentralized fashion to maintain the modularity and reliability inherent in its distributed structure. This paper presents DC bus signaling as a means of generator scheduling and power sharing in a nanogrid under steady-state conditions. DC bus signaling is a novel control strategy that is a hybrid of the voltage level signaling and voltage droop schemes. Discrete voltage levels on the nanogrid bus indicate the state of the system and determine the behaviour of each source. A case study and simulation results demonstrate the application of DC bus signaling.

Distributed Active Filter Systems (DAFSs): A New Approach to Power System Harmonics

Abstract: This paper proposes a distributed active filter system (DAFS) for alleviating the harmonic distortion of power systems. The proposed DAFS consists of multiple active filter units installed on the same location or different locations within the power system. The active filter units of the proposed DAFS can cooperate, without any communication among them, to reduce the voltage harmonic distortion of the power lines. Each individual active filter unit functions like a harmonic conductance to reduce voltage harmonics. A droop relationship between the harmonic conductance and the volt-ampere of the active filter unit is programmed into the controller of each unit so multiple active filter units can share the workload of harmonic filtering. The slope of the droop is determined by the volt-ampere rating of the active filter unit in order to distribute the harmonic filtering workload in proportion to the rated capacity of each unit. The principle of operation is explained in this paper and test results based on computer simulation and laboratory test bench are provided to validate the functionalities of the proposed DAFS.

Method of measuring threshold voltage for a NAND flash memory device

Abstract: Provided is a method of measuring threshold voltages in a NAND flash memory device. In the method, a test voltage is applied to a wordline of selected memory cells to measure a distribution profile of threshold voltages of memory cells. A voltage summing up a pass voltage and an operation voltage is applied to wordlines of deselected cells. The operation voltage is applied to a well and a common source line. A voltage summing up a precharge voltage and the operation voltage is applied to a bitline. After then, a voltage variation on the bitline can be detected to measure a threshold voltage of a memory cell. A negative threshold voltage can be measured by applying a positive voltage with reference to a voltage, as the threshold voltage of the memory cell, set by subtracting the operation voltage from the test voltage in accordance with the bitline voltage variation.

Output impedance design of parallel-connected UPS inverters

Abstract: This paper deals with the design of the output impedance of UPS inverters with parallel-connection capability. The inner control loops are considered in the design of the controllers that makes possible the power sharing among the UPS modules. In these paralleled units, the power-sharing outer control loops are based on the P/Q droop method in order to avoid any communication among the modules. The power sharing accuracy is highly sensitive to the output impedance of the inverters, making necessary the tight adjustment of this impedance. Novel control loops are proposed to achieve stable output impedance value, and, therefore, proper power balance is guarantee when sharing both linear and nonlinear loads.

Load driving device and portable apparatus utilizing such driving device

Abstract: A load such as an LED and a constant-current source are connected in series with each other between the node of a dc-dc conversion type power supply circuit providing an output voltage and the ground. The constant-current source provides a constant current Io, the magnitude of which can be adjusted. The power supply circuit controls the output voltage such that the voltage drop across the constant-current source serving as a detection voltage becomes equal to a reference voltage. Thus, the load current can be varied within a predetermined range while avoiding the power loss due to an increase in the load current, thereby always permitting efficient operation of the load.

A 10-nW 12-bit accurate analog storage cell with 10-aA leakage

Abstract: Medium-term analog storage offers a compact, accurate, and low-power method of implementing temporary local memory that can be useful in adaptive circuit applications. The performance of these cells is characterized by the sampling accuracy and voltage droop that can be achieved with a given level of die area and power. Hand calculations suggest past implementations have not achieved minimum voltage droop due to uncompensated MOS leakage mechanisms. In this paper, the dominant sources of MOS leakage are experimentally characterized in a standard 1.5-/spl mu/m CMOS process using an on-chip current integration technique, focusing specifically on the 1 fA to 1 aA current range. These measurements reveal an accumulation-mode source-drain coupling mechanism that can easily dominate diode leakage under certain bias conditions and may have limited previous designs. A simple rule-of-thumb is offered for avoiding this leakage effect, leading to a novel ultra-low leakage switch topology. A differential storage cell incorporating this new switch achieves an average leakage of 10 aA at room temperature, an 8/spl times/ reduction over past designs. The cell loses one bit of voltage accuracy, 700 /spl mu/V on a 12-bit scale and 11.3 mV on an 8-bit scale, in 3.3 and 54 min, respectively. This represents a 15/spl times/ increase in hold time at these voltage accuracies over the lowest leakage cell to date, in only 92% of the area. Since the leakage is independent of amplifier bias, the cell can operate on as little as 10 nW of power. Initial measurements also indicate the switch's leakage decreases with the square of process feature size.

Voltage boosting circuit and method

Abstract: A voltage boosting circuit, boosting power supply unit and methods thereof are provided. A boosting power supply unit includes a boosting circuit having a small number of externally-mounted capacitors, which generates stepped-up and stepped-down boosted voltages through charging and pumping under two-phase control, so that the simultaneous output of the stepped-up voltage and the stepped-down voltage, the output of only the stepped-up voltage, the output of only the stepped-down voltage, and the cut-off of the output of the stepped-up voltage and the stepped-down voltage can be controlled on the basis of the phase control signal generated from the enable signals of which the logic states are changed in accordance with an amount of load.

Multi-threshold multi-gain active transient response circuit and method for digital multiphase pulse width modulated regulators

Abstract: Disclosed is a multi-phase pulse width modulated voltage regulator and method in which transient voltage excursions or deviations that exceed the load line voltage by more than a pre-determined amount are detected by an ATR circuit and a correction signal is applied. The correction signal is in the form of asynchronous pulses and the number of such pulses is a function of the magnitude of the voltage excursion as determined by the number of thresholds that are exceeded. Also disclosed is an adaptive voltage positioning (AVP) circuit and method for early detection of a transient event by sensing voltage changes at the load and adjusting the target voltage with pre-determined current values prior to the time that ATR event changes in the current at the load are detected.

Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation

Abstract: Rapidly increasing input current of microprocessors resulted in rising cost and motherboard real estate occupied by decoupling capacitors and power routing. We show by analysis that an on-die switching DC-DC converter is feasible for future microprocessor power delivery. The DC-DC converter can be fabricated in an existing CMOS process (90nm-180nm) with a back-end thin-film inductor module. We show that 85% efficiency and 10% output voltage droop can be achieved for 4:1, 3:1, and 2:1 conversion ratios, area overhead of 5% and no additional on-die decoupling capacitance. A 4:1 conversion results in 3.4x smaller input current and 6.8x smaller external decoupling.

Voltage reference generator circuit subtracting CTAT current from PTAT current

Abstract: A voltage reference generator generates a stable reference voltage that is less than the bandgap voltage of silicon for power supply voltages less than 2V, yet provides sufficient voltage headroom to operate a current mirror. In one embodiment, the voltage reference generator has a power supply rejection ratio of at least 60 dB and has comparable noise performance as compared to traditional bandgap cirucits. These advantages are achieved by subtracting a current proportional to a complement of an absolute temperature from a current proportional to the absolute temperature to generate a voltage having a positive temperature coefficient, which is then added to a voltage that is a complement of the absolute temperature to achieve a voltage that has a low temperature coefficient.

Method and apparatus for detecting on-die voltage variations

Abstract: On-die voltage and/or frequency detectors. For one aspect, an adaptive frequency clock generation circuit includes a droop detector to detect a supply voltage level and to cause the frequency of an on-die clock signal to be adjusted accordingly.

Programmable calibration circuit for power supply current sensing and droop loss compensation

Abstract: A circuit for regulating power is disclosed. The present invention provides circuits and methods for current sensing variations, static droop settings, mismatched phase outputs, and temperature variations in a multiphase power regulator. The circuits may include a calibration controller that senses and regulates both a current sensing circuit and the droop in a power regulator over a range of temperatures thus equalizing phase outputs. The present invention includes the schematic organization and implementation of the circuit, the circuit's calibration, its use, and implementation. This invention advantageously provides circuits and methods to properly power a processor or IC chip according to the unique power specifications of the processor or chip.

On-chip compensation control for voltage regulation

Abstract: Manufacturing and/or operational variations that affect performance of an integrated circuit (IC) are at least partially compensated for, by determining the magnitude of these variations and providing one or more corresponding control signals to a voltage regulator (208), which, responsive thereto, increases or decreases the magnitude of the output voltage (Vdd). The output voltage (Vdd) of the voltage regulator (208) is typically provided to a power supply node of the IC. Similarly, the output of the voltage regulator (208) may be provided to a substrate portion of the IC, so as to provide a substrate bias that is variable in response to changes in the performance of the IC. In various embodiments, a determination of the magnitude of the variations is made by comparing the performance of a digital delay circuit (202)or a ring oscillator to a reference clock (204); speed characterization of the IC may be obtained from the voltage regulator control signals; and information regarding reliability degradation of the IC may be obtained from the control signals that are generated for control of the voltage regulation circuitry (208).

Compressible Dynamic Stall Control Using a Variable Droop Leading Edge Airfoil

Abstract: The control of compressible dynamic stall using a variable droop leading edge airfoil is described. The leading 25% of a VR-12 airfoil is drooped as it executes sinusoidal pitch oscillations such that the leading portion of the airfoil is always at a low effective incidence to the flow. Airfoil performance data determined for freestream Mach numbers ranging from 0.2 to 0.4, at reduced frequencies from 0 to 0.1, and using unsteady pressure transducer measurements, show that droop reduces the tendency of the airfoil to enter the dynamic stall state. Even when it does, the strength of the dynamic stall vortex is significantly reduced, which is reflected in the 40 to 50% smaller negative peak pitching-moment values, with positive damping of the airfoil. Also, the airfoil drag when the droop is dynamically varied is reduced by up to 75% relative to a nondrooped airfoil, making a strong case for the use of this concept for dynamic stall control

Output voltage correction circuit for multiplexed multi-phase hysteretic voltage regulator

Abstract: A method and circuit for compensating offset error caused by multiplexing in hysteretic control loops. An offset voltage, caused by one phase descending without being hysteretically controlled while another phase is being controlled, is determined by a sample-and-hold circuit that is arranged to track a low limit voltage Vlo and a lowest voltage Vvalley. The offset voltage is one half of a difference between Vlo and Vvalley. A timing and control circuit provides timing control voltages to the sample-and-hold circuit based on input signals associated with phase 1 and phase 2. The sample-and-hold circuit provides Vlo and Vvalley to a differential amplifier that is arranged to provide the offset voltage to a hysteretic controller circuit. In one embodiment, the offset voltage is added to a reference voltage for corrected output voltage. In another embodiment, the offset voltage is added to the output voltage.

Experimental Investigation of the Effect of Fiber-mat Architecture on the Unsaturated Flow in Liquid Composite Molding:

Abstract: In liquid composite molding technologies such as RTM, this study of the inlet-pressure history for the constant flow-rate 1-D flow experiment reveals that the measured pressure profile, which droop downwards as in earlier studies on the unsaturated flow, is at a variance with the linear pressure profile predicted by the physics used for state-of-the-art LCM mold filling simulations. The droop along with the error in the inlet-pressure predictions increase with an increase in the fibermat compression. The effect of fiber-mat architecture on the droop in the inletpressure profiles is studied and significant droops are observed for various stitched mats as compared to the woven mats. This study repudiates the long-held view that mere presence of cylindrical or elliptical tows in the woven or stitched fiber-mats automatically leads to the unsaturated flow characteristic of dual-scale porous media; rather the presence of continuous uninterrupted macrochannels along the flow direction for preferential channel-f...

Real-time voltage detection and protection circuit for PFC boost converters

Abstract: A circuit for protection of the operation of power factor correction (PFC) converters from conditions such as input voltage surges that can otherwise cause failure, and to prevent unnecessary down time of the boost converter after a power failure or on startup. The circuit detects the real time rectified input voltage and provides real time comparison of the detected input voltage and the output voltage. The boost function of the PFC is controlled as a function of the output of the comparison circuit so as to quickly inhibit the boost function of the PFC controller thereby disabling boost and protecting the circuit from burning out. The circuit enables the PFC to starts and restart more quickly, even before the output voltage becomes stabilized, since boost is permitted as soon as the output voltage exceeds the real time sampled input voltage. By enabling boost during this period, the circuit eliminates the need to wait at least a few cycle times until the output voltage is higher than the peak of rectified input voltage. In a preferred embodiment, a complementary protection circuit having a voltage clamp is also provided to prevent unnecessary shutdown of the converter.

Voltage conversion device and computer-readable recording medium having program recorded thereon for computer to control voltage conversion by voltage conversion device

Abstract: A control device (30) calculates a voltage command value of a voltage step-up converter (12) based on a torque command value (TR1 (or TR2)) and a motor revolution number (MRN1 (or MRN2)) and calculates an on-duty (DlONl1) of an NPN transistor (Q1) based on the calculated voltage command value and a DC voltage (Vb) from a voltage sensor (10). When the on-duty (DlONl1) is influenced by a dead time of NPN transistors (Q1, Q2), control device (30) fixes the on-duty (DlONl1) at 1.0 to control the NPN transistors (Q1, Q2) in such a manner that the voltage is increased or decreased.

Output impedance performance for parallel operation of UPS inverters using wireless and average current-sharing controllers

Abstract: This paper encompasses the study of the output impedance impact of parallel-connected UPS inverters. Two novel nonlinear control strategies are proposed. The first one is based on the single-wire current-sharing scheme, which is well known in parallel dc-to-dc converter systems. The second one is a wireless control technique derived from the droop method. The output impedance of the inverters is investigated in both cases. Results of two parallel-connected 1-kVA UPS inverters show the feasibility of the proposed approach. Finally, the two proposed controllers are compared between them and those with the existing solutions.

Load control receiver with line under voltage and line under frequency detection and load shedding

Abstract: A method for detecting line under voltage (LUV) events and initializing load shedding of loads located near the electrical disturbance without customer and utility intervention. In one example embodiment, the LUV detection system samples a primary voltage source at regular time intervals, thereby generating a series of voltage readings, and compares the voltage readings to an under voltage trigger threshold. If an under voltage condition is detected, then an under voltage in-response cycle is initialized that controls the electrical load. When the voltage readings decrease to below a voltage-power fail level, a plurality of load restore counter values are stored in memory before the load is shed from the primary voltage source. A restore response is then initialized after the voltage level rises above a restore value and is maintained above the restore value for an under voltage out-time period.

Self-reparable device to generate a high voltage, and method for repairing a device to generate a high voltage

Abstract: A generator produces a high voltage from a power supply voltage. The generator includes an oscillator for producing a driving signal, and a charge pump for producing the high voltage from the power supply voltage based upon receiving the driving signal. The charge pump includes n series-connected voltage step-up stages including a first step-up stage receiving the power supply voltage and a last step-up stage producing the high voltage, at least one replacement step-up stage, and a switching circuit. The switching circuit replaces a damaged one of the n series-connected voltage step-up stages with the at least one replacement stage when a warning signal is received. A voltage regulator produces an activation signal for activating the oscillator if the high voltage is below a desired value. A detector produces the warning signal if the charge pump is defective.

Thermal management system and method

Abstract: A method for determining a fan speed for a fan used to cool a payload is disclosed. The method includes, according to various embodiments, receiving a first signal indicative of a first fan speed and receiving a second signal indicative of a system temperature. The method further includes selecting a temperature setpoint based on the first fan speed and, based on a comparison of the system temperature and the selected temperature setpoint, computing a first fan speed output. A thermal management system and method for determining a speed-setpoint droop characteristic are also disclosed.