Showing papers on "Wafer published in 2001"

Third generation photovoltaics: Ultra‐high conversion efficiency at low cost

Abstract: Since the early days of terrestrial photovoltaics, a common perception has been that ‘first generation’ silicon wafer-based solar cells eventually would be replaced by a ‘second generation’ of lower cost thin-film technology, probably also involving a different semiconductor. Historically, cadmium sulphide, amorphous silicon, copper indium diselenide, cadmium telluride and now thin-film polycrystalline silicon have been regarded as key thin-film candidates. Any mature solar cell technology seems likely to evolve to the stage where costs are dominated by those of the constituent materials, be they silicon wafers or glass sheet. It is argued, therefore, that photovoltaics is likely to evolve, in its most mature form, to a ‘third generation’ of high-efficiency thin-film technology. By high efficiency, what is meant is energy conversion values double or triple the 15–20% range presently targeted, closer to the thermodynamic limit of 93%. Tandem cells are the best known of such high-efficiency approaches, where efficiency can be increased merely by adding more cells of different bandgap to a cell stack, at the expense of increased complexity and spectral sensitivity. However, a range of other more ‘paralleled’ approaches offer similar efficiency to an infinite stack of tandem cells. These options are reviewed together with possible approaches for practical implementation, likely to become more feasible with the evolution of materials technology over the next two decades. Copyright © 2001 John Wiley & Sons, Ltd.

Integration of self-assembled diblock copolymers for semiconductor capacitor fabrication

Abstract: We combine a self-organizing diblock copolymer system with semiconductor processing to produce silicon capacitors with increased charge storage capacity over planar structures. Our process uses a diblock copolymer thin film as a mask for dry etching to roughen a silicon surface on a 30 nm length scale, which is well below photolithographic resolution limits. Electron microscopy correlates measured capacitance values with silicon etch depth, and the data agree well with a geometric estimate. This block copolymer nanotemplating process is compatible with standard semiconductor processing techniques and is scalable to large wafer dimensions.

The Race for the Photonic Chip: Colloidal Crystal Assembly in Silicon Wafers

Abstract: This paper surveys recent developments in engineering physics approaches and self-assembly chemistry methodologies for creating 3D photonic crystals and how this has led to in-wafer patterned colloidal crystals. These materials are comprised of single crystal micrometer scale features of silica colloidal crystals that have controlled thickness, area, and orientation and are embedded within a single crystal silicon wafer. Two processes for growing opal-patterned chips are described. One is based upon microfluidic and the other spin coating driven self-assembly of colloidal silica micro-spheres within a lithographic patterned silicon wafer.

Cycling deposition of low temperature films in a cold wall single wafer process chamber

Abstract: A method for film deposition that includes, flowing a first reactive gas over a top surface of a wafer in a cold wall single wafer process chamber to form a first half-layer of the film on the wafer, stopping the flow of the first reactive gas, removing residual first reactive gas from the cold wall single wafer process chamber, flowing a second reactive gas over the first half-layer to form a second half-layer of the film where deposition of the second half-layer is non self-limiting, controlling a thickness of the second half-layer by regulating process parameters within the cold wall single wafer process chamber, stopping the flow of the second reactive gas; and removing residual second reactive gas from the cold wall single wafer process chamber.

Packaging of light-emitting diode

Abstract: The present invention of “Packaging of Light-Emitting Diode” is mainly to use silicon wafer as the substrate, whose crystal surface has a specific orientation for etching to form grooves. On the back of silicon substrate, dry etching is used for through-hole electrodes. Meanwhile, the insulating oxide layer or the nitride layer on silicon surface is plated with a reflective layer and an electrode layer, so the LED substrate is actually made of “silicon substrate”. Through the procedures including placement of LED chips in the grooves of a silicon substrate, die bonding, wire bonding, encapsulation and cutting, SMD LED can be formed. Compared to traditional LED packaging that uses circuit boards or metal leadframes as main packaging substrates, the present invention is a breakthrough, which uses silicon wafers as substrates, so it has several advantages including good heat dissipation, high heat resistance and easy miniaturization, which are not seen in common LED presently.

Low temperature full wafer adhesive bonding

Abstract: We have systematically investigated the influence of different bonding parameters on void formation in a low-temperature adhesive bonding process. As a result of these studies we present guidelines ...

System for real-time control of semiconductor wafer polishing

Abstract: A system for polishing a semiconductor wafer, the system comprising a wafer polishing assembly for polishing a face of a semiconductor wafer at a polishing rate and a polishing uniformity, the wafer polishing assembly including a platen subassembly defining a polishing area, and a polishing head selectively supporting a semiconductor wafer and holding a face of the semiconductor wafer in contact with the platen subassembly to polish the wafer face; and a controller selectively adjusting one of a plurality of adjustable polishing parameters during polishing of the wafer.

Micromachined chip scale package

Abstract: A chip scale package comprised of a semiconductor die having a silicon blank laminated to its active surface. The bond pads of the die are accessed through apertures micromachined through the blank. The package may be employed with wire bonds, or solder or other conductive bumps may be placed in the blank apertures for flip-chip applications. Further, the package may be employed to reroute external connections of the die to other locations, such as a centralized ball grid array or in an edge-connect arrangement for direct or discrete die connect (DDC) to a carrier. It is preferred that the chip scale package be formed at the wafer level, as one of a multitude of packages so formed with a wafer-level blank, and that the entire wafer be burned-in and tested to identify the known good die (KGD) before the wafer laminate is separated into individual packages.

Fabrication and Optoelectronic Properties of a Transparent ZnO Homostructural Light-Emitting Diode

Abstract: A transparent ZnO homostructural light-emitting diode (LED) with a structure of Au electrode/p(i)-ZnO film/n-ZnO single crystal/In electrode was fabricated using the technique of N2O plasma-enhanced pulsed laser reactive deposition. The contact between the p(i)-ZnO layer and n-ZnO wafer was found to exhibit nonlinear and rectifying current–voltage (I–V) characteristics. A current injection emission with bluish-white light was clearly observed at room temperature, and its intensity increased with increases in the injected electric current.

Method for low temperature chemical vapor deposition of low-k films using selected cyclosiloxane and ozone gases for semiconductor applications

Abstract: A method is described for forming a low-k dielectric film, in particular, a pre-metal dielectric (PMD) on a semiconductor wafer which has good gap-filling characteristics. The method uses a thermal sub-atmospheric CVD process that includes a carbon-containing organometallic precusor such as TMCTS or OMCTS, an ozone-containing gas, and a source of dopants for gettering alkali elements and for lowering the reflow temperature of the dielectric while attaining the desired low-k and gap-filling properties of the dielectric film. Phosphorous is a preferred dopant for gettering alkali elements such as sodium. Additional dopants for lowering the reflow temperature include, but are not limited to boron, germanium, arsenic, fluorine or combinations thereof.

Nanoscale patterning using self-assembled polymers for semiconductor applications

Abstract: Thin films of self-organizing diblock copolymers may be suitable for semiconductor applications since they enable patterning of ordered domains with dimensions below photolithographic resolution over wafer-scale areas. We investigate the process window for forming ordered arrays of nanoscale polymer domains in thin films across 8-in.-diam silicon wafers, including the effect of substrate material and surface treatment, annealing conditions, copolymer molecular weight, and film thickness. We also demonstrate pattern transfer of the nanoporous polymer template using both reactive ion etching and metal lift off.

Semiconductor devices having protective layers thereon through which contact pads are exposed and stereolithographic methods of fabricating such semiconductor devices

Abstract: A method for forming packaged substrates, including flip-chip dice individually or in a multi-die wafer. The method includes using a stereolithographic process to form a protective dielectric polymeric sealing structure on at least the active surface of the substrate. In addition, the invention encompasses forming a similar layer on a second substrate to be joined to the first substrate. Contact pads of the second substrate are exposed through the layer thereon to facilitate joining of the two substrates. Semiconductor devices formed by the method are also disclosed.

Actively-cooled distribution plate for reducing reactive gas temperature in a plasma processing system

Abstract: A plasma processing system is provided, having processor integral cooling passages for reducing an operating temperature thereof during processing of a wafer by the system. Cooling medium inlets and outlets are connected to the cooling passages to permit circulation of a cooling medium through the cooling passages. The baffle plate comprises a generally planar, apertured, gas distribution central portion surrounded by a flange into both of which the cooling passages may extend. Further, the baffle plate may have a non-apertured plate overlying and covering apertures in a central portion of the baffle plate.

Iii-v nitride substrate boule and method of making and using the same

Abstract: A boule formed by high rate vapor phase growth of Group III-V nitride boules (ingots) on native nitride seeds (Figure 1), from which wafers may be derived for fabrication of microelectronic structures (Figure 5). The boule is of microelectronic device quality, e.g., having a transverse dimension greater than 1 centimeter, a length greater than 1 millimeter, and a top surface defect density of less than 107 defects cm-2. The Group III-V nitride boule may be formed by growing a Group III-V nitride material on a corresponding native Group III-V nitride seed crystal by vapor phase epitaxy at a growth rate above 20 micrometers per hour.

Apparatus and method for injecting and modifying gas concentration of a meta-stable or atomic species in a downstream plasma reactor

Abstract: An apparatus and method for injecting gas within a plasma reactor and tailoring the distribution of an active species generated by the remote plasma source over the substrate or wafer. The distribution may be uniform, wafer-edge concentrated, or wafer-center concentrated. A contoured plate or profiler modifies the distribution. The profiler is an axially symmetric plate, having a narrow top end and a wider bottom end, shaped to redistribute the gas flow incident upon it. The method for tailoring the distribution of the active species over the substrate includes predetermining the profiler diameter and adjusting the profiler height over the substrate. A coaxial injector tube, for the concurrent injection of activated and non-activated gas species, allows gases to be delivered in an axially symmetric manner whereby one gas can be excited in a high density RF plasma, while the other gas can be prevented from excitation and/or dissociation caused by exposure to the plasma or heated surfaces in the source apparatus. The profiler is used in conjunction with the coaxial injector tube for redistributing the excited gases emerging from the injector tube, while allowing the non-excited gases to pass through its center.

Method and device for protecting micro electromechanical systems structures during dicing of a wafer

Abstract: A wafer cap protects micro electromechanical system (“MEMS”) structures during a dicing of a MEMS wafer to produce individual MEMS dies. A MEMS wafer is prepared having a plurality of MEMS structure sites thereon. Upon the MEMS wafer, the wafer cap is mounted to produce a laminated MEMS wafer. The wafer cap is recessed in areas corresponding to locations of the MEMS structure sites on the MEMS wafer. The capped MEMS wafer can be diced into a plurality of MEMS dies without causing damage to or contaminating the MEMS die.

Thin Film Transistor of ZnO Fabricated by Chemical Solution Deposition

Abstract: A ZnO thin film was deposited on a Si wafer having an oxidized SiO2 layer using a chemical solution deposition process and was applied to a bottom-gate type thin film transistor (TFT). The films prepared by combined heating at 600° and 900°C exhibited typical enhancement-type TFT characteristics with electrons as carriers. The low heating temperature around 600°C degraded the insulating properties of the SiO2 layer but high temperature annealing recovered that.

Patterned growth of single-walled carbon nanotubes on full 4-inch wafers

Abstract: Patterned growth of single-walled carbon nanotubes (SWNTs) is achieved on full 4-in. SiO2/Si wafers. Catalytic islands with high uniformity over the entire wafer are obtained by a deep ultraviolet photolithography technique. Growth by chemical vapor deposition of methane is found to be very sensitive to the amount of H2 co-flow. Understanding of the chemistry enables the growth of high quality SWNTs from massive arrays (107–108) of well-defined surface sites. The scale up in patterned nanotube growth shall pave the way to large-scale molecular wire devices.

Annealing of high-k dielectric materials

Abstract: A method for annealing a high dielectric constant (high-k) gate dielectric layer includes placing a wafer including one or more partially formed transistors in an ambient. The ambient may include hydrogen and an oxidizing gas or the ambient may include nitrous oxide. Each transistor includes a high-k gate dielectric layer coupled to a substrate. The method further includes heating the high-k gate dielectric layer to a temperature greater than 650° C. while the gate dielectric layer is in the ambient. The ambient prevents or reduces the formation of lower dielectric constant (lower-k) material between the high-k gate dielectric layer and the substrate. Another method for annealing a high-k gate dielectric layer includes the use of an ambient including chemically active oxygen gas. When such an ambient is used, the high-k gate dielectric layer is heated to a temperature not greater than 600° C. while the gate dielectric layer is in the ambient.

System and process for heating semiconductor wafers by optimizing absorption of electromagnetic energy

Abstract: An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly linear lamps for emitting light energy onto a wafer. The linear lamps can be placed in various configurations. In accordance with the present invention, tuning devices which are used to adjust the overall irradiance distribution of the light energy sources are included in the heating device. The tuning devices can be, for instance, are lamps or lasers.

Cooling disk unit for use in a wafer chucking device

Abstract: A cooling disk unit is used in a wafer chucking device and comprises first and second heat conducting disks one of which is concentrically superposed on the other in a casing. The first heat conducting disk has a first plurality of radial channels while the second heat conducting disk has a second plurality of radial channels. The first radial channels are connected to the second radial channels at either their inside ends or their outside ends so as to flow a cooling fluid from the first (or second) radial channels to the second (or first) radial channels.

Method for forming chip scale package

Abstract: A chip scale package design for a flip chip integrated circuit includes a redistribution metal layer upon the upper surface of a semiconductor wafer for simultaneously forming solder bump pads as well as the metal redistribution traces that electrically couple such solder bump pads with the conductive bond pads of the underlying integrated circuit. A patterned passivation layer is applied over the redistribution metal layer. Relatively large, ductile solder balls are placed on the solder bump pads for mounting the chip scale package to a circuit board or other substrate without the need for an underfill material. The back side of the semiconductor wafer can be protected by a coating for mechanical strength during handling. A method of forming such a chip scale package at the wafer processing level is also disclosed.

Method of coating film, coating unit, aging unit, solvent replacement unit, and apparatus for coating film

Abstract: Prior to transfer of an wafer W, a mixed gas is being generated and exhausted, thereby fluctuation of concentration and temperature of a solvent component at the beginning of gas introduction into a chamber 3 is suppressed. A step of gelling after the wafer W is carried into an aging unit is divided into several steps. Until a temperature of the wafer W reaches a predetermined treatment temperature, an average concentration of the solvent component in a mixed gas is gradually raised relative to the temperature of the wafer W. Thereby, immediately after the wafer W is transferred into a sealed chamber, the gas of the solvent component is prevented from condensing.

Method for forming nitride spacer by using atomic layer deposition

Abstract: The present invention provides a method for forming a silicon nitride spacer by using an atomic layer deposition (ALD) method. The procedure of the ALD is to use a first kind of excess gas as a reactant air and thus produce a first mono-layer solid phase of the first reactant air on the wafer. When the first chemical reaction is completed, the first excess air is drawn out, and then the second excess air is released to deposit a second mono-layer solid phase of the second reactant air on the first mono-layer solid phase. In this way, a whole deposited layer with a layer of the first mono-layer solid phase, a layer of the second mono-layer solid phase, and so on are stepwise formed on the wafer surface. The ALD method is a time consuming task in deposition process such as in the generation of 0.35 μm to 0.5 μm of VLSI ages. However, in the generation of 0.18 μm, 0.13 μm or beyond of VLSI ages, because the device is getting smaller than ever before, the deposition speed of the ALD method is just right on time to meet the demand and is an appropriate method in depositing silicon nitride spacer.

Wafer holding, wafer support member, wafer boat and heat treatment furnace

Abstract: The present invention provides a wafer holder, a wafer support member, a wafer boat and a heat treatment furnace, which are capable of sufficiently suppressing slip dislocations, without lowering productivity and at low cost, in the high temperature heat treatment of silicon wafers, and said wafer holder is characterized in that: the wafer holder is composed of a wafer support plate and three or more wafer support members mounted on said wafer support plate, each of the wafer support members having a wafer support portion or more; at least one of said wafer support members is a tilting wafer support member which has a plurality of upward-convex wafer support portions on the upper surface and is tiltable with respect to said wafer support plate; and the wafer is supported by at least four wafer support portions.

Silicon epitaxial wafer and production method therefor

Abstract: A surface roughness distribution in the surface of a silicon epitaxial wafer is made uniform by optimizing a temperature distribution in the surface of a susceptor used in a vapor phase thin film growth apparatus. The susceptor is not supported by its center of the rear surface thereof, but only the peripheral portion thereof is supported using vertical pins respectively provided at the far ends of spokes radially branched from a rotary shaft. The susceptor is constituted so that a difference in temperature between the maximum and minimum in the surface of a silicon wafer is suppressed to a value equal to or less than 7° C. Hence, a surface roughness distribution in the surface of the silicon epitaxial wafer can be suppressed to a value equal to or less than 0.02 ppm.

Method and apparatus for treating article to be treated

Abstract: An apparatus (1) for treating a wafer, which has a heater (12), a reaction tube (2) for storing a wafer (10) having an organic material adhered thereto and, a first gas conduit (13) and a second gas conduit (14) for feeding an oxygen gas and a hydrogen gas, respectively, into the reaction tube (2); and a method for treating a wafer to be treated, which comprises feeding an oxygen gas and a hydrogen gas through the first gas conduit (13) and the second gas conduit (14), respectively, into the reaction tube (2), and heating the reaction tube (2) by the heater (12) to a temperature sufficient for activating the oxygen gas and hydrogen gas, to thereby allow a combustion reaction to take place and oxidize, decompose and remove the organic material adhered to the wafer (10).

Single-substrate-heat-processing apparatus and method for performing reformation and crystallization

Abstract: An insulating film consisting of first and second tantalum oxide layers is formed on a semiconductor wafer. First, an amorphous first layer is formed by CVD, and a reforming process for removing organic impurities contained in the first layer is carried out. Then, an amorphous second layer is formed by CVD on the first layer. Then, a reforming process for removing organic impurities contained in the second layer is carried out by supplying a process gas containing ozone into a process chamber while heating the wafer to a temperature lower than a crystallizing temperature over a certain period. Further, within the same process chamber, the wafer is successively heated to a second temperature higher than the crystallizing temperature, followed by cooling the wafer to a temperature lower than the crystallizing temperature so as to crystallize the first and second layers simultaneously.