Showing papers by "Alberto Sangiovanni-Vincentelli published in 1998"

A framework for comparing models of computation

Abstract: We give a denotational framework (a "meta model") within which certain properties of models of computation can be compared. It describes concurrent processes in general terms as sets of possible behaviors. A process is determinate if, given the constraints imposed by the inputs, there are exactly one or exactly zero behaviors. Compositions of processes are processes with behaviors in the intersection of the behaviors of the component processes. The interaction between processes is through signals, which are collections of events. Each event is a value-tag pair, where the tags can come from a partially ordered or totally ordered set. Timed models are where the set of tags is totally ordered. Synchronous events share the same tag, and synchronous signals contain events with the same set of tags. Synchronous processes have only synchronous signals as behaviors. Strict causality (in timed tag systems) and continuity (in untimed tag systems) ensure determinacy under certain technical conditions. The framework is used to compare certain essential features of various models of computation, including Kahn process networks, dataflow, sequential processes, concurrent sequential processes with rendezvous, Petri nets, and discrete-event systems.

Automatic synthesis of interfaces between incompatible protocols

Abstract: A t the system level, reusable Intellectual Property (or IP) blo cks can be represented abstractly as blocks that exchange messages. The concrete implementations of these IP blocks m ust exc hange the messages through complex signaling protocols. Interfacing bet ween IP that use different signaling protocols is a tedious and error prone design task. We propose using regular expression based protocol descriptions to sho w ho w to map the message on to a signaling protocol. Given t w o protocols,an algorithm is proposed to build an interface machine. We ha ve implemented our algorithm in a program named PIG that synthesizes a Verilog implementation based on a regular expression protocol description.

Scheduling for embedded real-time systems

Abstract: The authors review several approaches to control-oriented and dataflow-oriented software scheduling to determine whether a given technique can satisfy deadlines, throughput, and other constraints for embedded real-time systems.

Software timing analysis using HW/SW cosimulation and instruction set simulator

Abstract: Timing analysis for checking satisfaction of constraints is a crucial problem in real-time system design. In some current approaches, the delay of software modules is precalculated by a software performance estimation method, which is not accurate enough for hard real-time systems and complicated designs. In this paper we present an approach to integrate a clock-cycle-accurate instruction set simulator (ISS) with a fast event-based system simulator. By using the ISS, the delay of events can be measured instead of estimated. An interprocess communication architecture and a simple protocol are designed to meet the requirement of robustness and flexibility. A cached refinement scheme is presented to improve the performance at the expense of accuracy. The scheme is especially effective for applications in which the delay of basic blocks is approximately data-independent. We also discuss the implementation issues by using the Ptolemy simulation environment and the ST20 simulator as an example.

Wireplanning in logic synthesis

Abstract: In this paper, we propose a new logic synthesis methodology to deal with the increasing importance of the interconnect delay in deep submicron technologies. We first show that conventional logic synthesis techniques can produce circuits which will have long paths even if placed optimally. Then, we characterize the conditions under which this can happen and propose logic synthesis techniques which produce circuits which are "better" for placement. Our proposed approach still separates logic synthesis from physical design.

A case study on modeling shared memory access effects during performance analysis of HW/SW systems

Abstract: Behavioral simulation with timing annotations derived from performance modeling and analysis is a promising alternative for use in evaluating system-level design trade-offs. The accuracy of such approaches is determined by how well the effects of various HW and SW architectural features, like the Real Time Operating System (RTOS), shared memories and buses, HW/SW communication mechanisms, etc are modeled at this level. We present a study of the effects of shared memory buses during system-level performance analysis in the POLIS co-design environment using the example of a TCP/IP Network Interface System. We demonstrate how the effects of the memory arbiter and shared memory bus can be modeled efficiently at the behavioral level, and used to evaluate various design tradeoffs. Experimental results demonstrate that modeling these effects can significantly increase the accuracy of system-level performance estimates.

Hybrid Control for Automotive Engine Management: The Cut-Off Case

Abstract: A novel approach to the control of an automotive engine in the cut-off region is presented. First, a hybrid model which describes the torque generation mechanism and the power-train dynamics is developed. Then, the cut-off control problem is formulated as a hybrid optimization problem, whose solution is obtained by relaxing it to the continuous domain and mapping its solution back into the hybrid domain. A formal analysis as well as simulation results demonstrate the properties and the quality of the control law.

Exact minimization of binary decision diagrams using implicit techniques

Abstract: This paper addresses the problem of binary decision diagram (BDD) minimization in the presence of don't care sets. Specifically given an incompletely specified function g and a fixed ordering of the variables, we propose an exact algorithm for selecting f such that f is a cover for g and the binary decision diagram for f is of minimum size. The approach described is the only known exact algorithm for this problem not based on the enumeration of the assignments to the points in the don't care set. We show also that our problem is NP-complete. We show that the BDD minimization problem can be formulated as a binate covering problem and solved using implicit enumeration techniques. In particular, we show that the minimum-sized binary decision diagram compatible with the specification can be found by solving a problem that is very similar to the problem of reducing incompletely specified finite state machines. We report experiments of an implicit implementation of our algorithm, by means of which a class of interesting examples was solved exactly. We compare it with existing heuristic algorithms to measure the quality of the latter.

A case study in embedded system design: an engine control unit

Abstract: A number of techniques and software tools for embedded system design have been recently proposed. However, the current practice in the designer community is heavily based on manual techniques and on past experience rather than on a rigorous approach to design. To advance the state of the art it is important to address a number of relevant design problems and solve them to demonstrate the power of the new approaches. We chose an industrial example in automotive electronics to validate our design methodology: an existing commercially available Engine Control Unit. We discuss in detail the specification, the implementation philosophy, and the architectural trade-off analysis. We analyze the results obtained with our approach and compare them with the existing design underlining the advantages offered by a systematic approach to embedded system design in terms of performance and design time.

Modeling reactive systems in Java

Abstract: We present an application of the Java/sup TM/ programming language to specify and implement reactive real-time systems. We have developed and tested a collection of classes and methods to describe concurrent modules and their asynchronous communication by means of signals. The control structures are closely patterned after those of the synchronous language Esterel, succinctly describing concurrency, sequencing and preemption. We show the user-friendliness and efficiency of the proposed technique by using an example from the automotive domain.

Intellectual property re-use in embedded system co-design: an industrial case study

Abstract: Design of large systems on a chip would be infeasible without the capability to flexibly adapt the system architecture to the application and the re-use of existing Intellectual Property (IP). This in turn requires the use of an appropriate methodology for system specification, architecture selection, IP integration and implementation generation. The goals of this work are: a) verification of the effectiveness of the POLIS HW/SW co-design methodology for the design of embedded systems for telecom applications; b) definition of methodology for integrating system level IP libraries in this HW/SW co-design framework. Methodology evaluations have been carried out through the development of an industrial telecom system design, an ATM node server.

Rapid-Prototyping of Embedded Systems via Reprogrammable Devices

Abstract: This paper describes a flexible board-level rapid-prototyping environment for embedded control applications. The environment is based on an APTIX board populated by Xilinx FPGA devices, a 68HC11 emulator, and APTIX programmable interconnect devices. Given a design consisting of logic and of software running on a micro-controller that implement a set of tasks, the prototype is obtained by programming the FPGA devices, the micro-controller emulator and the APTIX devices. This environment being based on programmable devices offers the flexibility to perform engineering changes, the performance needed to validate complex systems and the hardware setup for field tests. The key point in our approach is the use of results of our previous research on software and hardware synthesis as well as of some commercial tools to provide the designer with fast programming data from a high-level description of the algorithms to be implemented. We demonstrate the effectiveness of the approach by showing a close-to real-life example from the automotive world.

Formal verification of an automotive engine controller in cutoff mode

Abstract: We describe formal verification of convergence and performance properties of an engine control algorithm being developed for Magneti-Marelli. We study the cutoff mode, where the driver releases the accelerator and the controller regulates fuel injection to minimize the oscillations while decelerating. The engine and its controller are modeled with hybrid automata and the sliding action of the hybrid controller is formally verified with the model checker HYTECH.

Hybrid systems and the design of embedded controllers for automotive engine management

Abstract: The problem of designing an automotive engine control unit for the next-generation automobiles has been formulated as a hybrid control problem. We present first the overall methodology and its basic components. Then we focus on the highest levels of abstraction that involve the formulation of the control problem and its solution. Two particular control sub-problems (cut-off and fast positive force tracking) are formulated as hybrid optimal control problems. A formal analysis as well as experimental results demonstrate the properties and the quality of the control laws.

A hybrid approach to the fast positive force transient tracking problem in automotive engine control

Abstract: The engine control problem can be decomposed into a set of sub-problems corresponding to regions of operation identified by the settings of the control devices available to the driver (e.g., accelerator pedal angle, selected gear). One of these regions is the so called fast positive force transient, where a quick acceleration is requested, maintaining certain comfort standards. In this paper, this control problem is formulated as a hybrid control problem and solved by approximation of an auxiliary continuous control problem. The quality of the results is backed by a set of simulations on a commercial car model.

A Timed Automaton-Based Method for Accurate Computation of Circuit Delay in the Presence of Cross-Talk

Abstract: We present a timed automaton-based method for accurate computation of the delays of combinational circuits. In our method, circuits are represented as networks of timed automata, one per circuit element. The state space of the network represents the evolution of the circuit over time and delay is computed by performing a symbolic traversal of this state space.

System-level design models and implementation techniques

Abstract: Electronic systems need to accommodate rapidly changing product specifications and to reduce design costs together with design turn-around time. To be able to reuse part of previous designs and to be able to include new functionality rapidly, system designers tend to use microcontrollers and digital signal processors (DSPs) as much as possible. For performance reasons they may be forced to design special purpose hardware, but even then there is a strong motivation toward the reuse of parts already designed. This trend will change the industrial landscape and will make the trade and assembly of intellectual properties (IPs) embodied in layouts, RTL designs, and software programs indispensable. We believe that system design should be based on the use of one or more formal models to describe the behavior of the system at a high level of abstraction, before a decision on its decomposition into hardware and software components is taken. Design should then be based on a sequence consisting of the initial functional design (i.e. specifying what the system is intended to do) and its analysis, the mapping of such functional description, into an architecture, and the consequent performance evaluation. The final implementation of the system should be made using automatic synthesis as much as possible from this high level of abstraction, to ensure implementations that are "correct by construction". Validation (through simulation or verification) should be done at the highest possible levels of abstraction.

Theory and algorithms for face hypercube embedding

Abstract: We present a new matrix formulation of the face hypercube embedding problem that motivates the design of an efficient search strategy to find an encoding that satisfies all faces of minimum length. Increasing dimensions of the Boolean space are explored; for a given dimension constraints are satisfied one at a time. The following features help to reduce the nodes of the solution space that must be explored: candidate cubes instead of candidate codes are generated, cubes yielding symmetric solutions are not generated, a smaller sufficient set of solutions (producing basic sections) is explored, necessary conditions help discard unsuitable candidate cubes, early detection that a partial solution cannot be extended to be a global solution prunes infeasible portions of the search tree. We have implemented a prototype package minimum input satisfaction kernel (MINSK) based on the previous ideas and run experiments to evaluate it. The experiments show that MINSK is faster and solves more problems than any available algorithm. Moreover, MINSK is a robust algorithm, while most of the proposed alternatives are not. Besides most problems of the complete Microelectronics Center of North Carolina (MCNC) benchmark suite, other solved examples include an important set of decoder programmable logic arrays (PLA's) coming from the design of microprocessor instruction sets.

Time-Domain Non-Monte Carlo Noise Simulation

Abstract: The time domain non-Monte Carlo (meaning that no random number generators are used) noise analysis technique we proposed [2, 3] is not restricted to circuits with a time-invariant or (quasi-) periodic steady-state with WSS or cyclostationary noise sources. The deterministic excitations on the circuit can be arbitrary time domain signals, including transient waveforms without a steady-state characteristics. As a result, the noise sources in the circuit will be nonstationary in general as opposed to being WSS or cyclostationary. All the circuit variables, i.e. node voltages, will also be nonstationary stochastic processes in general. A complete second-order probabilistic characterization would then require the calculation of the autocorrelation, cross-correlation matrix of the component of the state vector due to noise, which is given by $$ R\left( {t,\tau } \right) = E\left[ {X\left( {t + \tau /2} \right)X\left( {t - \tau /2} \right)^T } \right] $$ (5.1) or the time-varying spectral, cross-spectral density matrix $$ S_X \left( {t,f} \right) = F\left\{ {R\left( {t,\tau } \right)} \right\}. $$ (5.2)

Injector characteristics estimation for spark ignition engines

Abstract: Injector characteristics estimation is an essential ingredient for an effective automotive engine control system. An accurate estimation algorithm is presented in the paper. Simulation and experimental results are provided to demonstrate the quality of the algorithm.

Bdd partitioning for formal verification and synthesis of digital systems

Abstract: Reduced Ordered Binary Decision Diagrams (ROBDDs) are extensively used in various VLSI-CAD algorithms as a representation for Boolean functions. However, the complexity of the problems that can be solved using these algorithms is usually limited by the fact that the ROBDDs of many functions can require space which is exponential in the number of variables. This large space requirement of ROBDDs is commonly known as the "memory explosion" problem. This dissertation addresses the ROBDD memory explosion problem in the context of digital system verification and synthesis. BDD partitioning is proposed as an effective way of dealing with this problem. The first part of the dissertation focuses on formal verification of digital systems. A new representation for Boolean functions called partitioned-ROBDDs is proposed. In this representation the Boolean space is divided into 'k' partitions and the function is represented as a separate ROBDD over each partition. It is shown that partitioned-ROBDDs are canonical and efficiently manipulable. In addition, for many functions they are exponentially more compact than ROBDDs. Moreover, different partitions can be processed independently and only one partition needs to be present in the memory at any given time which further increases the space efficiency. In addition to the theoretical discussion of the properties of partitioned-ROBDDs, their utility in formal verification of combinational and sequential circuits is demonstrated by means of experiments. Since ROBDDs and partitioned-ROBDDs are canonical representations of Boolean functions, they can be directly used to check the equivalence of two combinational circuits. A mixed bottom-up/top-down procedure for memory efficient construction of ROBDDs is proposed. This procedure aims at reducing the intermediate memory requirement by first introducing suitable decomposition points and then finding a good order of composition to obtain the ROBDD representation of the outputs of a Boolean netlist. Automatic techniques to construct partitioned-ROBDDs representing the outputs of combinational circuits and the set of reachable states of sequential circuits are also presented. In both cases, partitioned-ROBDDs show a substantial reduction in total memory utilization over ROBDDs. In the case of combinational verification, partitioned-ROBDDs are able to verify many circuits for which ROBDDs fail. These include some complex industrial circuits which could be verified for the first time using these techniques. Similarly, in the case of sequential circuits, for a given memory limit, partitioned-ROBDDs can complete traversal for many circuits for which ROBDDs fail. For circuits where both partitioned-ROBDDs as well as monolithic ROBDDs cannot complete traversal, partitioned-ROBDDs can reach a significantly larger set of states. The second part of the dissertation focuses on logic synthesis. A new application of ROBDDs, in the synthesis of pass-transistor circuits, is proposed and the ROBDD memory explosion problem is studied in this context. It is shown that Pass-transistor logic (PTL) can be a promising alternative to static CMOS for deep sub-micron designs. A comprehensive synthesis flow for PTL designs is outlined which utilizes the fact that ROBDDs can be directly mapped into PTL circuits. Decomposed-ROBDDs are proposed as a suitable logic level representation for multi-stage PTL circuits. Although not canonical, decomposed-ROBDDs do not suffer from the memory explosion problem associated with monolithic ROBDDs. A set of algorithms to synthesize PTL circuits optimized for area, delay and power using this representation are proposed.

An exact input encoding algorithm for BDDs representing FSMs

Abstract: We address the problem of encoding the state variables of a finite state machine such that the BDD representing its characteristic function has the minimum number of nodes. We present an exact formulation of the problem. Our formulation characterizes the two BDD reduction rules by deriving conditions under which these reduction rules can be applied. We then provide an algorithm that finds these conditions and solves the problem by formulating it as a 2-CNF formula and extracting all its prime implicants. In addition to this, we implemented a simulated annealing algorithm for this problem and provide a thorough experiment of the impact of encoding on a BDD representing an FSM with different orderings.

Noise in Free Running Oscillators

Abstract: Oscillators are among the key components of many different kinds of electronic systems. They are used for on-chip clock generation for microprocessors. Every communications receiver/transmitter has at least one oscillator that is used in the frequency synthesis of an oscillation signal which up or down converts the incoming/outgoing signal. Oscillators have one property that makes them quite unique from several aspects: They are autonomous systems. They generate an oscillatory signal at their output without an input (apart from a power supply input, and a control signal that sets the frequency), as opposed to amplifiers and mixers which generate an output when they are being driven with some input signals. The design, analysis and simulation of oscillators often require techniques which are specific for autonomous systems.

Performance estimation of data-flow applications for IP-based system design

Abstract: This paper addresses the problem of performance estimation for data-flow algorithms, and proposes a novel approach suitable in IP-based design methodology It assumes that an algorithm is defined as a set of interacting blocks, where each block is associated with implementations for target processors, and the delay for each implementation has been already measured and is characterized by a delay equation The estimation is performed using delay equations, rather than considering detailed implementations of the blocks This assumption matches well with the trend of system design, in which the system behavior is specified by using already characterized components The estimation procedure takes into account decisions made carefully at compile time, such as inter-block scheduling and static memory allocation This estimation technique is very fast and accurate, in particular for algorithms with small run-time dependencies such as those in data-flow applications The procedure has been implemented, and preliminary experimental results are presented for single DSP architectures to demonstrate its effectiveness