An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Considerations for Ultimate CMOS Scaling

This survey deals with 1/f noise in homogeneous semiconductor samples. A distinction is made between mobility noise and number noise. It is shown that there always is mobility noise with an /spl alpha/ value with a magnitude in the order of 10/sup -4/. Damaging the crystal has a strong influence on /spl alpha/, /spl alpha/ may increase by orders of magnitude. Some theoretical models are briefly discussed none of them can explain all experimental results. The /spl alpha/ values of several semiconductors are given. These values can be used in calculations of 1/f noise in devices. >

1/f Noise Sources

The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current becomes too large. This led to the replacement of SiO2 by a physically thicker layer of a higher dielectric constant or ‘high-K’ oxide such as hafnium oxide. Intensive research was carried out to develop these oxides into high quality electronic materials. In addition, the incorporation of Ge in the CMOS transistor structure has been employed to enable higher carrier mobility and performance. This review covers both scientific and technological issues related to the high-K gate stack – the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging to achieve the thinnest oxide thicknesses. The high K oxides were implemented in conjunction with a replacement of polycrystalline Si gate electrodes with metal gates. The strong metallurgical interactions between the gate electrodes and the HfO2 which resulted an unstable gate threshold voltage resulted in the use of the lower temperature ‘gate last’ process flow, in addition to the standard ‘gate first’ approach. Work function control by metal gate electrodes and by oxide dipole layers is discussed. The problems associated with high K oxides on Ge channels are also discussed.

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High-K materials and metal gates for CMOS applications

https://www.iue.tuwien.ac.at/pdf/ib_2011/JB2011_Grasser_5.pdf

Stochastic charge trapping in oxides: From random telegraph noise to bias temperature instabilities

3D Backside Integration of FinFETs: Is There an Impact on LF Noise?

/pdf/heterogeneous-nano-electronic-devices-enabled-by-monolithic-4tr62kzsav.pdf

Heterogeneous Nano-electronic Devices Enabled by Monolithic Integration of IIIV, Ge, and Si to expand future CMOS functionality

This work presents an experimental analysis of the trade-off between transistor efficiency (gm/I D ) and unit gain frequency (f T ) of nanosheet field effect transistors (NSFETs) with different metal gate (MG) stack, considering the influence of high temperature (T), until T=200 °C. The results are very promising for both MG stacks. The MG stack (n*) presents a high f T about 260 GHz (T=25 °C and L=28 nm) and a gm/I D about 37 V-1 (T=25 °C and L=200 nm). The MG stack (m*) also presents very good characteristics, like a f T about 252 GHz (T=25 °C and L=28 nm) and a gm/I D about 35 V-1 (T=25 °C and L=200 nm). From the analyses as a function of the inversion coefficient (IC), it was possible to determine that the optimal operation point occurs in the transition from moderate to strong inversion for L=28 nm and it is in strong inversion for long channel devices. In all cases, although the intrinsic voltage gain (A V ) is degraded moving away from weak inversion, the degradation was not very pronounced up to the optimal operation point and considering the temperature variation, the A V presents a greater stability at the optimal point than in weak inversion.

High Temperature Influence on the Trade-off between gm/I D and f T of nanosheet NMOS Transistors with Different Metal Gate Stack

In this work, an in-depth static and low frequency noise characterization of nanosheet FETs, consisting of two vertically stacked silicon channels per device, is performed. A comparison of the performances from n- versus p-channel FETs operated at 300 K and 78 K, in terms of static and low frequency noise parameters variability, is also discussed. The main electrical parameters are estimated from the I-V characteristics using access resistance robust methodologies. An additional criterion demonstrating that the extracted parameters are not influenced by the second mobility attenuation factor is proposed. The low frequency noise studies prove that the dominant flicker noise mechanism is linked to correlated carrier number and mobility fluctuations, with additional access resistances noise contribution in very strong inversion. The importance of the considered total flicker noise model on the estimation of the Coulomb scattering coefficient is highlighted.

(Invited) In-Depth DC and Low Frequency Noise Characterization of Nanosheet FETs at Room and Cryogenic Temperatures

We report on vertically stacked nanosheet (NS) FETs, focusing on the combined inner spacers and source/drain (S/D) epitaxial growth modules sequence, a key integration flow differentiator as compared to finFETs, addressing the impact and control of parasitics and channel strain engineering. The use of both wafer sides for device connection, via nTSVs landing on buried power rails (BPR) after extreme wafer thinning, is also discussed. This configuration is shown to be advantageous for obtaining reduced IR drop values and for, overall, enabling enhanced performance and additional area scaling. It also has the potential to further expand such as to include extra options, together with novel devices/circuits and for various applications.

Anabela Veloso

Papers

3D Backside Integration of FinFETs: Is There an Impact on LF Noise?

Heterogeneous Nano-electronic Devices Enabled by Monolithic Integration of IIIV, Ge, and Si to expand future CMOS functionality

High Temperature Influence on the Trade-off between gm/I D and f T of nanosheet NMOS Transistors with Different Metal Gate Stack

(Invited) In-Depth DC and Low Frequency Noise Characterization of Nanosheet FETs at Room and Cryogenic Temperatures

Innovations in Transistor Architecture and Device Connectivity for Advanced Logic Scaling