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Anabela Veloso
Researcher at Katholieke Universiteit Leuven
Publications - 190
Citations - 2175
Anabela Veloso is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: CMOS & Metal gate. The author has an hindex of 22, co-authored 164 publications receiving 1794 citations.
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Proceedings ArticleDOI
Low Power CMOS Featuring Dual Work Function FUSI on HfSiON and 17ps Inverter Delay
T. Y. Hoffmann,Anabela Veloso,Anne Lauwers,Hao Yu,M.J.H. van Dal,Howard L. Tigelaar,T. Chiarella,Christoph Kerner,R. Mitsuhashi,I. Satoru,M. Niwa,Aude Rothschild,Benoit Froment,J. Ramos,Axel Nackaerts,Stephan Brus,Christa Vrancken,Philippe Absil,M. Jurczak,Jorge A. Kittl,S. Biesemans +20 more
TL;DR: In this article, Lauwers et al. reported record unloaded ring oscillator delay (17ps at VDD = 1.1V and 20pA/mum Ioff) using low power CMOS transistors with Ni-based fully silicided (FUSI) gates on HfSiON.
Proceedings ArticleDOI
Middle-of-line plasma dry etch challenges for buried power rail integration
Dunja Radisic,Anabela Veloso,A. Gupta,Maryamsadat Hosseini,S. Wang,V. Mertens,Bt Chan,Dmitry Batuk,G. T. Martinez,Frederic Lazzarino,Eugenio Dentoni Litta,Naoto Horiguchi +11 more
TL;DR: In this paper , the authors focused on plasma dry etch development of high aspect ratio Via contact to BPR metal (VBPR) and Trench contact etch (M0A) to the source/drain (S/D) device region.
Proceedings ArticleDOI
Discussion on the 1/f noise behavior in Si gate-all-around nanowire MOSFETs at liquid helium temperatures
TL;DR: In this paper, gate-all-around nanowire MOSFETs are studied at very low temperature (4.2 K) and drain voltage, and the 1/f noise level is investigated in order to study the impact of quantum transport on the noise mechanism.
Proceedings ArticleDOI
Addressing Key Concerns for Implementation of Ni FUSI into Manufacturing for 45/32 nm CMOS
A. Shickova,Thomas Kauerauf,Aude Rothschild,Marc Aoulaiche,S. Sahhaf,Ben Kaczer,Anabela Veloso,C. Torregiani,Luigi Pantisano,Anne Lauwers,Mohammed Zahid,T. Rost,H. Tigelaar,M. Pas,J. Fretwell,J. McCormack,T. Hoffmann,C. Kemer,Thomas Chiarella,S. Bras,Yoshinao Harada,M. Niwa,Vidya Kaushik,Herman Maes,Philippe Absil,Guido Groeseneken,Serge Biesemans,Jorge A. Kittl +27 more
TL;DR: In this article, the authors studied NiSi, Ni2Si and Ni31Si12 FUSI gates and their showing 1) Excellent reliability (NBTI, PBTI and TDDB) on HfSiON (EOT=1.1nm), with lifetimes > 10 years at 1.2 V for optimized Hf siON (BTI similar/improved compared to reference MG, strong effect of N (DPN Hf SiON) finding optimal point in NMOS-PMOS BTI trade-off).
Refined DC and Low-Frequency Noise Characterization at Room and Cryogenic Temperatures of Vertically Stacked Silicon Nanosheet FETs
TL;DR: In this paper , two types of gate-all-around (GAA) vertically stacked silicon nanosheet (NS) FETs are investigated, the main difference being the vertical distance between the stacked NSs.