Anabela Veloso

TL;DR: In this article, the authors show that adding a Dy 2 O 3 capping layer on the host dielectric has no significant impact on T inv (<1 A), while up to ∼5 and 2 A reduction occurs for SiON and HfSiON Yb-implanted devices, respectively.

TL;DR: In this paper, the authors study vfTLP characteristics of gate-all-around (GAA) ESD devices and provide an in-depth understanding on physical failure mechanism of GAA devices during CDM ESD events.

TL;DR: In this article, a new quantum mechanical model for the calculation of leakage currents is proposed, which incorporates both variational calculus and the transfer matrix method to compute the subband energies and the life times of the inversion layer states.

TL;DR: In this article , an active backside (BS) technology with BS contacts is proposed to bring new opportunities to the primary reliability challenges of ESD and LU, and the measured and simulated results indicate the benefits for ESD robustness by enhancing the current uniformity and LU immunity by reducing the parasitic bipolar β of ~50%.

TL;DR: In this paper, a sub-monolayer HfSiON cap was applied on the SiON host dielectrics in the phase-controlled Ni-FUSI CMOS devices.