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Anabela Veloso
Researcher at Katholieke Universiteit Leuven
Publications - 190
Citations - 2175
Anabela Veloso is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: CMOS & Metal gate. The author has an hindex of 22, co-authored 164 publications receiving 1794 citations.
Papers
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Journal ArticleDOI
Low-Frequency Noise Assessment of the Oxide Quality of Gate-Last High- $k$ pMOSFETs
TL;DR: In this paper, the impact of wet versus dry dummy dielectric removal approaches on replacement metal gate (RMG high-k last) pMOSFETs, with aggressively scaled high- k gate dielectrics, has been studied by low-frequency noise.
Patent
Method for gate electrode height control
TL;DR: In this paper, a method of controlling the gate electrode in a silicidation process is proposed, which consists of applying a sacrificial cap layer on top of each gate electrode, each of the at least one gate electrode deposited with a given height on a semiconductor substrate.
Proceedings Article
Highly scalable effective work function engineering approach for multi-V T modulation of planar and FinFET-based RMG high-k last devices for (Sub-)22nm nodes
Anabela Veloso,Guillaume Boccardi,L.-A. Ragnarsson,Higuchi Yuichi,Jae Woo Lee,Eddy Simoen,Ph. J. Roussel,Moon Ju Cho,S. A. Chew,Tom Schram,H. Dekkers,A. Van Ammel,Thomas Witters,Stephan Brus,A. Dangol,Vasile Paraschiv,E. Vecchio,X. Shi,Farid Sebaai,Kristof Kellens,Nancy Heylen,Katia Devriendt,O. Richard,Hugo Bender,Thomas Chiarella,Hiroaki Arimura,Aaron Thean,Naoto Horiguchi +27 more
TL;DR: A novel EWF engineering approach enabling wide VT modulation in aggressively scaled RMG-HKL planar and multi-gate FinFET-based devices with high aspect-ratio gate trenches is reported on.
Journal ArticleDOI
Experimental Evaluation of Self-Heating and Analog/RF FOM in GAA-Nanowire FETs
TL;DR: The characterization and modeling of multi-finger gate all around (GAA) nanowire (NW) FETs (NWFETs) from dc to 14 GHz shows a good correlation with the measurement data and the self-heating effect (SHE) is significant in short-channel silicon on insulator (SOI) NWFets.
Proceedings ArticleDOI
Low V t Ni-FUSI CMOS Technology using a DyO cap layer with either single or dual Ni-phases
Hui Yu,Shou-Zen Chang,Anabela Veloso,Anne Lauwers,Christoph Adelmann,B. Onsia,S. Van Elshocht,R. Singanamalla,Marc Demand,Rita Vos,Thomas Kauerauf,Stephan Brus,X. Shi,Stefan Kubicek,Christa Vrancken,R. Mitsuhashi,P. Lehnen,Jorge A. Kittl,M. Niwa,K.M. Yin,T. Y. Hoffmann,S. DeGendt,Malgorzata Jurczak,Philippe Absil,Serge Biesemans +24 more
TL;DR: In this article, an ultra-thin dysprosium oxide (DyO) cap layer (5 Aring) was proposed to lower the NiSi FUSI nFET Vt by 300 mV/500 mV on HfSiON/SiON and achieved a Vt,lin of 0.25 V/0.18 V respectively.