An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Considerations for Ultimate CMOS Scaling

This survey deals with 1/f noise in homogeneous semiconductor samples. A distinction is made between mobility noise and number noise. It is shown that there always is mobility noise with an /spl alpha/ value with a magnitude in the order of 10/sup -4/. Damaging the crystal has a strong influence on /spl alpha/, /spl alpha/ may increase by orders of magnitude. Some theoretical models are briefly discussed none of them can explain all experimental results. The /spl alpha/ values of several semiconductors are given. These values can be used in calculations of 1/f noise in devices. >

1/f Noise Sources

The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current becomes too large. This led to the replacement of SiO2 by a physically thicker layer of a higher dielectric constant or ‘high-K’ oxide such as hafnium oxide. Intensive research was carried out to develop these oxides into high quality electronic materials. In addition, the incorporation of Ge in the CMOS transistor structure has been employed to enable higher carrier mobility and performance. This review covers both scientific and technological issues related to the high-K gate stack – the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging to achieve the thinnest oxide thicknesses. The high K oxides were implemented in conjunction with a replacement of polycrystalline Si gate electrodes with metal gates. The strong metallurgical interactions between the gate electrodes and the HfO2 which resulted an unstable gate threshold voltage resulted in the use of the lower temperature ‘gate last’ process flow, in addition to the standard ‘gate first’ approach. Work function control by metal gate electrodes and by oxide dipole layers is discussed. The problems associated with high K oxides on Ge channels are also discussed.

/pdf/high-k-materials-and-metal-gates-for-cmos-applications-4hs77i3c4a.pdf

High-K materials and metal gates for CMOS applications

https://www.iue.tuwien.ac.at/pdf/ib_2011/JB2011_Grasser_5.pdf

Stochastic charge trapping in oxides: From random telegraph noise to bias temperature instabilities

In this work, we comprehensively evaluate the impact of using backside power delivery network (BSPDN) for CPU of 2D and 3D designs at A14 node from the aspects of power, performance, area and thermal (PPAT) compared to identical designs of conventional front-side (FS) PDN. 2D BSPDN power consumption is 57% smaller than that of 2D FSPDN at iso-CPU frequency. 3D CPU-on-CPU PDN power consumption shows ~3.8 totally (or ~1.9/CPU) times the 2D FSPDN counterpart. Ring oscillator evaluation shows that logic gates in the IR-drop hotspot region of CPU has worst performance loss <9% and >16% for BSPDN and FSPDN based CPUs respectively while the 3D top CPU can suffer from 25% performance loss. BSPDN based CPU area can be scaled down by 8% compared with the FSPDN counterpart with similar power and performance after physical design and PPA evaluation. Due to the thinning of substrate thickness and the BSPDN process, BSPDN based CPU local temperature can be ~40% more than the FSPDN counterpart, illustrating the importance of considering the heat dissipation for the chips with BSPDN. For the CPU-on-CPU 3D IC with power source/package on the bottom and cooler on the top, the top CPU die has 39% more IR drop than the bottom one while the later has 17% more temperature than the former. This opposite trend may induce additional challenge of power integrity and thermal reliability co-design and optimization for 3D ICs with BSPDN.

Power, Performance, Area and Thermal Analysis of 2D and 3D ICs at A14 Node Designed with Back-side Power Delivery Network

A wafer-scaled III-V vertical FET fabrication by means of plasma etching

Advanced semiconductor devices for future CMOS technologies

In this work the gate-all-around nanosheet transistor is analyzed at high temperatures, from analog point of view. At first, the gate-all-around nanosheet (NS) behavior is compared with reported omega-gate nanowire (NW) transistors, at room temperature. It is worth noting that the nanosheets devices present a stronger electrostatic coupling between gate and channel (lower short channel effect -SCE), and higher intrinsic voltage gain, AV (better Early voltage) when compared with NW devices (60 dB for NS and 55 db for NW, with L = 200 nm). Therefore, the second part of this work focuses on the analog study only for NS transistors (with different metal gate stacks), presenting the trade-off between transistor efficiency and unit gain frequency, fT from room temperature to 200 °C. The obtained results are very promising for both gate stack transistors, where values of transistor efficiency about 37 V−1 (T = 25 °C and L = 200 nm) and fT about 260 GHz (T = 25 °C and L = 28 nm) are obtained. The optimal application point was obtained at the transition from moderate to strong inversion. 

Trade-off Analysis between gm/ID and fT of nanosheet NMOS Transistors with Different Metal Gate Stack at High Temperature

Low frequency noise characterization is used to compare the quality and reliability of gate dielectric processed using both gate-first and gate-last or replacement metal gate integration schemes. The influence of different processing treatments will be studied, for both planar and FinFET devices, and the obtained results compared with the LF noise specifications of the International Technology Roadmap for Semiconductors (ITRS).

Anabela Veloso

Papers

Power, Performance, Area and Thermal Analysis of 2D and 3D ICs at A14 Node Designed with Back-side Power Delivery Network

A wafer-scaled III-V vertical FET fabrication by means of plasma etching

Advanced semiconductor devices for future CMOS technologies

Trade-off Analysis between gm/ID and fT of nanosheet NMOS Transistors with Different Metal Gate Stack at High Temperature

Low frequency noise performance of gate-first and replacement metal gate CMOS technologies