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Anabela Veloso
Researcher at Katholieke Universiteit Leuven
Publications - 190
Citations - 2175
Anabela Veloso is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: CMOS & Metal gate. The author has an hindex of 22, co-authored 164 publications receiving 1794 citations.
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Proceedings ArticleDOI
On the efficiency of stress techniques in gate-last N-type bulk FinFETs
Geert Eneman,Nadine Collaert,Anabela Veloso,An De Keersgieter,Kristin De Meyer,Thomas Hoffmann +5 more
TL;DR: In this article, a TCAD study on the effectiveness of stress techniques on bulk FinFET and planar nFETs is presented, comparing gate-first to gate-last schemes.
Journal ArticleDOI
Stress Techniques and Mobility Enhancement in FinFET Architectures
Geert Eneman,Liesbeth Witters,Jerome Mitard,Geert Hellings,An De Keersgieter,David P. Brunco,Andriy Hikavyy,Benjamin Vincent,Eddy Simoen,Paola Favia,Hugo Bender,Anabela Veloso,Thomas Chiarella,Guillaume Boccardi,Minsoo Kim,M. Togo,Roger Loo,Kristin De Meyer,Naoto Horiguchi,Nadine Collaert,Aaron Thean +20 more
TL;DR: To make the switch from planar to fin architectures, numerous process challenges need to be overcome, such as the need for adapted gate/spacer modules that maintain good performance and process control in these hightopography structures.
Proceedings ArticleDOI
High performance Si .45 Ge .55 Implant Free Quantum Well FET featuring low temperature process, eSiGe stressor and transversal strain relaxation
S. Yamaguchi,Liesbeth Witters,Jerome Mitard,Geert Eneman,Geert Hellings,M. Fukuda,Andriy Hikavyy,Roger Loo,Anabela Veloso,Y. Crabbe,E. Rohr,Paola Favia,Hugo Bender,S. Takeoka,Georgios Vellianitis,Wei-E Wang,L.-A. Ragnarsson,K. De Meyer,An Steegen,Naoto Horiguchi +19 more
TL;DR: In this work, high performance Si.45Ge.55 Implant Free Quantum Well pFET with high drive current with embedded SiGe (eSiGe) stressor which is fully compatible with SiGe channel is reported.
Proceedings ArticleDOI
Strain enhanced low-V T CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay
Stefan Kubicek,Tom Schram,E. Rohr,Vasile Paraschiv,Rita Vos,Marc Demand,Christoph Adelmann,Thomas Witters,Laura Nyns,Annelies Delabie,L.-A. Ragnarsson,Thomas Chiarella,Christoph Kerner,Abdelkarim Mercha,Bertrand Parvais,Marc Aoulaiche,C. Ortolland,Hao Yu,Anabela Veloso,Liesbeth Witters,R. Singanamalla,Thomas Kauerauf,Stephan Brus,Christa Vrancken,V.S. Chang,S.Z. Chang,R. Mitsuhashi,Y. Okuno,A. Akheyar,H.-J. Cho,J.C. Hooker,Barry O'Sullivan,S. Van Elshocht,K. De Meyer,Malgorzata Jurczak,Philippe Absil,Serge Biesemans,T. Y. Hoffmann +37 more
TL;DR: Kubicek et al. as mentioned in this paper proposed a blanket SMT process that does not require a photo to protect the pMOS by selecting a hydrogen-rich SiN film.
Proceedings ArticleDOI
Benchmarking time-dependent variability of junctionless nanowire FETs
B. Kaczer,Gerhard Rzepa,J. Franco,Pieter Weckx,Adrian Chasin,V. Putcha,Erik Bury,Marko Simicic,Ph. J. Roussel,Geert Hellings,Anabela Veloso,Ph. Matagne,Tibor Grasser,D. Linten +13 more
TL;DR: In this article, the variability of junctionless gate-all-around nanowire pFETs is studied through measurements and simulations, and it is concluded that the time dependent variability of our JL GAA NW p-FET is comparable to previously measured pFinFET, provided that other sources of variability are suppressed.