Anabela Veloso

TL;DR: In this paper, stress enhanced mobilities for n-and p-FinFETs with both Si and Ge channels for the 14 nm node and beyond are investigated. But the authors focus on the Si channel and not the Ge channel.

TL;DR: In this article, the floating-body-RAM sense margin and retention time dependence on the gate length were investigated in UTBOX devices using BJT programming combined with a positive back bias (so-called V th feedback).

TL;DR: In this paper, gate-last technology for improved effective work function tuning with ∼200meV higher p-EWF at 7A EOT, ∼2x higher f max performance, and further options for channel stress enhancement than with gate-first by taking advantage of the intrinsic stress of metals and gate height dependence.

TL;DR: In this article, the Ni silicide phases and morphology in Ni fully silicided gates were investigated for varying deposited Ni to Si thickness ratios and rapid thermal processing conditions, and the presence of NiSi"2, NiSi, Ni"3Si", Ni"1Si"1"2 and Ni" 3Si as predominant phases was observed for increasing Ni-to-Si thickness ratios.

TL;DR: This work shows that interconnect delay variability of a wire of average length in SoCs can overwhelm device variability, and suggests a new device architecture with a smaller footprint as VFET would effectively lower the BEOL variability by shortening the wirelength and help SRAM bit cells to follow 50% area scaling trend.