An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Considerations for Ultimate CMOS Scaling

This survey deals with 1/f noise in homogeneous semiconductor samples. A distinction is made between mobility noise and number noise. It is shown that there always is mobility noise with an /spl alpha/ value with a magnitude in the order of 10/sup -4/. Damaging the crystal has a strong influence on /spl alpha/, /spl alpha/ may increase by orders of magnitude. Some theoretical models are briefly discussed none of them can explain all experimental results. The /spl alpha/ values of several semiconductors are given. These values can be used in calculations of 1/f noise in devices. >

1/f Noise Sources

The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current becomes too large. This led to the replacement of SiO2 by a physically thicker layer of a higher dielectric constant or ‘high-K’ oxide such as hafnium oxide. Intensive research was carried out to develop these oxides into high quality electronic materials. In addition, the incorporation of Ge in the CMOS transistor structure has been employed to enable higher carrier mobility and performance. This review covers both scientific and technological issues related to the high-K gate stack – the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging to achieve the thinnest oxide thicknesses. The high K oxides were implemented in conjunction with a replacement of polycrystalline Si gate electrodes with metal gates. The strong metallurgical interactions between the gate electrodes and the HfO2 which resulted an unstable gate threshold voltage resulted in the use of the lower temperature ‘gate last’ process flow, in addition to the standard ‘gate first’ approach. Work function control by metal gate electrodes and by oxide dipole layers is discussed. The problems associated with high K oxides on Ge channels are also discussed.

/pdf/high-k-materials-and-metal-gates-for-cmos-applications-4hs77i3c4a.pdf

High-K materials and metal gates for CMOS applications

https://www.iue.tuwien.ac.at/pdf/ib_2011/JB2011_Grasser_5.pdf

Stochastic charge trapping in oxides: From random telegraph noise to bias temperature instabilities

This paper shows an experimental analysis of the zero-temperature coefficient (ZTC) bias point of vertically stacked gate-all-around nanosheet pMOS devices (GAA-NS) for different channel lengths (L), in linear and saturation regions. The gate voltage at ZTC point (V ZTC ) experimental results are compared with the values obtained by analytical model (CM-ZTC model) in order to evaluate the behavior of the ZTC of the GAA-NS pMOS transistors. The comparison between the data from the CM-ZTC model and the experimental values resulted a difference smaller than 7% when operating in linear region, which means that the behavior of GAA-NS in ZTC point can be well described through the mobility degradation and threshold voltage shift basic models like in planar fully depleted SOI devices. However, in saturation region the difference increases substantially due to the high series resistance, and in case of 28 nm channel devices, due to the short-channel effect (SCE), which is not considered in the analytical model. But the experimental V ZTC in saturation region does not change too much (|V ZTZ | ≅ 0.75V with standard deviation ≅ 0.06V) for all studied devices (from 200 nm down to 28 nm channel lengths) which means that the GAA-NS is a trusted device for analog circuits biased at ZTC point.

Analysis of the ZTC-Point for Vertically Stacked Nanosheet pMOS Devices

In this work, the impact of the channel doping density on the low-frequency noise of silicon Gate-All-Around (GAA) Vertical Nanowire (VNW) pMOSFETs on Silicon-on-Insulator (SOI) substrates will be described and discussed. It is demonstrated that the dominant fluctuation mechanism of the 1/f noise in the subthreshold regime changes from number (Δn) to mobility (Δμ) fluctuations with increasing p-type doping density of the silicon nanowires. At the same time, the lowest input-referred voltage noise Power Spectral Density is observed for an intermediate boron concentration in the nanowire of 5 × 1018 cm−3. 

Impact of the Channel Doping on the Low-Frequency Noise of Gate-All-Around Silicon Vertical Nanowire pMOSFETs

Low frequency noise study is performed at deep cryogenic temperature of 10 K in p-channel gate-all-around (GAA) nanowire (NW) FETs. As expected, the carrier number fluctuations mechanism explains the flicker noise origin for conventional fixed applied drain bias. At very low applied drain biases step-like effects impact the drain current transfer characteristics. Noise measurements performed at a fixed very low drain voltage as a function of the applied gate bias show that the gate voltage flicker noise behavior follows a I DS 3 / 2 / g m 2 law. It was already proved that this dependency may be modeled considering classical transport theory, in the framework of the mobility fluctuations mechanism from Coulomb scattering interactions. The noise measurements performed at fixed gate voltage as a function of the applied drain bias show that the gate voltage 1/f noise levels present a deviation from the I DS 3 / 2 / g m 2 law. In order to explain this behavior, an improved model is proposed mainly considering some additional hypotheses: the inversion charge dependency on the applied drain bias and the fact that the impact of the drift component of the drain current may be neglected when measurements are made at low fixed gate voltage biases for very low applied drain voltages. The results show that for the lower drain biases considered in this work, the flicker noise behavior may be explained using physical-based models derived from classical transport considerations for cryogenic temperatures by the mobility fluctuations mechanism originating from Coulomb scattering interactions. This may be surprising, and suggests that even if step-like effects impact the DC measurements, there is a polarization interval in which they do not impact the 1/f noise.

Improved physics-based analysis to discriminate the flicker noise origin at very low temperature and drain voltage polarization

An original detailed methodology has been demonstrated for comparing short channel device performances in HfSiON and two different MG integration schemes. In HfSiON there is substantial room for improvement towards shorter metallurgical gate length and lower series resistance to obtain the desired ION-IOFF performances.

Anabela Veloso

Papers

Analysis of the ZTC-Point for Vertically Stacked Nanosheet pMOS Devices

Impact of the Channel Doping on the Low-Frequency Noise of Gate-All-Around Silicon Vertical Nanowire pMOSFETs

Improved physics-based analysis to discriminate the flicker noise origin at very low temperature and drain voltage polarization

Line width dependent mobility in high-k a comparative performance study between FUSI and TiN

Thermal and plasma treatments for improved (Sub-)1nm EOT RMG high-k last devices