An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Considerations for Ultimate CMOS Scaling

This survey deals with 1/f noise in homogeneous semiconductor samples. A distinction is made between mobility noise and number noise. It is shown that there always is mobility noise with an /spl alpha/ value with a magnitude in the order of 10/sup -4/. Damaging the crystal has a strong influence on /spl alpha/, /spl alpha/ may increase by orders of magnitude. Some theoretical models are briefly discussed none of them can explain all experimental results. The /spl alpha/ values of several semiconductors are given. These values can be used in calculations of 1/f noise in devices. >

1/f Noise Sources

The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current becomes too large. This led to the replacement of SiO2 by a physically thicker layer of a higher dielectric constant or ‘high-K’ oxide such as hafnium oxide. Intensive research was carried out to develop these oxides into high quality electronic materials. In addition, the incorporation of Ge in the CMOS transistor structure has been employed to enable higher carrier mobility and performance. This review covers both scientific and technological issues related to the high-K gate stack – the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging to achieve the thinnest oxide thicknesses. The high K oxides were implemented in conjunction with a replacement of polycrystalline Si gate electrodes with metal gates. The strong metallurgical interactions between the gate electrodes and the HfO2 which resulted an unstable gate threshold voltage resulted in the use of the lower temperature ‘gate last’ process flow, in addition to the standard ‘gate first’ approach. Work function control by metal gate electrodes and by oxide dipole layers is discussed. The problems associated with high K oxides on Ge channels are also discussed.

/pdf/high-k-materials-and-metal-gates-for-cmos-applications-4hs77i3c4a.pdf

High-K materials and metal gates for CMOS applications

https://www.iue.tuwien.ac.at/pdf/ib_2011/JB2011_Grasser_5.pdf

Stochastic charge trapping in oxides: From random telegraph noise to bias temperature instabilities

The work investigates the impact of plasma nitridation process parameters upon the physical properties and upon the electrical performance of sub-15 A plasma nitrided gate dielectrics. The nitrogen distribution and chemical bonding of ultra-thin plasma nitrided films have been investigated using XPS. It is shown that N-Si3 bonds are dominant in the ultra-thin plasma nitrided films, and that O2=N-Si bonding configuration is observed when no PNA is applied after the plasma nitridation. The EOT reduction due to an increase of N in the film is not a monotonic increasing function of the DPN time. It seems that there is an optimum N concentration for a given thickness of the base oxide that enables the continued down scaling of DPN base dielectrics.

Plasma nitridation optimization for sub-15 A gate dielectrics

Spacer Length and Tilt Implantation Influence on Scaled UTBOX FD MOSFETs

As will be shown, the architecture and gate stack processing have a clear impact on the low-frequency noise performance of horizontal nanowire (NW) transistors. In this work, the noise of single nanowires is compared with stacked devices. For single NWs, junctionless (JL) transistors tend to exhibit a better noise performance than inversion mode (IM) counterparts. In addition, a clear impact of the type of metal gate (MG) on the 1/f noise Power Spectral Density (PSD) will be demonstrated.

Impact of Device Architecture and Gate Stack Processing on the Low-Frequency Noise of Silicon Nanowire Transistors

In this work, DC and low frequency noise measurements are performed on n-channel gate all around (GAA) vertically stacked silicon nanosheets (NS) at room and liquid nitrogen temperature. Principal static (DC) parameters such as low field mobility, access resistance and subthreshold swing are estimated. Preliminary low frequency noise studies reveal that the 1/f noise may be explained by the carrier number fluctuations mechanism at room and liquid nitrogen temperature operation.

Low temperature investigation of n-channel GAA vertically stacked silicon nanosheets

The influence of different spacer lengths and tilt-implantation on underlapped devices compared to the standard S/D junctions (with Lightly Doped Drain – LDD) on fully depleted (FD) SOI MOSFETs with Ultra-Thin Buried Oxide (UTBOX) at room and high temperatures is explored. It is shown that devices with longer spacers and no LDD implantation increase the underlap region between the gate edge and the S/D regions, increase the immunity to short channel effects and improve the analog performance even at high temperatures. However, the lateral dopant diffusion can reduce or suppress the underlap formation, mainly for smaller spacer length. Tilt-implanted devices exhibit the same trend as the devices with LDD. The angled implantation favors the dopant diffusion into the underlap regions, which degrades the transistor performance.

Anabela Veloso

Papers

Plasma nitridation optimization for sub-15 A gate dielectrics

Spacer Length and Tilt Implantation Influence on Scaled UTBOX FD MOSFETs

Impact of Device Architecture and Gate Stack Processing on the Low-Frequency Noise of Silicon Nanowire Transistors

Low temperature investigation of n-channel GAA vertically stacked silicon nanosheets

Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation