E
Eric Karl
Researcher at Intel
Publications - 48
Citations - 1956
Eric Karl is an academic researcher from Intel. The author has contributed to research in topics: Static random-access memory & Voltage. The author has an hindex of 20, co-authored 42 publications receiving 1759 citations. Previous affiliations of Eric Karl include University of Michigan.
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Proceedings ArticleDOI
A 14nm logic technology featuring 2 nd -generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size
Sanjay Natarajan,M. Agostinelli,S. Akbar,M. Bost,A. Bowonder,V. Chikarmane,S. Chouksey,A. Dasgupta,K. Fischer,Q. Fu,Tahir Ghani,M. Giles,S. Govindaraju,R. Grover,W. Han,D. Hanken,E. Haralson,M. Haran,M. Heckscher,R. Heussner,Pulkit Jain,R. James,R. Jhaveri,I. Jin,Hei Kam,Eric Karl,C. Kenyon,Mark Y. Liu,Y. Luo,R. Mehandru,S. Morarka,L. Neiberg,Paul A. Packan,A. Paliwal,C. Parker,P. Patel,R. Patel,C. Pelto,L. Pipes,P. Plekhanov,M. Prince,S. Rajamani,J. Sandford,Sell Bernhard,Swaminathan Sivakumar,Pete Smith,B. Song,K. Tone,T. Troeger,J. Wiedemer,M. Yang,Kevin Zhang +51 more
TL;DR: In this paper, a 14nm logic technology using 2nd-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described.
Proceedings ArticleDOI
A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active V MIN -enhancing assist circuitry
Eric Karl,Yih Wang,Yong-Gee Ng,Zheng Guo,Fatih Hamzaoglu,Uddalak Bhattacharya,Kevin Zhang,Kaizad Mistry,Mark T. Bohr +8 more
TL;DR: A high-performance, voltage-scalable 162Mb SRAM array is developed in a 22nm tri-gate bulk technology featuring 3rd-generation high-k metal-gate transistors and 5th-generation strained silicon to address process variation and fin quantization at 22nm.
Proceedings ArticleDOI
Compact In-Situ Sensors for Monitoring Negative-Bias-Temperature-Instability Effect and Oxide Degradation
TL;DR: Two compact structures are introduced to digitally quantify the change in performance and power of devices undergoing NBTI and defect-induced oxide breakdown and are amenable to use in a standard-cell design with low area and power overhead.
Journal ArticleDOI
ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon
TL;DR: This article presents a broad vision of a new cohesive architecture, ElastIC, which can provide a pathway to successful design in unpredictable silicon and incorporates several novel concepts in these areas.
Journal ArticleDOI
A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation
Hyunwoo Nho,Pramod Kolar,Fatih Hamzaoglu,Yih Wang,Eric Karl,Yong-Gee Ng,Uddalak Bhattacharya,Kevin Zhang +7 more
TL;DR: An adaptive, dynamic SRAM word-line under-drive (ADWLUD) scheme that uses a bitcell-based sensor to dynamically optimize the strength of WLUD for each die is introduced.