Showing papers by "Hafez Walid M published in 2009"

A 32nm SoC platform technology with 2 nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications

Abstract: A leading edge 32nm high-k/metal gate transistor technology has been optimized for SoC platform applications that span a wide range of power, performance, and feature space. This technology has been developed to be modular, offering mix-and-match transistors, interconnects, RF/analog passive elements, embedded memory, and noise mitigation options. The low gate leakage of the high-k gate dielectric enables the triple transistor architecture to support ultra low power, high performance, and high voltage tolerant I/O devices concurrently. Embedded memories include high density (0.148 um2) and low voltage (0.171 um2) SRAMs as well as secure OTP fuses. Analog/RF SoC features include high precision, high quality passives (resistors, capacitors and inductors) and deep-nwell noise isolation.

Flash cell with integrated high-k dielectric and metal-based control gate

Abstract: A semiconductor device is described having an integrated high-k dielectric layer and metal control gate. A method of fabricating the same is described. Embodiments of the semiconductor device include a high-k dielectric layer disposed on a floating gate. The high-k dielectric layer defines a recess. A metal control gate is formed in the recess.