Showing papers by "Herman Maes published in 2005"

Matching Properties of Deep Sub-Micron MOS Transistors

Abstract: Introduction: Matching analysis. Importance for circuit design. State of the art. Research objectives. Outline of this book.- Measurement and Modeling of Mismatch. Measurement setup. Experimental setup. Modeling of mismatch in the drain current. Width and length dependence. Example: Yield of a current-steering D/A converter. Conclusions.- Parameter Extraction. Extraction methods. Experimental setup. Comparison of extraction methods. Future issues. Conclusions.- Physical Origins of Mosfet Mismatch. Basic operation of the MOS transistor. Mismatch in the drain current. Physical origins of fluctuations. Conclusions.- Technological Aspects. Technology descriptions. Impact of the gate. Impact of the halo implantation. Comparison of di(R)erent CMOS technologies. Alternative device concepts. Conclusions.- Impact of Line-Edge Roughness. Characterization of line-edge roughness. Modeling the impact of line-width roughness. Experimental investigation of the impact of LWR. Prediction of the impact of LWR and guidelines. Conclusions.- Conclusions, Future Work and Outlook. Conclusions. Future work.- Outlook.

Scaling CMOS: Finding the gate stack with the lowest leakage current

Abstract: In order to reduce the gate leakage current, high-k gate dielectrics are expected to replace SiO2 in future CMOS generations. Many of these novel dielectrics are stacks of a thin SiO2 and a high-k layer. We present a theoretical study that aims at identifying the combination of the stack architecture and high-k material with the lowest leakage current. In the first part of this work the leakage current through high-k double stacks with various thicknesses, materials and gate electrodes is calculated assuming tunneling only. We discuss the difference between gate and substrate injection and show quantitatively the impact of interfacial layer thickness, barrier height, k-value and the work function of the gate material on the tunneling current. In the second part the material properties are no longer considered to be independent and with the universal relation between k-value and barrier height introduced, we are able to identify what material suits best all requirements. The leakage current is calculated for different EOTs and we demonstrate that if all dielectrics follow this universal relation, for a fixed thickness there exists one material, which gives a minimum gate leakage current. It is concluded that even for sub 1 nm EOT devices the k-value has not to exceed ∼25 and ZrO2 or HfO2 come closest to the ideal high-k if only leakage current issues are considered.

Abrupt breakdown in dielectric/metal gate stacks: a potential reliability limitation?

Abstract: In downscaled poly-Si gate MOSFET devices reliability margin is gained by progressive wearout. When the poly-Si gate is replaced with a metal gate, the slow wearout phase observed in ultrathin SiON and HfSiON dielectrics with poly-Si gate disappears, and with it, the reliability margin. We demonstrate for several combinations of dielectric and gate materials that the large abrupt current increase (/spl Delta/I) as compared to poly-Si is not likely due to process issues, but is an intrinsic property of the dielectric/metal gate stack. The occurrence of large /spl Delta/I is a potential limitation for the reliability of metal gate devices.

Dependency of the properties of SrxBiyTa2O9 thin films on the Sr and Bi stoichiometry

Abstract: In this study the properties of ferroelectric SBT thin films crystallized at 700 °C have been investigated as function of the Sr and Bi stoichiometry. A matrix of 130 nm Sr x Bi y Ta 2 O 9 films with 0.7 ≤ x ≤ 1.0 and 2.0 ≤ y ≤ 2.4 has been realized by metal-organic spin-on deposition technique on Pt/IrO 2 /Ir/TiAlN/SiO 2 /Si substrates. Within this composition range, we found that the ferroelectric properties peak into a narrow window of 0.8 ≤ x ≤ 0.9 and y ∼ 2.25 with Pr and Ec of 6.5 μC/cm 2 and 50 kV/cm, respectively (at 2.5 V). Outside this composition window, the Pr decreases while the hysteresis loop becomes slanted. For some Sr/Bi-ratios even no ferroelectricity was achieved. 2Ec-tendencies were seen as function of the x / y -ratios, too. Examination of the microstructure of the films by scanning electron microscopy showed that film grain size increased with decreasing Sr-deficiency and that nucleation increased with increasing Bi-excess. At high Sr-deficiency and low Bi-excess, no complete crystallization of the SBT film occurs. From the film morphology, also different phases can be discriminated. X-ray diffraction analysis showed a strong correlation of the film orientation with the film composition. While our results show a clear correlation of Pr, film grain size and orientation with composition, further investigations are required to clarify the relation of the hysteresis parameters with film orientation.

A comprehensive study of boron and carbon diffusion models in SiGeC heterojunction bipolar transistors

Abstract: Three different diffusion models in SiGeC layers are compared and evaluated for their implementation in the process simulation program Taurus TSUPREM-4™ (TSUPREM-4 computer code from Synopsys, Inc.). The models considered in the evaluation are verified for actual process conditions of modern SiGeC heterojunction bipolar transistors in bipolar complementary metal-oxide-semiconductor technologies. Rapid thermal annealing temperatures in the range of 1020–1070°C were used for the present study. In this study it is shown that the compared models are similar to each other despite the different physical approach. A common set of coefficients was used for the simulations of the three models under study.