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Jean-Michel Portal

Researcher at Centre national de la recherche scientifique

Publications -  145
Citations -  2335

Jean-Michel Portal is an academic researcher from Centre national de la recherche scientifique. The author has contributed to research in topics: Resistive random-access memory & Artificial neural network. The author has an hindex of 25, co-authored 136 publications receiving 2047 citations. Previous affiliations of Jean-Michel Portal include Alternatives & Aix-Marseille University.

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Journal ArticleDOI

Simulation of Single and Multi-Node Collection: Impact on SEU Occurrence in Nanometric SRAM Cells

TL;DR: In this article, the authors compared the relative influence of nMOS and pMOS sensitive zones within the cell by means of electrical simulations and discussed the impact on the definition of an event criterion.
Proceedings ArticleDOI

Definition of an innovative filling structure for digital blocks : the DFM filler cell

TL;DR: This paper presents a DFM filler cell solution that takes into account a large amount of problems that can be encountered at many steps of the production flow, such as lithography or planarity variations, while other kinds of filler cells only solve density problems.
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RRAM-based FPGA for “Normally Off, Instantly On” applications

TL;DR: This paper proposes to integrate non-volatile resistive memories in the configuration cells and registers in order to instantly restore the FPGA context and shows that if the circuit is in the ‘ON’ state for less than 42% of time, non-Volatile FPGa starts saving energy compared to classical FPGAs.
Proceedings ArticleDOI

Impact of hump effect on MOSFET mismatch in the sub-threshold area for low power analog applications

TL;DR: In this paper, two narrow parasitic MOS are introduced in parallel with the main device to simulate matching degradation in sub-threshold mode, in case of hump effect, have to be considered.
Proceedings ArticleDOI

Analyzing the test generation problem for an application-oriented test of FPGAs

TL;DR: The objective of this paper is to generate an application-oriented test procedure to be used by a FPGA user in a given application and it is demonstrated that test pattern generation can be significantly accelerated by removing most of the AC-redundant faults.