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Jean-Michel Portal

Researcher at Centre national de la recherche scientifique

Publications -  145
Citations -  2335

Jean-Michel Portal is an academic researcher from Centre national de la recherche scientifique. The author has contributed to research in topics: Resistive random-access memory & Artificial neural network. The author has an hindex of 25, co-authored 136 publications receiving 2047 citations. Previous affiliations of Jean-Michel Portal include Alternatives & Aix-Marseille University.

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Journal ArticleDOI

Resistive Switching Memory Architecture Based on Polarity Controllable Selectors

TL;DR: This paper presents two innovative PCT-based bitcells and proposes an extensive study of their functionality, physical design considerations, and performances in read and write operations compared to CMOS-based 1T1R and 2T1 R bitcells.
Proceedings ArticleDOI

High voltage recycling scheme to improve power consumption of regulated charge pumps

TL;DR: An ultra-low power regulated charge pump system based on charge recycling between a tank capacitor and the charge pump output load capacitor is presented and simulation results show a maximum current reduction of about 38% compared to a conventional regulatedcharge pump system.
Journal ArticleDOI

Phenomenological modelling of non-volatile memory threshold voltage shift induced by nonlinear ionization with a femtosecond laser.

TL;DR: By comparing the evolution of the electrical characteristics of Flash cells under the cumulative effect of repeated femtosecond laser pulses with first-order physical considerations and TCAD (Technology Computer Aided Design) simulations, the role of the carriers created by nonlinear ionization on the functionality of the structures is established.
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Suppressing the memory state of floating gate transistors with repeated femtosecond laser backside irradiations

TL;DR: In this article, the authors demonstrate that femtosecond laser pulses with intensity above the two-photon ionization threshold of crystalline silicon induce charge transport through the tunnel oxide in floating gate Metal-Oxide-Semiconductor transistor devices.
Proceedings ArticleDOI

High density emerging resistive memories: What are the limits?

TL;DR: Two physical IRdrop models for crosspoint and Vertical-RRAM architectures are introduced and it is shown that both periphery overhead and IRdrop limit the crosspoint architecture under 50nm of half pitch.